CMR Institute of Technology, Bangalore

Department: Electronics & Communication

Semester: 07 Section(s): B & C Lectures/week: 04
Subject: VLSI Design Code: 18EC72
Course Instructor: Dr.Venkatesh M
Course duration: Sept 2022 –Dec 2022
Google Classroom Link: https://meet.google.com/yrc-ruks-qhi (7B-SECTION)
https://meet.google.com/hmv-knmi-cat (7C-SECTION)

Assignment-3 Issue Date: 24/12/2022 Submission Date: 30/12/2022

Blooms
Q.No Questions CO
Level

Calculate the Elmore delay for 3-input NAND and NOR gate if output
1 CO3 L3
is driving 'h' identical gates.
Explain the linear delay model for a gate. Use the linear
delay model to estimate the delay in picoseconds of the fanout-of-4
2 CO3 L3
(FO4) inverter Assume the inverter is constructed in a 65 nm process
with τ = 3 ps.
Calculate the delay of multistage circuit shown below:

3 CO3 L3

Define a) Logical effort, b) Parasitic delay. Find Logical effort and

4 Parasitic delay of 2 input NAND and NOR gate circuits. Also CO3 L3
calculate the total delay.
Realize the y = + using a) Static CMOS, b) Pseudo nMOS,
5 CO3 L3
c) CVSL.
Using AND-OR-INVERT logic draw the circuit for Y = . +
and find the logical effort for each input A,B,C and also the parasitic
6 CO3 L3
delay. Calculate the delay of the gate if output Y is driving four unit
sized inverters.
Explain the operation of dynamic shift register with necessary CO4
7 L2
diagrams.
Realize the 2 to 1 mux using a) Static CMOS, b) Pseudo nMOS, CO3
8 L3
c) CVSL and d) CPL.
Describe the construction and working principle of Conventional CO4
9 L2
CMOS Latches.
With necessary circuit diagrams, explain the operation of static and CO4
10 L2
dynamic flip-flops.
 Explain Cascode Voltage Switch Logic (CVSL).Also realize two input CO3
11 L2
AND/NAND using CVSL.
Compare the logical efforts of the following gates with the help of CO3
12 L2
schematic diagrams. (i) 2- input NAND gate (i) 3- input NOR gate.
Explain (i)Psedo nmos (ii) Ganged CMOS with necessary circuit CO3
13 L2
examples.
14 Describe in detail about skewed gates with an example. CO3 L2
With necessary circuit diagrams,explain resettable latches with CO4
15 L2
(i)Synchronous reset (ii) Aysnchronous reset

Course Outcomes
1. Impart knowledge of MOS transistor theory and CMOS technologies
2. Learn the operation principles and analysis of inverter circuits
3. Design combinational, sequential and dynamic logic circuits as per the requirements
4. Infer the operations of semiconductor memory circuits
5. Demonstrate the concepts of CMOS testing.