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    Pranavkumar Patil
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    This document summarizes the structural description of a system in VHDL and Verilog. In VHDL, it defines the system entity with ports, then declares xor2 and and2 components with their ports. It maps the component ports to the entity ports using port map. In Verilog, it defines the system module with inputs and outputs, then instantiates an xor gate assigning its outputs and a and gate assigning its output, without using components.

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    This document summarizes the structural description of a system in VHDL and Verilog. In VHDL, it defines the system entity with ports, then declares xor2 and and2 components with their ports. It maps the component ports to the entity ports using port map. In Verilog, it defines the system module with inputs and outputs, then instantiates an xor gate assigning its outputs and a and gate assigning its output, without using components.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    21 views1 page

    Untitled

    Uploaded by

    Pranavkumar Patil
    This document summarizes the structural description of a system in VHDL and Verilog. In VHDL, it defines the system entity with ports, then declares xor2 and and2 components with their ports. It maps the component ports to the entity ports using port map. In Verilog, it defines the system module with inputs and outputs, then instantiates an xor gate assigning its outputs and a and gate assigning its output, without using components.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    of 1

    Listing 1.4?

    Pure Structural Description�VHDL and Verilog

    VHDL Structural Description


    entity system is

    port (a, b : in bit;


    sum, cout : out bit);
    end system;

    architecture struct_exple of system is

    component xor2
    --The above statement is a component statement
    port(I1, I2 : in bit;
    O1 : out bit);
    end component;
    component and2
    port(I1, I2 : in bit;
    O1 : out bit);
    end component;
    begin
    X1 : xor2 port map (a, b, sum);
    A1 : and2 port map (a, b, cout);
    end struct_exple;

    Verilog Structural Description


    module system(a, b, sum, cout);
    input a, b;
    output sum, cout;
    xor X1(sum, a, b);
    //The above statement is EXCLUSIVE-OR gate
    and a1(cout, a, b);
    //The above statement is AND gate
    endmodule

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