TOSHIBA TD62650,651,652F TOSHIBA BIPOLAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TD62650F, TD62651F, TD62652F 5V POWER SUPPLY & SUPPLY MONITORING + COMMUNICATIONS IC The TD6265xF series covers products developed for use in microcomputer systems applicable to automatic vending machines. They produce an output voltage of 5V+0.5V without need for adjustment, through their accurate ™ reference voltage and amplifier circuit. > The 5V section can reset the system by outputting reset ~ al f ? reset signal when Eau signals at power-on, and also output a reset signal wher QUE’ the 5V output voltage drops below the specified 925% (T1062650F /652F) or 85% (TD62651F) because of external disturbances or other problem It also incorporates a watchdog timer for self-diagnosing the system. When the system malfunctions, the IC Weight : 0.639 (Typ.) generates reset pulses intermittently to prevent the system from running away. The interface section incorporates three serial ports corresponding to the typical 24-V 4800bps system in microcomputers. 50P30-P-375-1.00, FEATURES © Accurate output 5V£0.25V © Output PNP Tr incorporated Current capacity ; 300mA (max) ‘© Power-on Reset timer incorporated ‘© Watchdog timer incorporated © Small flat package sealing MFP30 pin (1mm pitch) ssron:eaas @ TOSHIBA is continually working to Improve the quality and the reliability of fs products. Nevertheless, semiconductor devices in general can malfunction or Tail due to thelr inherent electrical sensitivity and vulnerability to prysical stress I's the responsiblity of the buyer, when utlizing TOSHIBA products, to observe standards of safely, and to avoid Situations Im which a malfunction ‘or failure of @ TOSHIBA product could. cause loss of human life, bodily injury oF Gamage to property. In developing your designs, please ensure thet TOSMIBA products are’ used within spectlied ‘operating ranges. se set forth im the ‘most recent products specifications. Also, please Keep in mind ‘the precautions nd conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. ihe prec described in ws document are subject to foreign exchange and foreign trade contol lows ‘The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed. by TOSHIBA CORPORATION for ary Infringements of intellectual property or ‘other rights of the third Darties which may result from its use. No license Is granted by Implication oF otherwise under any intelectual roperty or other fights of TOSHIBA CORPORATION or others @ The information contained herein is subject to change without notice 7998-05-15 1/17TOSHIBA TD62650,651,652F © Difference 1 CHARACTERISTIC | TD62650/652F Reset Detecting svaz% Voltage PIN CONNECTION TD62651F 5v/85% + Difference 2 Time setting resistance 22k for power-on reset! watchdog timer, and PULL resistance of 4.7k2 for RESET pin. TD62650F TD62651F ‘1062652F Builtin None None 7998-05-15 2/17TOSHIBA TD62650,651,652F ‘TD62650F BLOCK DIAGRAM 5V POWER SUPPLY +SUPPLY MONITORING ® one Veen co 20) eet INTERFACE Ss ie OO 5 ~ om = ssw ss ew fe Ot - z ate = 3016) wsso/60 = omoo fg oor —= @ o aan < = smo — RK — _ MsAXD = ~® > :595ynem puss ru nw[ D0: 5:0 Stem Open Caer Po: 244 System Open clef >: 54 Sse Pt Pl Bue 7998-05-15 3/17TOSHIBA TD62650,651,652F ‘1062651F/ TD62652F BLOCK DIAGRAM 5V POWER SUPPLY +SUPPLY MONITORING our BAS Vesgur scx x 1 ee ase ote) for oe ecw co 2) INTERFACE > —_@« — om is oO < ae: = ss = wns een > sso ~ ake) — 0160 ss0160 = — ser oe sm a => eovour $8 9 rou = @ o @ sno — sexo > 59 synem pus pu nw[>>0: 50 Stem Oper Cale PO: 264 System Open Clea: 54 Sst Ph Pl Bur 7998-05-15 4/17TOSHIBA TD62650,651,652F INTERFACE INPUT / OUTPUT CIRCUITS Et © Veen v1ss0160 ws @) smn @) (@ 1x0 wssen 7998-05-15 5/17TOSHIBA TD62650,651,652F PIN FUNCTION BIN pin NAME PIN FUNCTION 1 [GND GND pin for SV power supply and supply monitoring. 2_| ComP [Phase compensation pin for output stabilization Power supply pin for internal circuit. The output voltage can also be detected 3 Vecin at this pin. Output pin for builtin Power Tr, having a current capacitance of 300mA (max) 4 | Vecour _ It is also used as an output pin for SV constant power supply through shorting with Vecin pin. Connected to the base of an external PNP transistor so that the output voltage is stabilized. Current design suitable for load capacities is thus possible. 5 | our Since the recommended lout current is SmA, an output current of 300mA is assured if the external transistor has an hFE of 60 When the internal transistor is used, it can be opened, Power supply starting pin. The starting current is supplied through @ resistor to 6 | ems which the input voltage is applied. When Vccin rises above 3.0V, the starting current is absorbed in the internal circuit ; instead, lour is supplied via VeciN. 7_| Veez Power supply pin for the 24-V system 8 | sisyn Input pin for the 24-V system interface. Pull-up resistor 47K0. is incorporated at Vec2 pin. 9 | soveo Input pin for 24-V system interface. Pull-up resistor 47KQ2 is incorporated at Vec2 pin. 70_|_MSSYN [Output pin for the 24-V system open collector. Input pin for the 5-V system Push/Pull inverter. Pull-up resistor 30K] is incorporated at Vccin pin. LED lighting pin for the 8 system open collector. 6802 limiting resistor is 11 | ceuout 12 | Leo incorporated 13_| TxD Output pin for the 24-V system open collector. va | RxD Input pin for the 24-V system interface. Pull-up resistor 47K. is incorporated at the Vcc pin. 15 | PG GND pin for the 5-V/24-V system interfaces. v6 || suxp Output pin for the 5-V system open collector. Pull-up resistor 4.7kI) is incorporated at the Vccin pin. 17_|_MSRXD___|Output pin for the 5-V system Push-Pull buffer. ve | mstxp _|IMPUt pin for the 5-V system interface, for input at LED (12 pin) and TXD (13 pin) pins. 79 |_TXDOUT _ [Output pin for the 5-V system Push/Pull inverter (CPUOUT + 11 pin. 20_|_SYNIN Input pin for the 5-V system interface. Output pin for the 5-V system open collector. Pull-up resistor 4.7kQ is incorporated at VcciN pin. 22_| 5150/60 [Output pin for the 5-V system Push/Pull buffer 23_|_SYN Output pin for the 5-V system Push-Pull buffer. Output pin for the 5-V system open collector. Pull-up resistor 4.7kQ incorporated at Vccin pin. 25 | eck Output pin for the 5-V system Push-Pull buffer. 21 | mss0/60 24 | HNSYN 1998-05-15 6/17TOSHIBA TD62650,651,652F BIN | pin NAME PIN FUNCTION 26 | cK Taput pin for watchdog timer. The pin is pulled up to Vccin W the Ic is used only as a power-on reset timer. y | mscex To input clock pulses, one-shot pulses can be generated for CK (26 pin) inputs at the rise edge. When the pin is not used, short it with GND. 2 | Te Time setting pin for the reset and watchdog timers. NPN transistor open-collector output. (1) The signal goes low when the output voltage drops below the specified 92% (TD62650/652) or 85% (651F) level. (2) The pin generates a reset signal that is determined by the external condenser connected to the TC pin. (3) The pin generates reset pulses intermittently if no clock is attached to the CK pin. This function can be used as a watchdog timer for microcomputers. Output voltage adjusting pin. The voltage will increase when a resistor is connected between ADJ and GND (1 pin). It can reduce the voltage when the resistor is inserted between ADJ and Vccin (3 pin). The voltage can be changed by @ maximum oft 1V. 29 | RESET 30 | ADs 7998-05-15 7/17TOSHIBA TD62650,651,652F TIMING CHART (TD62650F, TD62652F) CONSTANT VOLTAGE OF 5.4 . \ este | wo. Trst2) (Note) TD62650F incorporates RT (22k2 (Typ.) only for Cr:) rast) TIMING CHART (TD62651F) CONSTANT VOLTAGE OF 5.4 cos a - a otl.. este | wo. ot rast) 7998-05-15 8/17TOSHIBA TD62650,651,652F MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC | SYMBOL RATING UNIT PIN Weer T0a=35 V__|Weca, BIAS Ween, = 0457 Vv [Veen Vin2a Input Voltage | (Condition 1) | -0.4~vvec2+0.4| v__ | SLSYN, 50/60, RXD (Condition 2) = 0.4~30 ‘CPUOUT, MSCK, ADI, COMP, CK, Vins Tea Ween #04] V _ |rc, SyNIN, MSTXD Vourza =04=Ween +04 | _V__|MSSYN, TXD Wecour =0.4-Vaias +04 | V_ [Vecour. OUT VieD Output Voltage | (Condition 3) | -0.4~Vaias+04 | v |teD (Condition 4) =0.4~10 RESET, CCK, HNSYN, SYN, $150/60, Yours ToA-Weein +04] V | ss0/60, TXOOUT, MSRXD, SLTXO Tour 70 mA [OUT RESET 4 mA [RESET : CCK, SYN, SI50/60, TXDOUT, Output Current |!OUT Push/ Pull *4 march |sirxo Tours 70 mA/ch_[HNSYN, MS50760, LED, MSRXD Tour24, 24 mATch_[MSSYN, TXD Wecour 300 mA_[Vecout Power Dissipation | Pp (Note 5) 147 Ww. Operating F Tope ~40~ [Temperature i on 8s © Storage a Temperature Tso 55150 (Condition 1) WWec2=29.6V (Condition 2) VV¢c2>29.6V (Condition 3) Vgias=9.6V (Condition 4) Vgias>9.6V (Note 5) Board mounting time (50 x 50x 1.6mm, Cu = 30%) 7998-05-15 9/17TOSHIBA TD62650,651,652F DC ELECTRICAL CHARACTERISTICS (Ta =25°C, VccIN=5V) Interface Section, rs characrensmic | svwaou | pin [eR fresr conomion| win | tye, | wax | unit Veen | |= Vins x 70% (Note 1) = Input Voltage ViLS. _ _ _ 30% Vv Vin2a B = Wee +04) Vuza —_|Nte ?) =o [= 7 THS-1 320 W62 600 | ATR Wus-1 Wote 3) = 0 10 Tis? — [vinesv oe a Input cent HHS2 lore 7) — WES ‘so_| 690 [ 900 NH24 Vin =24V ww 1.6 24 mA/ch ta | NOt?) Vin=0V. 350 310 690 | A Vous Toi= = 2028 [Vee-01 — Ve Vous.2 ton= ama | veaw [fo Vousa | ote ToL = 202A = = On % Vous-2 - = oN Output Voltage - v Voss |iNote 5) — | — | os Vou te | LD — fo 1a TiN = 200,28 Voi2s _|(Note 6) eosin = - os Output RoL ted | LED | [Note 8) 520. 30 | 1000 | a Impedance Rows __[(ote 5) (Wote 9) 32 a7, 62 | ko Current ve —|wee=2v | — | 1 21 | ma Consumption 24 cc cca: 6 TLEAK2a_[(Note 6) Vou=24.0V = = 70 wn - nh Leakage Current Tye aks [(Note 4)| — [VoH=5V = = 70 | * Output Shorting (+) Vecin = 5.25V Current los (*) (Note 4)) — Vou =0V. = 17.5 = mA (*) Two outputs or more must not be shorted at the same time. Shorting duration must be limited to less than 1 second. (Note 1) CPUOUT, SYNIN, MSTXD (Note 5) HNSYN, MS50/60, MSRXD_ (Note 2) SLSYN, 50/60, RXD (Note 6) MSSYN, TXD (Note 3) SYNIN, MSTXD (Note 7) CPUOUT (Note 4) CCK, SYN, SL50/60, TXDOUT, SLTXD (Note 8) (VoL (@loL =5mA) VoL (@lon = 1mA)) ama (Note 9) 4V + (@IgH (VoH = 0V) - @ioH (VoH=4¥)) 7998-05-15 10/17TOSHIBA TD62650,651,652F DC ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vgias=7 to 17V, Ta= ~40 to 85°C) 5V power supply, supply monitoring section TEST] cHaracrenismic | symeot | ciR-| test conomon | mw | tye. | max | unrr ‘Output Voltage VecouT. — |Wecour=0.1A 475 50 5.25 Vv input Stability Vecout UNE | — |Vpias=7=35V = or [05 | % Load Stability Vecour toad | — [Wccour= = 150ma | — or [os | % FTemperature Coefficient Vecour t oor verre ‘Output Voltage Vou RESET — |lor=2mA = = 05, Vv Output Leakage a . _ fo 7 Cutput IteaK RESET Vpeser=7V 5] ua n HW Wre= dt 35V 3) Input Current Ite Woe a) 3 3 | na RESET “High” to aH Vic H ™ “ _ > ‘Low’ Vccin Threshold Voltage Vick RESET “Low” to __ | 40% x _ v re "High" Vein Input Current Tek. — [Vin =5V (Note 8) = 03 07 | mA Vecin via x70% — — Input Voltage — |(Note 4) v VL — | _ | veaw 30% Bo%K | THX | 95% x 7062650 /652F Reset Detecting Jy peser | Ven | Vea | Veaw | y Voltage cc 82% x | 85% x | 88% x 7062651F Veen | Vecin_ | Vecun Ron RESET TD62650F (Note 1) 3.2. 47 62 Output Impedance Fao te TD62650F (Note 1) 15 22 2 |‘ Current Ve __ [{Note 2) = 5 65 | a Consumption 5 ‘CCIN (Note 5) SS 115 15.0 oe Ipias, — |Veias =8V (Note 7) = 173 | 2.25 | ma TD62650F (Note 6) 15.4x CT [24.2 xCT|33.0xCT| ms Watchdog Timer Two - 9x | tix | 13x 7062651 /2F cTRT CTRT cTRT . ‘TD62650F (Note 6) 24.2xCT|35.2xCT|48.4xCT| ms aesee timer () Test (1) = Tax | 16x | 19x (Note 3) TD62651 / 2F crt cTRT Rt s Reset Timer (Note 3) [Trst (2) — [iNote 6) 300xCT | 600xcT|900xcT| _ms 1998-05-15 11/17TOSHIBA TD62650,651,652F TEST characteristic | syweot |cik-| Test conomion | win | tye, | max | unit Clock input Pulse width Twek = s|-~|-|* ‘Maximum Response |- — _ To Frequency 1 Max MSCK 2 kee ‘Maximum Response Frequency 2 fax ck ° kee Msck Pin Input tr MSCK — | (Note 9) - - 500 | ns | signal Rise Time Minimum Input Output Voltage Vou Vecout | — |IVccour= - - is} ov Difference (Note 1) 4V+(@loy (VoH=0V) - @loy (VoH=4V) (Note 2) Vgias=8V, Vccin-Vecour Short Open Collector 1/0: Open Push-Pull 1/0 Open MSCK Input Open (Note 3) Reset Timer (1) Power On Reset Time Reset Timer (2) Watchdog Reset Time (Note 4) MSCK, CK Pins (Note 5) HNSYN, MS50/60, MSRXD Pull / UP Resistance + CCK, SYN, SL50/60, TXDOUT, SLTXD Driving Current (Note 6) CT Unit (uF) (Note 7) Vecin, Vecour Open (Note 8) Only TD62651F, TD62652F (Note 9) Input Condition 5V ; 0 to 100% 1998-05-15 12/17TOSHIBA TD62650,651,652F ‘AC ELECTRICAL CHARACTERISTICS (Ta = 25°C) ‘CHARACTERISTIC/ TEST] output cuaracrenistic | Aut Conperion | SYMBOL ]IR-/ OMT | may | Tye, | ax | unit SISYN-CCK wir = [we = (Note 1) tpHL ote) [asp = SLSYN-SYN ‘iH =est— (Note 1) tpHL i a a SLSYN-HNSYN | *pL =est— (Note 1) 1pHL Mote) orp 50760-MS50760 | tpl = pest = (Note 1) tpHL (ote 8) orp — 50760-5150/60 | tpl = [os | = Propagation Delay _| (Note 1) *pHL (ote 4) 4s p = rime SYNINMSSYN _|_tpLH = [ot = (tpLH : 50%-50%, | (Note 2) wnt | — [3 orp tpHL : 50%-50%) CPUOUT-TXDOUT |_tpLH = 10 [| — (Note 2) {PHL Mote) Paap MSTXD-LED pil ‘Nowe = pest = (Note 2) ‘pHL ote 5) oa MSTXD-TXD tplH = oop = (Note 2) tHE (ote 3) =r = RXD-SLTXD ‘tli = ost — (Note 1) *pHL ote) [41s = RXD-MSRXD lH — est (Note 1) tpHL (ote 5) [orp = MS50760 = [est — 150760 = [po2t— LED. =e2t— MSSYN Saar Rise Time pour ‘ = {0} = fr + 10%-90% . - = =| « » SYN = ort = eck =ro2t— HINSYN = res t= SLTXD = [o2t— MSRXD =es t= 1998-05-15_13/17TOSHIBA TD62650,651,652F ‘CHARACTERISTIC/ TEST] ureuT CHARACTERISTIC | eur conpiTion | SYMBOL IRI onooy) MIN | TWP. | Max | UNIT MiS507 60 = orf 3150/60 = fos [— LED orf MSSYN = [orp — TXDOUT, os Fall Time TxD co - = orl — | us (tf: 90%-10%) SYN = os eck ss HNSYN = [orp — SUTXD fs MSRXD = orp = Input/Output Conditions © Input Condition (Note 1) 24-V system O.2us at 2 to 22-V (Note 2) 5-V system 0.148 at 30 to 70% © Output Conditions (Note 3) 24-V system: C,=50pF (Note 4) 5-V System (Note 5) 5-V System 1998-05-15 14/17TOSHIBA TD62650,651,652F APPLICATION CIRCUIT When using an external PNP transistor (ote2) vo ___@ +} (Note 1) When using the MSCK pin, short circuit the CK pin with GND. When using the CK pin, short circuit the MSCK pin with GND. (Note 2) C1 and C2 are necessary to absorb external noise, etc. Connect them as close to the IC as possible. C3 is used for phase correction, but this also must be connected as close to the IC as possible. We recommend that C4 be connected between OUT and VcciN. PRECAUTIONS for USING Utmost care is necessary in the design of the output line, Vec (VcciN, Vecour, BIAS, Vec2) and GND line since IC may be destroyed due to short-circuit between outputs, air contamination fault, or fault by improper grounding 1998-05-15 15/17TOSHIBA TD62650,651,652F When using a built-in PNP transistor vo @—} (Note 1) When using the MSCK pin, short the CK pin with GND. When using the CK pin, short the MSCK pin with GND. (Note 2) C1 and C2 are necessary to absorb external noise, etc. Connect them as close to the IC as possible. 3 is used for phase correction, but this also must be connected as close to the IC as possible. 1998-05-15 16/17TOSHIBA TD62650,651,652F OUTLINE DRAWING ‘SS0P30-P-375-1.00 Unit > mm 30 16 ARORA ARARARAAG a 5 als g - aTanqoaaned 5 1 | 15 well L} eee ssa02 rs 8 uUNUNNNNNO | Sg Weight : 0.639 (Typ.) 1998-05-15 17/17