CBCS SGHEME

18MAT31
N

Dec.2019/Jan.2020
Third Semester B.E. Degree Examination,
Numerical
Transform Calculus, Fourier Series and
Techniques
Max. Marks: 100
ime: 3 hrs.
each module.
Note: Answer any FIVE full questions, choosing ONE full question from
Module-1
a. Find the Laplace transform of:

sin 2t (ii) tcos at . (10 Marks)

0st<a
Show that
b. The square wavc function f(t) with period 2a defined by f(t) ={
-1 ast<2a
(05 Marks)

transform to solve
ydy =0 y(0)=y,(0) =3. (05 Marks)
C. Employ Laplace dt2 dt

OR

2 a. ind() L i) cot (i)

s+2)(s+3))
(10 Marks)

convolution theorem. (05 Marks)

b. Find the inverse Laplace transform of, s(s* +1) using

if 0<t<l1
C. Express f(t) = { i f < t < i n terms of unit step function and hence find its Laplace

COst t>

(05 Marks)
transformation.
Module-2
<0
(08 Marks)
d . Obtain the Fourier series of
x)=0<x <2 in the interval 0sx S1 (06 Marks)
b. Find thehalf range cosine series of, f(x) =(x +1)
series of period 27 in the interval 0 < x <27. (06 Marks)
c. Express f(x) =X as a Fourier

I of 3
 18MAT31
OR
4 a. Compute the first two harmonics of the Fourier Series of f(x) given the following table
600 120° 180° 240° 300
7.9 7.2 3.60.5 0.9 6.8
b.
(08 Marks)
Find the half range size series of e in the interval 03xs1. (06 Marks)
T X
Obtain the Fourier series of f(x)
=-12 valid in the interval-T t) (06 Marks)

Module-3
5 a. Find the Infinite Fourier transform
b.
of e. (07 Marks)
Find the Fourier cosine transform
of f(x) e2* +4e. =
(06 Marks)
C. Solve u12-3ul
+2u, =3". given u =u, =0. (07 Marks)
OR
a.a. IfIf f(x)=for|xlsa
f(x)=o for la
T find the infinite
transform of fx) and hence evaluate dx.
0
b. Obtain the
Z-transform of cosh n6 and sinh ne (07 Marks
(06 Marks)
C.
Find the
inverse Z-transform of 4z22z
z52 +8z- (07 Marks)

7 a. Solve dy
Module-4
dx =e-y, y(O) =2 using Taylor's Series method upto
the value of 4 degree terms and
y(1.1).
b. Use (07 Marks
Runge-Kutta method of fourth order to solve
(Take h = 0.1)1 +y#2x at x =
1.1given y()=3
c.
Apply Milne s (06Marks)
predictor-corrector formulae to compute y(0.4) given
dx
=
2e*y, with
x 0.1 0.2 0 0.3 (07 Marks)
y2.4 2.473 3.129 4.059
OR
8
aGiven dy
dx =x+ sin y y(0)= 1.
method.
Compute y(0.4) with h =
0.2 using Euler's modified
b.
Apply Runge-Kutta fourth
order method, to find y(0.1) with h (07 Marks
y0)= 1. =0.1 given dy +y+Xy 0
c. dx
Using
Adams-Bashforth method, find y(4.4) given 5x (06 Marks)
4.1
4.2 dx +y =2 with

.00491.0097 4.3
1.0143
(07 MarkS
2 of 3
 18MAT31

Module5
9.
. Solve by Runge Kutta method for x0.2 correct 4 decimal places,
dx dx
using initial conditions y(0)= 1, y'(0) = 0,h=0,2 (07 Marks)
b. Derive Euler's equation inthe standard form, or d or1-0.
0. (06 Marks)
Oy dx Oy'

c. Find the extramal ofthe functional. y ( +2ye'dx (07 Marks)

OR
dy =1+and the following table
10 a. Apply Milne's predictor corrcctor method to compute dx

of initial values:
0 0.1 0.2 0.3
1.2427 1.3990
| 1.1103
I1.2103 1.4427 1.6990 (07 Marks)

=0; y=1
functional, -y'"-2ysin xix: y(0)
6. Find the extramal for the
(06 Marks)
(07 Marks)
surface are straight lines.
C. Prove that geodesics of a plane

6107 0
 GBGS SGHEME
N
18EC32

Third Semester B.E. Degree Examination, Dec.2019/Jan.2020

Network Theoryy
me: 3 hrs. Max. Marks: 100
Note: Answer any FIVE full questions, choosing ONEfull question from each module.

Module-1
a. Using source transformation technique find the current through 50 resistor for the cireuit
shown in Fig.Q.1(a) (06 Marks)
5

Fig.Q.1(a)
20
3

shown in
b. Use Mesh Analysis to determine the Mesh currentsi1, iz and is for the network
(06 Marks)
Fig.Q.1(b) - - M M l n

- M.

Fig.Q.1(6)
2
shown in
C. Find the power delivered by 1A current source using nodal analysis for the circuit
(08 Marks)
Fig.Q.1(c). LA

2
M-

Fig.Q.1() 12
3J

OR
are connected in delta, obtain the star equivalent of the network.
2 a. Three Impedances (06 Marks)
in the
delivered by the dependent voltage
source
b. Use Mesh Analysis to find the power
(06 Marks)
circuit shown in Fig.Q.2(b). 5
ww
+
66oV 15 25-

Fig.Q.2(b)
a 50

the circuit shown in Fig.Q.2(c) using nodal analysis.

C. Determine all the node voltages for (08 Marks)

w .

K * A

MM

Fig.Q.2(c)
ww- 20 A

I of4
 18
Module-2
theorem (06 M
3a. State and explain superposition
b. Use Millman's Theorem to find the
current flowing through (2+ J3)S2 impedance
circuit shown in Fig.Q.3(b). (08 M
2

2 uN J3

Fig.Q.3(b)
C. State and prove Norton's theorem. (06 Mat
OR
4 a. Find the Thevenin's equivalent for the circuit shown in Fig.Q.4(a) with respe
terminals X-Y. (081Ma
6
J
6
20v
&
b.
Fig.Q.4(a)
Find the condition for maximum power transfer in the AC circuit, where both R; and Xu-
varying. (06 Mai
C. Determine the' current through the load resistance using Norton's Theorem for the cinoE
shown in Fig.Q4(c).
(06 Marks

Fig.Q.4(c)
5 a.
Explain the behavior of R, L,
Module-3
C elements at the time of switching at t =0, at t =0
and1
(071Marks
b. In the network shown in Fig.Q.5(b). Find i,
is initially uncharged.
and at t =
0". Assume that the
capat"
(07 Marks

loF

Fig.Q.5(b)
C.
In the network shown in Fig.Q.5(¢)
find, i, and
t 0 with zero current dt att
dt2 0*. =
The swich k is clos
in the inductor.
(06
Mars
lo

loov

Fig.Q.5(e)
2 of 4
 OR 0,
is changed from position a to b at t =

shown in Fig.Q.6(a). The switch k

a. In the network 2
Assume that the
is reached at position a. Find i, and at t = 0*.
the steady state
dt
(10 Marks)
capacitor is initially uncharged.
1,000

Fig.Q.6(a)
steady státe with switch k is closed.
b. For the network shown in Fig.Q.6(b). The network is in
opened. Determine the voltage across the switch Ve andVat
Att 0. the switch is
(10 Marks)
0.
V 4

2v
HH

Fig.Q.6(b)
Module-4
a. Obtain Laplace transform of
i) Step function
ii) Ramp function
(09 Marks)
ii) Impulse function.
shown in Fig.Q.7(6). (11 Marks)
b. Find the Laplace transform of the periodic signal x(t) as

Fig.Q.7(b)

OR
8 a. In the series RL circuit shown in Fig.Q.8(a), the 'source voltage is v(t) = 50 sin 250tV. Using

is closed at t 0. (10 Marks)

when switch K
=

the current
Laplace transform determine,
2.5

ooo5 H

Fig.Q.8(a)
Find the Laplace transform of the non-sinuso idal periodic waveform shown in Fig.Q.8(b)

Fig.Q.8(b) (10 Marks)

3 of 4
 18EC
9 a. Define Z parametlers. Determine Z
Modulc-5
parameters interms of Y parameters. (06 Mar
b. Determine h parameters of the circuit shown in Fig.Q.96) (07 Mark

Fig.Q.9(b)
C. For the network shown in
Fig.Q.9(c). Find the transmission parameters. (07 Marks
www- MM

V2

Fig.Q.9()
OR
10 Define
a.
Q-factor, selcctivity and
Band width
b. A series RLC circuit has a (03 Marks
resistance of 102, an inductance of 0.3H
100uF. The applied voltage is 230V. Find: i) The resonant and a capacitance
o
cut off
frequencies i ) current at resonance frequency ii) lower and uppeë
the inductance at resonance. iv) currents at fi and f2
v) Voltage across
Voltage acrosSS
c. Derive the (07 Marks
expression for the resonant
frequency of the circuit shown in
show that the circuit will resonate Fig.Q.10(c). Also
at all frequency if R, Re
= =

(10 Marks
RL
R
MM-

Fig.Q.10(c)

L07-7T ***
 CBCS SCHEME
USN 18EC33

Third Semester B.E. Degree Examination, Dec.2019/Jan.2020

Electronic Devices
Time: 3 hrs. Max. Marks: 100
Note: Answer FIVE full questions, choosing ONE full question from each module.

a.
Module-1
What are the types of Bonding forceses in solids? Explain. (06 Marks)
b. Explain the classification of material based on conductivity and energy band diagram.
(08 Marks)
C.
Find the con tivity of the intrinsic germanium at 300 K. Ifa donar type impurity is added
to the extent of I atom/10 germanium atom assume H, =3800, Hp =1800, n, =2.5x10°.
Q= 1.602x10-19. (06 Marks)

OR
2 a. What are Direct and Indirect band gap semiconductor? Explain with examples. (08 Marks)
semiconductor with energy band
b. Explain the concentration of electron-hole pair in Intrinsic
(06 Marks)
diagram. 300 K.
room temperature T
=

C. Calculate the Intrinsic carrier concentration in Silicon at

and EG as the bandgap energy
where B is the material dependent parameter 5.4x10
(06 Marks)
1.12 eV, where K is the Boltzman constant 8.62x10eV/K.
=

Module-2
and at
the doping level in extrinsic semiconductor at 0 K
3 a. With energy band diagram, explain
(09 Marks)
50K.
What is the magnitude of HALL voltage in a N-Type germanium bar having an majority
b.
0.2 Wb/ms, d 2 mm, E 10 V/cm.
=
=

Np 10" cm. Assume B

=

carrier concentration
=

(05 Marks)
(06 Marks)
effect of temperature on semiconductor.
C. Explain the
OR
flow at P-N junction under equilibrium and
of current
4 a. Explain the qualitative description (08 Marks)
biased condition. biased P-N junction.
breakdown under reverse
breakdown and avalanche (06 Marks)
b. Explain zener
under ideal condition.
Discuss the piece-wise
linear approximations of junction diode (06 Marks)
c.

Module-3 (08 Marks)

carrier in a P-N junction.
Explain the optical generation of
(06 Marks)
(06 Marks)
a. the planar junction.
cell in enlarged view of
b. Discuss the configuration of a solar (06 Marks)

injection-electroluminiscence
and what are its applications?
C. What is

I of2
 OR
a.
Explain 1-V characterist ics of n-p function of emitter current.
b. junction as a
Discuss switching
operationin common-emitter transistor.
i g u r e Q6 (c)
shows the common emitter amplifier circuit. Calculate ls and
Tp=10 us, t, =
0.1 AS

500
P
B
VBE P
5V

Fig. Q6 (c)
7 a. Draw and
explain the 1-V Module-4
voltages. characteristics of n-channel PNJFET
b. for differen
Draw and
explain the small signal
C.
Explain the MOS structure with theequivalent
aid of
circuit of n-channel
PNJFET.
parallel-plate capacitor.

8 OR
a.
Explain the effect of
frequency on gate voltage of a MOS
b.
Explain P-channel enhancement and capacitor with a P-type
depletion type MOSFET with the ir
circuit sym

9 a. With schematic Module-5

diagram, explain 1ON-implantation
b.
Explain low pressure chemical system.
c. Discuss photolithography. vapour deposition reactor.

10 a. What OR
are the different
b. types of integrated circuits and its
Explain the process of
Integration. advantages?
*** **

2 of 2
 CBIGS SChEME
8EC34
SN

Third Semester B.E. Degree Examination, Dec.2019/.Jan.2020

Digital System Design

Max. Marks: 100
ime: 3 hrs.
module.
Note: Answer any FIVE full questions, choosing ONE full question from euch
Module-1 number.
a. Design a combinational circuit to output the 2's complement of a 4-bit binary
(07 Marks)
of following function using
b. ldentify all prime implicants and essential prime implicants
K-map: Draw the diagram using NAND
f(a, b, c, d)
=
Zm + (6, 7, 9, 10, 13) + dc(1, 4, 5, 11, 15).
(07 Mark»)
gates. in decimal form:
C. Expand the following in to canonical form and represent
i) fa+bc + ac'd in to min-terms (06 Marks)
ii) f2 a(b +c) (a + c + d) into max terms.
OR method:
using Boolean function Quinc-McClusky
2a. Find the minimalof the following sum
(07 Mark)
+ dc (4, 11).
fa, b, c, d) =2m (7, 9, 12, 13, 14, 15) of sum expressions an implement
the simplificd
b. Using K-map determine minimal product
equation using only NOR gates: (07 Marks)
f(w, x, y, z) T(1,2, 3, 4, 9,
=
10) +d(0, 14, 15). and
Incompletely specified functions, essential prime implicants
C.Explain briefly K-map, (06 Marks)
Gray code.
Module-2 IIIGH
active low enable and active
the following using 3 to 8 decoder with
a. Implement
outputs:
fia, b, c, d)
=
2m (0, 1, 5, 6, 7, 9, 10, 15) (06 Marks)
i)
ii) fa(a, b, c)
=
t(1, 3, 6, 7) relevant expressions.
look-ahead adder with necessary
diagram and (08 Marks)
Explain 4-bit carry
b. ILSB least
encoder which gives MSB the highest priority and
C. Design 4 line to 2 line priority (06 Marks)

priority.
OR
a. Implement f{a, b, c, d)
=
2(0, 4, 8, 10, 14, 15) using
lines
with a, b, c as select (06 Marks)
i) 8:1 MUX
with a, b as select lines. (08 Marks)
ii) 4:1 MUX comparator and
draw the neat diagram. (06 Marks)
b. Design a two bit magnitude with an example.
programmable logic arrays (PLA)
C. Explain the structure of
Module-3 truth table and
waveform.
NAND gates with necessary (06 Marks)
Explain clocked SR flip flop using
to store binary
a.
4-bit SIPO shift register
truth table, a (07 Marks)
Explain with a neat diagram and
b with a diagram, function
number 1011. master slave flip flop
around condition? Explain JK (07 Marks)
C. What is race

table and timing diagram. I of2

 OR
6 a. Explain with an excitation table, the conversion of SR flip flop in to JK and D flip flop
(06 M,
b. Explain the working of 4-bit Twisted Ring counter using necessary diagram and wave
(07 M
C. Explain the working of 3-bit Asynchronous up-down counter with necessary wavefom
truth table. (07 Ma
Module-4
7 a. Design a self correcting synchronous counter using positive edge triggered JK flip fon
count 0, 1, 2, 4, 5, 6, 0, 1,2... Use the state table and state diagram. (10 Man
b. Design a clocked sequential circuit which operates according to the state diagram show
Fig.Q.7(6). Implement the circuit using negative edge triggered JK flip-flop. (10 Ma

ot
b

Fig.Q.7(b)
OR
8 a. Construct the excitation table, transition table, state table and state diagram for th
sequential circuit shown in Fig.Q.8(a). (10 Marks3

Fig.Q.8(a)
b. Realize synchronous decade counter using T-flip-flop and draw the neat diagram. (10 Mark<

Module-5
9 a. Design a Melay type sequence detector to detect the sequence of 101 in the given sequenc
of 001101100101011. (10Marks
b. With necessary diagram, explain the concept of serial adder with accumulators. (10 Marks

OR
10 a. Design a sequential circuit to convert BCD to Excess-3 code with state table, state graphan
transition table. (10 Marks
b. Explain the design of sequential circuit using CPLDs and give CPLD implementation of
shift register and parallel adder with accumulator. (10 Marks
*** **

2 of 2
 CBCS SCHEME
USN 18EC35
Third Semester B.E. Degree Examination, Dec.2019/Jan.2020
Computer Organization and Architecture
Time: 3 hrs.
Max. Marks: 100
Note: Answer any FIVE full questions, choosing ONE full question from each module.

Module-1
1 a. With a neat diagram, explain basic operational concept of computer.
(10 Marks)
b. Explain in brief different types of key parameters that affect the processor performance.
S) (05 Marks)
c. Explain the Bus Structures. (05 Marks)

OR
2 a. Ilustrate Instruction and Instruction sequencing with an example. (10 Marks)
b. Define Byte Addressability, Big-endian and Little-endian assignment. (06 Marks)
C. Represent 85.125 in IEEE floating point using single precision. (04 Marks)

Module-2
3 a. What is an addressing mode? Explain any five types of addressing modes with example.
(10 Marks)
b. Write a program to add 'n' number using indirect addressing mode. (06 Marks)
C. Explain various assembler directives used in assembly language program. (04 Marks)
the:
ks) OR
4 a. Explain stack operation with an example (10 Marks)
b. Explain subroutine linkage with an example using linkage register. (06 Marks)
c. Explain the shift and rotate operations with example. (04 Marks)

Module-3
in I/0 interface, explain program controlled
5 a. Showing the possible register configuration (10 Marks)
input/output. illustrate the concept of interrupt. (10 Marks)
b. What is an interrupt? With an example

ks) OR
of initiat ing interrupts
situations where a number of devices capable
6 a. Explain in detail, the (10 Marks)
How to resolve the problems?
are connected to processor.
illustrate DMA. (06 Marks)
ce involved in a DMA interface, to
b. Explain the registers (04 Marks)
Vectored Interrupt.
ks) C. Explain the concept of
ks) Module-4
chip. (10 Marks)
With figure, explain Internal Organization of 2Mx8 dynamic memory
7 a. (10 Marks)
memories.
nd b. Ilustrate Internal structure of static
ks)
OR
fa (10 Marks)
organization.
ks) 8 a. With diagram, explain virtual memory
a neat (05 Marks)
four non-volatile memory concepts.
b. Briefly explain any devices.
(05 Marks)

C. Briefly explain secondary storage

1of 2
9 Module-5
a.
Explain the three-bus organization of the processor and its
b. Discuss the advantages.
organization of hardwired control unit.
C. Discuss the control sequence for execution of
instruction ADD(R3), R
10 OR
a. With a block diagram, describe the
organization ofa micro programmed control un
b. Describe the sequence of control
memory in a single bus
signals to be generated to fetch
organization. an instruct
**** *
 CBCS SCHEME M 18EC36
USN

Third Semester B.E. Degree Examination, Dec.2019/Jan.2020

Power Electronics and Instrumentation
Max. Marks: 100
Time: 3 hrs.
each module.
Note: Answer any FIVE full questions, choosing ONE full question from
Module-1
and maximum Ratings.
their circuit symbols
a. Name the power semiconductor devices along (04 Marks)
transistor model and derive anode current and
b. Explain the operation of SCR, interms of two device into condition.
how a small gate current can trigger the
gate currents relation. Discuss (08 Marks)
60m Amp. The duration of the firing pulse is
C. The latching current of a thyristor circuit is
connected in series.
are
Given V, 100V, R 202 and L =0.5H
=
=

50usec.
i) Derive the expression for circuit i(t)
current
to time
ii) Draw variation of current i(t) with reference (08 Marks)
iii) Will the thyristor device gets turned ON?
OR
(04 Marks)
of power electronics.
2 a. Enumerate the applications with relevant circuit
b. Explain the operation of self
commutation by resonating load [class A] (08 Marks)
and waveforms.
and forms, now
schemes? Explain with circuit diagram
wave

C. What are the gate triggering (08 Marks)

RC circuit turns ON (triggers) SCRs
triggering
Module-2
(06 Marks)
strategies used to operate choppers.
3 a. Explain the control the operation of a single phase
neat circuit diagram and waveforms,
b. Explain with the help of load. Derive an expression for the
controlled rectifiers with resistive
half wave load voltage.
(08 Marks)
i) Average load voltage i) RMS conditions are given: V 220V,
A [step down] chopper circuit, following
c. Forthe ideal type
f= 500Hz, R
frequency 12, L =3mH and Eb= 23 volts.
=

Duty cycle
=
Chopping
0.3,
Determine the following
value of output current (load)
i) Minimum current (load)
ii) Maximum value of output
curent.
(06 Marks)
ii) Average output (load)
OR
(04 Marks)
diode used in controlled rectifiers.
free wheeling
4 a. Explain the effect of circuit waveforms, explain
the principle of operation of step-up
5 b. With the circuit diagram
and (08 Marks)

chopper. rectifier is feeding to a

RL load, to obtain a regulated
A single phase fully controlled bridge at 50Hz and the firing angle
C.
RMS value of the AC voltage is 230V,
DC output voltage. The
maintained at t/3, so that
the load current is 4Amp.
is
Calculate the DC average output
voltage
i) input voltage. IT
i) Active power and reactive power determine DC average output
resistance remains the same, (08 Marks)
Assuming the load conditions remains
same.
1in) with all the
a freewheeling
diode is used at output
I of 2
 18EC3
US
Module-33 Relative crrors?
Absolute error iv)
5a. Detine the : i) instrument ii) Accuracy iii)
terms (04 Mark
b. Explain the operation of single phase half bridge inverter connected to RL load,(08with
Mark

waveforms.
help of circuit and of 2mAmp and having an intern
a null scale deflection
C. A basic D' arsonval movement with 0-1000V, 0-100V an
resistance of 502 is available. It is to be
converted into a 0--10V,
to extend? (08 Marky
-250V multi range voltmeter. Determine
the value of resistance

OR
What are inverters? Classify the inverters accordingto commutation and connections?
(04 Mark
6 a.
(08 Marks
b. What are the static errors?Explain them in detail with examples.
of R 32 and DC input votag
bridge inverter, has resistive load
=

C. A single phase half

Vic 50 volts. Calculate
i) RMS output voltage at fundamental frequency
ii) The output power (Po)
iii) The average and peak current of each thyristor
The peak reverse blocking voltage of each thyristor.
(08Marks
iv) -

Module-4
7 a. Explain how a simple AC bridge circuit operates and derive an expression for the unknow

parameters. (04Mark
With the aid of diagram, explain the working of unbalanced wheat stöne bridge and derivg
b.
for a galvanometer current expression. (08 Marks
C.
Explain the principle of operation of digital time measurement with basic block diagram.
(08 Marks E

OR
8 a. What are the advantages of digital instruments over analog instruments? (04Marke
b. Determine the equivalent parallel resistance and capacitance that causes a Wein's bridge
null condition with the following values : Ri =3.1KQ, C =5.2uF, R= 55KO, R =100K
ff
With2.5KHz. Derive
neat block the balanced
diagram, explain expressions.
the operating principle of a Ramp type DVM. (08Marks
Mar
C.

Module-5
9 a.Define transducers. What are advantages of electrical transducers? (04 Marks
b. Explain instrumentation Amplifier using transducer bridge with the help of circuit diagra
(08MarksS

Explain with neat diagram the PLC structure.

( 0 8M a r k E

OR
10 a. What are features of instrumentation Amplifiers? How it differs from the ordinary Ops
Amy
( 0 4M a r k s 2 ?

b. Describe the operation of resistive position transducer with constructional diagra am

typical circuit used. (08Marks

Er. MentioS
C. With the aid of Bridge circuit, explain the working of resistance thermometer. V
limitations of it. ( 0 8M a r k s
 GBGS SCHEME
USN 18EE32
Third Semester B.E.
Degree Examination, Dec.2019/Jan.2020
Electric Circuit Analysis
Time: 3 hrs.
Max. Marks: 100
Note: Answer any
FIVEfull questions, choosing ONE full question from each module.
Module-1
a. Setup nodal equations for the circuit of
source. Fig.Q1(a) and then find the power supplied by 5 -

M 2 r

b. Fig.Q1(a) (08 Marks)

Making use of source shifting procedure, simplify the circuit of Fig.Q1(6) in such
the voltage Vx is determined. a way that

2 5

C. Use mesh
Fig.Q1(b) (06 Marks)
analysis to determine the branch currents in the network indicated in Fig.Ql(c).
JOT2 SN Ta
Dm

Fig.Q1(c) (06 Marks)

2 a.
OR
Find 'Req' for the network shown in Fig.Q2(a) across A and B.

each
Fig.Q2(a) {( K M (06 Marks)
b. Draw the exact dual of the network shown in Fig.Q2(6) by writing Kirchhoffs law
equations.

lo2
Fig.Q2(b) VSosbm (08 Marks
c. Reduce the network of Fig.Q2(¢) to a fornm with only one current source across terminals
using source transformation (terminals A and B).

3.2 6V
M-
2/2
Fig.Q2() 4V
(06 Marks)
1 of 4
 Module-2
3 a. ind the Thevenin's equivalent cireuit at the terminals A and B of the circuit in

200

Fig.Q3(a)
b. Find the value of R, in the network shown in
and specify the value of that Fig.Q3(b) that will absorb a maxim
pOwer.
M
202

c. In the
Fig.Q3(b)
network shown in
resistor. Find T'. Verify theFig.Q3(c)
the voltage source of 5V causes a current
reciprocity theorem.

5v 2N
Fig.Q3(c)

4 a. In the network shown in OR

theoremn Fig.Q4(a) determine the nodal
voltage V2 using sup-
.5102-

io'
b. Use Fig.Q4(a)
Thevenin's theorem to find current in Ri= 62 in
Fig.Q4(b).
4 0 6a0
6ov A
360 sh0
C. State and prove Fig.4(b)
Millman's theoremn.

2 of 4
 18EE32

a, Derive an Module-3
expression for resonant
show in Fig.Q5(a). frequency "fo for the general parallel resonant cireuit

b.
Fig.Q5a)
Fig.Q5(6) shows a network with zero
switch 'K" is capacitor voltage and zero inductor current (08
open. Att= 0 the switch 'K'
Marks)
when the
i) V and V2 at t
is closed. Solve for
0
=

and2
dt
and 0
iii) Vi and V2 at t=

Fig. Q5(b)
(12 Marks))

6
OR
2.
Fig.Q6(a) shows a RCIL paralle! circuit excited by a DC current source. At t
K is opened. Find v(t).
=
0, the switch

7-7
Fig.06(a)
(08 Marks)
b. A 400V, 200Hz AC source is connected in series with a capactor and a coil whose
resistance and inductançe are 20ms2 and 6mH respectively. If the circuit is in resonance at
200Hz,find:
i) Value of capacitor
ii) V A/C the capacitor
ii) Maximurn energy stored (instantaneous) in the coil
Civ) The half-powerfrequencies. (08 Marks)
What are initial conditions in network? Write the equivalent form of the network elements
interms of the initial conditions. (04 Marks)
3 of 4
 181
Module-4

wave shown in Fig.Q7(a).

transform of the square
7 a. Find the Lapalce USN

Fig.Q7(a) =
12 sin 5t. The Time
a voltage v(t)
R-L-C circuit excited by
b. Fig.Q7(6) shows a series a/c capacitor is one volt with
current in the circuit is
5A and the initial voltage
transformat ion method.
shown. Find i(t) using Lapalce
6 L+
MO0-

Eio04F
(08 Me
Fig.Q7(6) transformation. (04 M
in the context of Lapalce
the initial-value theorem
C. State and prove

OR
unit height and duration
T' is applied to a series
8 A rectangular voltage pulse of
a.
the voltage across the capacitance "C as a function oft
combinatión at t 0. Determine
=

(10 Mar 5
Use Laplace transformation method. 2
below and sketch
two different functions given
b. Find the Laplace transforms of the (10 Mar
waveforms. i) sin (wt) u(t to) ii)sin w(t -to) u(t-to)

Module-5
9a. A symmetrical 3 ¢, 100V, 3-wire supply feeds an unbalanced star-connected load

Find tei
impedances of the load as ZR 5a, zY-290n and ZB= 4E90Q.
=

currents, voltage across the impedances and the displacement natural voltage. Also caku
sequence RYB. Take
VR!,.
the power consumed by the load. Draw the phasor diagram
ref.
(10Man
b. For the circuit of Fig.9(6) find Z-parameters. Hence calculate transmission (AB
parametérs, Find whether the network is symmetrical? Reciprocal?

Fig.Q9(b) (10Man

OR
10 a. A 3-0 delta connected load has ZRY = (100 + j50)2, ZyB = (20 j75)

ZBR = (70.7 +j70.7).2 and it is connected to balanced 3 - o, 400V supply. Determine

currents, power consumed by the load. Sketch the phasor diagram. Assume RY ( 1 0Man
sequence and take VYB as the reference phasor.
b. For the circuit shown in Fig.Q10(b) find Y-parameters. Is the network symme
er

Reciprocal?

Ys
ys) 2V,6Y
( 1 0M a r

Fig.10(b) -
*** 4 of 4 * * *
 USN
CBC SCHEME
18EE35
Third Semester B.F.
Degree Examination,
Digital System DesignDec.2019/Jan.2020
Time: 3 hrs.

Max. Marks: 100

Note: Answer
any FIVE full questions, choosing
ONE Jull question from each module.
I. Write the truth table Module-1
of the logic circuit having and
yaabe + abe + abe. Also inputs a, b and c and an output
using NAND gates only. simplily the Boolean
expression and implement the logic circuit
b.
Minimize the following
i)fita. b, e, d) =
multiple output functions using K-map (06 Marks)
Xm(l.,5,7,8,9, 10, 11, 13, 15)
ii) a, b, e, d) Xin(1,2,
6,7 8,
C.
Define Canonical Minterm form 13, 14, 15) + Xd(3, 5, 12). (10 Marks)
and canonical Maxterm form.
(04 Marks)

2 OR
a. Convert the following Boolean funetion into their
notation. proper canonical form in decimal
i) f= ab + be ii)f =(x + y)My + 7).
b. Simplify using Quine-Mecluskey minimization technique for the (08 Marks)
(w, N. y, z) =X(0, 1, 4, 5, 9, 11, 13, 15). following function.
(12 Marks)

3 Module-2
a. Design a combinational circuit that ill multiply two 2-bit numbers.
b. (12 Marks)
Implement full subtractor using 3 8 line decoder with active high outputs and active low
enable input.
(08 Marks)

OR
4. Implement the following using 8 to I MUX with a, b, c as select lines
(a, b, c, d)=2(0, 1, 5, 6, 7,9, 10, 15)
b.
(08 Marks)
Implement a 1-bit comparator using 2:4 decoder 74139 (04 Marks)
c. Design a priority encoder for a system with three inputs, with the middle bit with highest
priority encoding to I10, the MSB with the next priority encoding to 11, while the LSB with
the least priority encoding to 01. (08 Marks)

Module-3
5a. With a neat diagram, explain the working of master-slave JK flip-flop along with
waveforms. (10 Marks)
b. Explain switch debouncer using SR latch with waveforms. (10 Marks)

OR
6 a. Write the characteristic equation of SR, JK, D and T flip-flops. (08 Marks)
b. Differentiate sequential logic circuit and combinational logic circuit. (04 Marks)
C. Explain the operation of SR latch with an example. (08 Marks)
Iof2
 18
Module-4
Denign a 4-bit register using positive edge triggered D-flip-flop to operate as indican.
tae ekow indicate
Mode select
Data line selected Register operation
Hold
Shift right
d Shift left
da Parallel load
bDesign a 4-bit md-% ohnson counter and also write the count sequence table. (12
(08

OR
Design a 4-bit binary
ripple up counter using positive edge triggered t-flip-flop witha
eable line. Write the
counting sequence and relevant timing diagram.
e i g n a synchronous counter to count the sequence 0. 1, 4, 6, 7, 5 and (08
dye triggered IK flip-fops. repeat using p
(12

9 Module-5
a
Enplain Meay and Moore model in a sequential circuit
Desin a sequertial circuit using D-flip-flop for stateanalys
is. (08
the diagram. Show below in Fig
(12

olo
Fig.Q9(b)
1 Coastrua the excitation table, transitionOR
wgertial círcut shown in table, state table and state
Fig.Q10(a). diagram for the-
(12

Wrte shot noes on Fig.Q10(a)

iy ROM i) RAM
ii) EPROVM iv) Flash Memory.
k** *

2 of 2
 CBGS SCHEME
18EE36
USN

Third Semester B.E. Degree Examination, Dec.2019/Jan.2020

Electrical and Electronic Measurements

Time: 3 hrs. Max. Marks: 100

Note: Answer any FIVE full questions, choosing ONE full question from each module.

1a
Module-1
Define "Votage Sensitivity of a Galvanometer. Obtain an expression for bridge senstivity
be
Sin terms of and bridge parameters. When will the bridge sensitivity
votage sensitivity
(07 Marks)
maximum?
fall of
the necessity of Earthing. Explain measurement of Earth Resistance by
b. Explain (06 Marks)
potential method.
balance equation. (07 Marks)
Explain Maxwell Inductance capacitance bridge and derive its
OR
resistance' measurement. With a neat circuit diagram.
2 a. Explain significance
the of low
(08 Marks)
explain Kelvin Double Bridge and derive its balance cquation.
values of Z, 400|50
= ohm.
b. The four arms of an ac bridge have impedance
ohm. Find whether the bridge is
Z, 800-50 ohm and Z, 400|20
=

= 200 40 ohm. =

(04 Marks)
ba lanced under this working condit ion. of
Hith a neat circuit diagtam, explain
modified De-Sauty bridge for measurement

and derive its balance equation. (08 Marks)

capacitance ofan imperfect capacitor

Module-2
Wattmeter. (07 Marks)
3 a. Derive the torque equation of a single phase Dynamometer type
required in Energy meter for the accurate reading.
b. Explain the various adjustments (06 Marks)

neat sketch. explain the construction and working of a single phase Dynamometer
With a
(07 Marks)
type Power Factor meter.

OR

4a Explain: i) Phase sequence Indicators ) Determination of power factor of a balanced three

Wi and W2 obtained from two Wattmeter method of
phase load. using Wattmeter readings (08 Marks)
power measurement.
and adjustments in Dynamometer type
Wattmeter. (06 Marks)
b. Explain the various errors
meter.
sketch. explain the construction
and working of Weston frequency
C.With a neat (06 Marks)

Module-3
to find the required values of shunts
What shunts and multipliers? Derive expressions
5 a. are
(06 Marks)
and multipliers. and Power
Differentiate between Current Transformers
b. What are Instrument Transformers? (06 Marks)
Transformers. and phasor
transformer with the help of an equivalent
circuit diagram a

Explain the current

(08 Marks)
for ratio error and "phase angle
error' ofa CT.
diagram. write expressions
I of 2
 G3GS SGHEME 18CPC39

Question Paper Version: D

USN
Third Semester B.E. Degree Examination, Dec.2019/Jan.2020
Constitution of India and Professional Ethics and Cyber
Law
(COMMON TO ALL BRANCHES)
Time: 2 hrs.] [Max. Marks: 100

INSTRUCTIONS TO THE CANDIDATES

1. Answer all the Hundred questions, each question carries ONE mark.
2. Use only Black ball point pen for writing/ darkening the circles.
3. For each question, after selecting your answer, darken the appropriate circle

corresponding to the same question number on the OMR sheet.

4. Darkening twó circles for the same question makes the answer invalid.
5. Damaging/overwriting, using whiteners on the OMR sheets are strictly
prohibited.

1. Which is the landmark Judgment passed by the Supreme Court in respect to Preamble of
Constitution
a) Beur beri b) Keshavananda Bharathi
c) Menaka Gandhi d) Sonia Gandhi

2. Who is the neutral person in the affairs of party politics

a) C.M b) Home Minister c) Finance Minister d) Speaker
SC & ST in
3. Indian Constitution guarantees reservation of seatsb)toLok Sabha only
a) Lok Sabha and Assembly
c) Lok Sabha and Rajya Sabha d) Rajya Sabha

Who will preside over the joint session of both the houses of the Parliament
b) Prime Minister c) Speaker d) Law Minister
a) President
5. What is the minimum age for becoming M.P in Rajya Sabha and Lok Sabha
a) 18 and 25 b) 25 and 18 c) 25 and 30 d) 30 and 25

6. India is referred to as under the Indian Constitution

b) Hindustan c)India d) Bharat
a) Country
The citizens can enforce their Fundamental Rights before SC under
b) Article 32 c) Article 33 d) Article 34
a) Article 31

Version D-1 of 8