DESIGN AND VERIFICATION OF DUAL PORT

ASYNCHRONOUS FIFO

Dr. Deepti S.Khurge

4/14/2023 1
 Multiple clock domain circuits
 No clk is accurately supplied
to all areas of the circuit at
almost precisely the same time.

 Reducing transistor sizing

 GALS

 Crossing the clock domain

1st ???? 2nd

clock Data clock
domain x’fer domain

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 Situations in data transfer
 Synchronous data transfer. (same clock domain: control & HS signals)
 Asynchronous data transfer. (clock domain crossing)

Various scenarios

Writing
writing speed reading speed
>>>>
reading
reading >> writing

Burst input
data has larger system
????
width than
output data Burst output
data is larger
width than
input data
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 Design of FIFO

Depends on the requirements for a allow the

specific application. resynchronization
of the data path
FIFO has got two interfaces, across different
1. Writing 2.Reading clock domains.

Two clocks,
one for writing other for reading

FIFO full ensures that pointers

FIFO empty signals are resynchronized as
single-bit transitions
only
The FIFO uses gray-encoded read and write
pointers..

Data should not be lost ,

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duplicated or missed. 4
 Design Features

 Synthesizable
 Dual-clock architecture
 Configurable data width
 Configurable fifo depth
 Gray-coded read/write pointers
 Full/Empty flags

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 Pin-out Description
Pin Name I/O Description Active
state
Data_in[7:0] In FIFO data input Data
Data_out[7:0] Out FIFO data output data
Read_en In Enable reading Posedge
Write_en In Enable writing posedge
reset In Global reset posedge
Wclk In Input Clk in write posedge
domain
Rclk In Input Clk in read posedge
domain
Fifo_empty Out Fifo empty flag in low
read domain
Fifo_full out Fifo full flag in low
write domain
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 Dual Port FIFO Architecture
8 Datain
8

Dataout
wr Binary
addr addr Binary
counter
counter rd
Wclk FIFO
Mem
rdclk
Dual port
Binary to gray Binary to gray
converter
RAM converter

full comparator comparator empty

wrptr

wrpointer

DFF DFF
rdclk

rdpointer rdptr

DFF DFF

wclk
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 Synchronizers
 Synchronization is achieved by a chain of flip-flops to
resolve metastability
 If 2 flip-flops are chained together, the synchronizer
will now have roughly 2 clock periods to resolve
possible metastable events
 Using binary to gray converters ensures the glitches
free signals
 binary to gray converters + 2 flip-flops are chained
together = Synchronization

 Metastability
 setup and hold time violation

8
 Binary to Gray to Write
Write
gray code binary code _ptr
_ptr
converter converter sync

Read
clk

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 Source File Description
Source file (verilog) Description

"fifo_write.v" Writes into fifo

"fifo_rd.v" Reads from fifo

"fifo_memory.v" Fifo memory to store the data.

"syncro.v" used to avoid, or reduce the probability of

metastability

"fifo_top.v" Top-level block

“tp.v” Top level Test bench

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 Synthesis
Device utilization summary:---------------------------

Spartan III
Selected Device : 3s200pq208-4

Number of Slices: 185 out of 1920 9%

Number of Slice Flip Flops: 228 out of 3840 5%
Number of 4 input LUTs: 179 out of 3840 4%
Number of bonded IOBs: 48 out of 141 34%
Number of BRAMs: 1 out of 6 16%
Number of GCLKs: 2 out of 8 25%

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 FIFO Depth Calculation For Burst Data Input
Writing speed faster than reading
Ex:
 Writing speed = 10ns
 Reading speed = 25 ns
 Burst data = 16
 For 16 data time taken to write = 16
x10 ns =160 ns
 For 16 data time taken to read = 16 x
25 ns = 400ns
 Hence depth = 400/160 = 3
Reading speed faster than writing
• Both pointers are going to cross
any how!!!
• So handshake signaling must be
used.
• Read will wait till valid writing of
data happens
• Write block sends signal that it is
busy writing.
• Read block sends
acknowledgement signal , it has
finished reading.

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 HANDSHAKE SIGNALING

wrclk rdclk
Confirmation to read
rst
rst
Write block read block
wr
rd
Acc to write

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 A big deal-----VERIFICATION
Verification is expensive……..

DESIGN, 30

VERIFICATION
, 70

• But poor verification is even more expensive!!!

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 VERIFICATION

 Process : :“ INTEND OF THE DESIGN

IS PRESERVED IN ITS
IMPLEMENTATION”

 From specification : EXTRACT THE FEATURES

TO BE VERIFIED

 Technique : i. DIRECTED TEST CASES

 ii. RANDOMIZATION

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 Verification Plan
Verifying the specification
Architectural specification : functional requirement
Design specification : implementation of architecture
down the block
Levels of verification
Unit level
Reusable component
System level
Board level
Prioritizing the features
Must have : for first time success
Should have : commercial success
Nice to have : optional
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 FIFO features verified in this project
1.Features
 data_out : data which written first should be read first.
 fifo_full :i. when memory is full the fifo_full flag is set
 ii. no writing should happen after fifo_full flag is set
 fifo_empty : i. when memory is empty fifo_empty is set or not
 ii. no reading should happen after fifo_empty flag is set

2. Additional features (RTL engg. Specification):

 wr_pointer: To check which memory address location is pointed
while performing write operation
 rd_pointer: To check which memory address location is pointed
while performing read operation

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 Verification model
Monitor Flags

Stimuli Driver
FIFO
Generator Data Checker
UUT

Write
Task
FIFO
Behavioral
Read
Task

testing
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 Stimuli generation
Clock sources to be generated for verification:

i. clkwr : a. clock for creating address for FIFO to write data

b. writing the data on same clock pulse into those addresses.
ii. clkrd : a. clock generated for creating address for FIFO to read data
b. reading the data on same clock pulse form those
addresses
iii. ref_clk: reference clock is used for generation of different stimuli
and for invoking the tasks.

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 Task

 Write task (write_task): this task is written to store the data

to respective address locations of FIFO memory using
write incrementor (wr)

 Read task : this task is written to read the data from

respective address locations of FIFO memory using read
incrementor (rd)

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 Test cases
Normal function tests:
Reset, Data read

Corner test cases:

Multiple reset ,power on reset , empty at 0th mem.
,full at 0th mem , empty at 7th mem, full at 7th mem. write after
full , read after empty Pointer test

Extreme test cases.

All these test cases are written for following of clock conditions:

 read clock (clkrd) = write clock ( clkwr)

 read clock (clkrd) > write clock ( clkwr)
 read clock (clkrd) < write clock ( clkwr)

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Progress of a directed test case approach

100 %

% of
completeness
of test cases

time

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 Applications
 Used for interfacing units with unrelated clocks in
high-speed applications.
 Architecture is well suited for all dual-clock
applications and achieves area utilization;
 This architecture can be utilized as a drop-in module
to many applications.
 Suited for communication between processors and
peripheral devices with different data widths.
 This is best suited for the communication between
communication protocols

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Future scope
 Memory is the largest block in the FIFO, investigations
into power and area reductions while maintaining
reliability could have substantial impact on the overall
module design

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 Conclusion
 When we started to design FIFO we felt its very easy
to design and verify , but when FIFO is required for
specific application then we realize that we need to
change the modules accordingly and also verify them.
 Hence every time new corner cases need to be taken
care.

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