Chapter 4

The Central Processing Unit

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 Contents
— Instruction sets: Characteristics and functions
— Instruction sets: Addressing modes and formats
— Processor structure and function

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 Machine Instruction Characteristics
— The operation of the processor is determined by the
instructions it executes, referred to as machine
instructions or computer instructions
— The collection of different instructions that the
processor can execute is referred to as the processor’s
instruction set
— Each instruction must contain the information required
by the processor for execution
— Instruction’s semantic is works which are performed
by hardware.

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 Elements of a Machine Instruction
Operation code Source operand
(opcode) reference
Specifies the operation • The operation may
to be performed. The involve one or more
operation is specified by source operands, that is,
a binary code, known as operands that are inputs
the operation code, or for the operation
opcode

Result operand Next instruction

reference reference
• The operation may • This tells the processor
produce a result where to fetch the
next instruction after
the execution of this
instruction is complete
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 Source and result operands
1) Main or virtual memory
— As with next instruction references,
the main or virtual memory address
must be supplied
2) I/O device
— The instruction must specify the
I/O module and device for the
operation. If memory-mapped
I/O is used, this is just another
main or virtual memory address
5 instruction being executed
3) Processor register
— A processor contains one or
more registers that may be
referenced by machine
instructions.
— If more than one register
exists each register is assigned
a unique name or number and
the instruction must contain
the number of the desired
register
4) Immediate
— The value of the operand is
contained in a field in the
 Instruction Types

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 Number of Addresses

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 Common Instruction Set Operations

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 Common Instruction Set Operations (cont’d)

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 Common Instruction Set Operations (cont’d)

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 Contents
— Instruction sets: Characteristics and functions
— Instruction sets: Addressing modes and formats
— Processor structure and function

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 Addressing Modes

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 Addressing Modes
— A = contents of an address field in the instruction
— R = contents of an address field in the instruction that refers to a register
— EA = actual (effective) address of the location containing the referenced
operand
— (X) = contents of memory location X or register X

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 Immediate Addressing
— Simplest form of addressing
— Operand = A
— This mode can be used to define and use constants or set initial
values of variables
— Typically the number will be stored in twos complement form
— The leftmost bit of the operand field is used as a sign bit
— Advantage:
— No memory reference other than the instruction fetch is required to
obtain the operand, thus saving one memory or cache cycle in the
instruction cycle
— Disadvantage:
— The size of the number is restricted to the size of the address field,
which, in most instruction sets, is small compared with the word
length

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 Direct Addressing
— Address field contains the effective address of the
operand
— Effective address (EA) = address field (A)
— Was common in earlier generations of computers
— Requires only one memory reference and no special
calculation
— Limitation is that it provides only a limited address
space

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 Indirect Addressing
— Reference to the address of a word in memory which contains a
full-length address of the operand
— EA = (A)
— Parentheses are to be interpreted as meaning contents of
— Advantage:
— For a word length of N an address space of 2N is now available
— Disadvantage:
— Instruction execution requires two memory references to fetch the
operand
— One to get its address and a second to get its value
— A rarely used variant of indirect addressing is multilevel or
cascaded indirect addressing
— EA = ( . . . (A) . . . )
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— Disadvantage is that three or more memory references could be
required to fetch an operand
 Register Addressing
— Address field refers to a register rather than a main memory
address
— EA = R
— Advantages:
— Only a small address field is needed in the instruction
— No time-consuming memory references are required
— Disadvantage:
— The address space is very limited

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 Register Indirect Addressing
— Analogous to indirect addressing
— The only difference is whether the address field refers to a memory location
or a register
— EA = (R)
— Address space limitation of the address field is overcome by
having that field refer to a word-length location containing an
address
— Uses one less memory reference than indirect addressing

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 Displacement Addressing
— Combines the capabilities of direct addressing and register
indirect addressing
— EA = A + (R)
— Requires that the instruction have two address fields, at least
one of which is explicit
— The value contained in one address field (value = A) is used
directly
— The other address field refers to a register whose contents are
added to A to produce the effective address
— Most common uses:
— Relative addressing
— Base-register addressing
— Indexing
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 Relative Addressing
— The implicitly referenced register is the program counter (PC)
— The next instruction address is added to the address field to produce the EA
— Typically the address field is treated as a twos complement number for this
operation
— Thus the effective address is a displacement relative to the address of the
instruction
— Exploits the concept of locality
— Saves address bits in the instruction if most memory references
are relatively near to the instruction being executed

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 Base-Register Addressing
— The referenced register contains a main memory address and the
address field contains a displacement from that address
— The register reference may be explicit or implicit
— Exploits the locality of memory references
— Convenient means of implementing segmentation
— In some implementations a single segment base register is
employed and is used implicitly
— In others the programmer may choose a register to hold the base
address of a segment and the instruction must reference it
explicitly

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 Indexed Addressing
— The address field references a main memory address and the referenced
register contains a positive displacement from that address
— The method of calculating the EA is the same as for base-register
addressing
— An important use is to provide an efficient mechanism for performing
iterative operations
— Autoindexing
— Automatically increment or decrement the index register after each reference
to it
— EA = A + (R)
— (R) ç (R) + 1
— Postindexing
— Indexing is performed after the indirection
— EA = (A) + (R)
— Preindexing
— Indexing is performed before the indirection
22 — EA = (A + (R))
 Stack Addressing
— A stack is a linear array of locations
— Sometimes referred to as a pushdown list or last-in-first-out
queue
— A stack is a reserved block of locations
— Items are appended to the top of the stack so that the block is
partially filled
— Associated with the stack is a pointer whose value is the
address of the top of the stack
— The stack pointer is maintained in a register
— Thus references to stack locations in memory are in fact
register indirect addresses
— Is a form of implied addressing
— The machine instructions need not include a memory
reference but implicitly operate on the top of the stack
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 Instruction Formats

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 Contents
— Instruction sets: Characteristics and functions
— Instruction sets: Addressing modes and formats
— Processor structure and function

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 Processor Organization
— Processor requirements:
— Fetch instruction (from memory (register, cache, main
memory)
— Interpret instruction (what action is required)
— Fetch data (data from memory or an I/O module)
— Process data (performing some operations on data)
— Write data (writing result to memory or an I/O module)
è In order to do these things the processor needs to store some
data temporarily and therefore needs a small internal memory

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 Register Organization
— Within the processor there is a set of registers that
function as a level of memory above main memory
and cache in the hierarchy
— The registers in the processor perform two roles:
User-Visible Registers Control and Status Registers

n Enable the machine or n Used by the control unit

assembly language
programmer to minimize
main memory references
by optimizing use of
registers
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to control the operation
of the processor and by
privileged operating
system programs to
control the execution of
programs
 Program Status Word (PSW)
— Register or set of registers that contain status
information
— Common fields or flags include:
— Sign
— Zero
— Carry
— Equal
— Overflow
— Interrupt Enable/Disable
— Supervisor

— Status information are used to give a decision for

branching

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 Instruction Pipelining Strategy
— A way to improve performance is performing jobs in
parallel manner
— An assembly line in which some operations are
performed concurrently
— Similar to the use of an assembly line in a
manufacturing plant
— New inputs are accepted at one end before previously
accepted inputs appear as outputs at the other end
— To apply this concept to instruction execution we must
recognize that an instruction has a number of stages

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 Instruction Stages
— Fetch instruction (FI)
— Read the next expected instruction into a buffer
— Decode instruction (DI)
— Determine the opcode and the operand specifiers
— Calculate operands (CO)
— Calculate the effective address of each source operand
— This may involve displacement, register indirect, indirect, or other forms of
address calculation
— Fetch operands (FO)
— Fetch each operand from memory
— Operands in registers need not be fetched
— Execute instruction (EI)
— Perform the indicated operation and store the result, if any, in the specified
destination operand location
— Write operand (WO)
— Store the result in memory
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 Timing Diagram for Instruction
Pipeline Operation

I: Instruction
O: operand
F: Fetch
C: Calculate
F: Fetch
E: Execute
W: Write

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 Pipeline Hazards
Occur when the pipeline, or There are three types
some portion of the of hazards:
pipeline, must stall (trì
hoãn) because conditions do •Resource
not permit continued •Data
execution •Control

Also referred
to as a
pipeline
bubble

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 Resource Hazards
— A resource hazard
occurs when two or
more instructions that
are already in the
pipeline need the
same resource
— The result is that the
instructions must be
executed in serial
rather than parallel
for a portion of the
pipeline
— A resource hazard is
sometimes referred to
as a structural hazard
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 Data Hazards
— A data hazard occurs when there is a conflict in the access of an
operand location
Instruction is executing and the register
EAX is writing to. So, it can not be read.

X86
instruction

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 Types of Data Hazards
— Read after write (RAW), or true dependency
— An instruction modifies a register or memory location
— Succeeding instruction reads data in memory or register location
— Hazard occurs if the read takes place before write operation is
complete
— Write after read (WAR), or antidependency
— An instruction reads a register or memory location
— Succeeding instruction writes to the location
— Hazard occurs if the write operation completes before the read
operation takes place
— Write after write (WAW), or output dependency
— Two instructions both write to the same location
— Hazard occurs if the write operations take place in the reverse
order of the intended sequence
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 Control Hazards
— Also known as a branch hazard
— Occurs when the pipeline makes the wrong decision on a
branch prediction
— Brings instructions into the pipeline that must subsequently be
discarded

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 Control Hazards (cont’d)

At the time 7, the

instruction 3 executes
and the instruction 15 is
loaded.

These jobs are wasted

Suppose that the
instruction 3 is a
branch to the
instruction 15

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 Control Hazards (cont’d)

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 Exercises
— 14.1-14.4, 14.8-14.10

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 Exercises

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 Exercises

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 Exercises

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