Reliability and failure analysis in power GaN-

HEMTs: an overview

Matteo Meneghini, Isabella Rossetto, Carlo De Santi, Fabiana Rampazzo, Alaleh Tajalli, Alessandro Barbato,
Maria Ruzzarin, Matteo Borga, Eleonora Canato, Enrico Zanoni and Gaudenzio Meneghesso

University of Padova, Department of Information Engineering,

Via Gradenigo 6/B, 35131
Padova, Italy
Phone: +39 049 827 7664, email: matteo.meneghini@dei.unipd.it

Abstract—Power GaN transistors have recently demonstrated to
be excellent devices for application in power electronics. The
high breakdown field and the superior mobility of the 2-
dimensional electron gas allow to fabricate transistors with low
resistive and switching losses, that permit to increase the
efficiency of switching mode power converters beyond 99 %.
GaN-based transistors are currently supposed to be adopted in
KW-range power converters; 650 V transistors are already
available on the market, and 1200 V devices are currently under
development.
During operation, GaN power transistors can reach critical
conditions, especially in the off-state (with a high VDS, in excess
of 650 V), during hard-switching (where high current and
voltage can be simultaneously present), and for high positive
gate voltages (in the case of normally-off devices).
This paper reports our most recent results on the gradual and
catastrophic degradation of GaN-based power HEMTs. We
present the results of three different case studies, on: (i) the
time-dependent breakdown of power HEMTs submitted to high
off-state stress; (ii) the degradation of HEMTs with p-GaN gate
submitted to high gate stress; (iii) the hot electron effects in
GaN-MISHEMTs submitted to high-temperature source current
stress.
Index Terms—GaN, transistor, reliability, defect, degradation
I. INTRODUCTION
Over the last few years, the research in the field of GaN
power transistors has shown impressive advancements [1].
Gallium nitride has a wide energy gap (3.4 eV), that allows for
high temperature operation. GaN transistors can remain fully
functional well above 300 °C, with an excellent control of the
channel current [2]. In addition, GaN has a breakdown field of
3.3 MV/cm, which is approximately ten times higher than that
of silicon. For the same breakdown voltage, GaN-based
transistors are ~10 times shorter/thinner with respect to the
silicon counterpart, and this results in a significant reduction
of the on-resistance of the devices. GaN transistors with
breakdown voltages higher than 1900 V have already been
demonstrated [3], thanks to the optimization of the buffer
structure and/or to the adoption of specific methods for
substrate removal.
In AlGaN/GaN transistors, the channel is formed at the
heterointerface between a larger gap material (AlGaN) and
GaN, due to the spontaneous and piezoelectric polarization,
without the need of any doping. For this reason, the mobility
of the channel is extremely high (>2000 cm2/Vs [4]), resulting
in current densities >1 A/mm. Commercial 650 V/60 A
devices can have a very low on resistance (<25 mΩ, [5]); this
has a positive impact on the resistive losses of the transistors,
when they are used in switching mode power converters.
Finally, GaN transistors have a low Ron·Qg product (product of
on-resistance and gate charge), smaller than 1 nC·Ω, and – as
a consequence – very low switching losses.
Compared to the silicon counterparts, power converters
based on GaN will be therefore lighter (since they will require
smaller heat sinks), smaller (the lower switching losses will
permit to increase the switching frequency, and to use smaller
passives), and more efficient (thanks to the lower resistive and
switching losses). But…what about reliability?
In a switching mode power converter (see the simplified
boost circuit in Figure 1), the transistors is continuously
switched from the off-state to the on-state and vice versa.
When the transistor is in the off-state, a high voltage (up to
650 V) is applied between drain and substrate, drain and
source, and between drain and gate.
Load
Vin Driver HEMT
VDS 650 V
OFF, ON,
VGS=0 V, VGS>5 V,
ID=0 A high ID
Figure 1: (top) simplified representation of a switching mode power
converter (boost configuration); (bottom) simplified representation of the
different operating regimes of the transistor in a boost converter

978-1-5090-6641-4/17/$31.00 ©2017 IEEE 3B-2.1

 Bias point Degradation Physical origin Test methodology
mode/process
Off-state Dynamic-Ron Buffer trapping [29], due to -Pulsed ID-VDS characterization [31]
increase
-ionization of buffer acceptors [30] -“on-the-fly” measurements [31]
-injection of electrons from the substrate -backgating tests [32], [33]
[7]
-substrate ramps [34]
Surface trapping due to -surface leakage measurements [36]
-injection of electrons from gate to -analysis of the trapping transients with
drain, due to poor passivation [35] drain connected to substrate [33]
Vth shift -trapping/detrapping of electrons in the -Pulsed ID-VGS characterization [37]
gate area [37]
-“on-the-fly” measurements [7]
Time-dependent -generation of source-drain current paths -HTRB testing [40]
degradation [38], [8]
-2-terminal (drain to substrate) stress
-short circuits between gate and channel [39]
[16], [9]
-vertical (drain to substrate) breakdown
[39]
On-state Vth shift (PBTI, -trapping at the gate insulator (for -Pulsed ID-VGS characterization [43]
NBTI) MIS/MOS structures) [39], [41], [37]
-capacitance-voltage-frequency
-electron/hole trapping in the p-GaN (for analysis [43]
transistors with p-GaN gate) [42]
-“on-the-fly” measurements [7]
-analysis of the correlation between Vth
shift and gate leakage [44]
Time-dependent -TDDB (for MIS/MOS structures) [45], -high temperature gate stress testing
gate breakdown [46] [18], [19]
-generation of defects/leakage paths in -constant voltage gate stress [19], [22]
the p-GaN/AlGaN gate stack [20], [18],
[24], [19], [21] - Pulsed ID-VGS/DLTS to investigate
the generation of traps induced by
stress [47]
-electroluminescence to identify the
failed regions [24]
Semi-on Vth shift/increase in -trapping of hot electrons under the gate -constant voltage stress in semi-on
state Ron induced by and at the gate edge [44], [31], [28] conditions [48]
semi-on operation
-generation of lattice defects [26], [27] -High temperature source current
(HTSC) stress [28]
-stress in hard switching [49]
Table I: summary of the degradation mechanisms that take place in a GaN power HEMT under off-state, on-state and semi-on state conditions

This may result in:
-buffer trapping processes, that are responsible for the increase
in dynamic on-resistance; charge trapping may take place due
to both the ionization of acceptor states [6], and to the
injection of electrons from the substrate [7].
-injection of electrons at the gate-drain surface, which can be
avoided through the use of an optimized passivation layer
-time-dependent (permanent) degradation of the devices,
consisting in the increase in source-to-drain leakage [8], or in

3B-2.2
the generation of short circuit paths between the gate and the
channel [9].
When the transistor is in the on-state, the gate is positively
biased at voltages higher than 5-6 V (we consider here the
case of a normally-off device). Normally-off GaN transistors
can be fabricated via the use of MIS/MOS structures with a
partially-recessed gate [10], or through the use of a p-type gate
stack [11]. Both technologies can show reliability issues when
the devices are stressed at high gate voltages [12], [13].
Finally, when the transistor in Figure 1 switches from the off-
state to the on-state, it crosses a semi-on condition, in which
the voltage and current on the drain may be simultaneously
high (grey areas in Figure 1). This “hard-switching” condition
can originate from the discharge of the drain-source
capacitance of the transistor (when the HEMT is switched
from off- to on-state, [14], [15]), and/or from a poor
optimization of the dead times of the switching events (in a
half-bridge circuit). The simultaneous presence of high current
and voltage on the drain may favor hot electron
trapping/degradation effects, which reduce the
performance/reliability of the devices.
that the off-state degradation of GaN-HEMTs is a time-
dependent process. In [16], we showed that devices with a
breakdown voltage higher than 1000 V (measured by a dc
sweep) can show a time-dependent failure when submitted to
constant voltage stress at VDS=600-700 V. During an off-state
stress test with VDS=600 V the devices showed a sudden
increase in gate-drain leakage, with an average time-to-failure
in the order of 20 ks.
A detailed analysis of the variation of drain/gate current
during stress is reported in Figure 3 (a). Current shows a step-
wise increase, until the catastrophic failure is reached. The
stress test was interrupted repeatedly, to measure the gate
leakage; the results (Figure 3 (b)) indicate that gate leakage
shows a significant increase even before catastrophic failure.
100 1000
10 -1 Gate, Source and 900
10-2
Substrate grounded
Drain voltage from 0V 800
10-3

Drain Stress Voltage (V)

to failure, 20V/step

Drain Current (A)

700
10-4
Table I summarizes the most critical degradation processes
that are induced by off-state, on-state and semi-on state stress, 10-5 600
along with the related failure modes; we also report here the 10-6 500
test methodologies that have been proposed for the analysis of -7
these degradation mechanisms. 10 400
10-8
In the following we summarize the results of three recent case Breakdown at 800V 300
studies that we have carried out to investigate the physical 10-9
origin of degradation under off-state, on-state and semi-on 200
10-10
state. Three different technologies have been investigated, 100
Schottky-gated HEMTs (for the analysis of degradation under 10-11
off-state), HEMTs with a p-GaN gate (for the analysis of 10-12
0
degradation under positive gate bias), and MIS-HEMTs (for 0 1000 2000 3000 4000 5000
the study of hot electron effects induced by the simultaneous time (s)
presence of high voltage and current at the drain). The results
obtained on test structures from different laboratories are
compared to those obtained on commercially-available 100 1200
transistors bought off-the-shelf. 10-1
10-2 Failure at 1020V 1000
II. DEGRADATION OF GAN HEMTS IN THE OFF-STATE
-3
10

Drain Stress Voltage (V)

A quick method to evaluate the degradation limits of
Drain Current (A)

devices under off-state stress is to use step-stress experiments. 10-4 800

With source and substrate grounded, the devices are biased in 10 -5

the off-state (with a negative gate bias for normally-on devices

and a null gate bias for normally-off devices), and the drain 10-6 600
voltage is increased until failure. Figure 2 reports 10 -7

representative results obtained on two commercially-available 10-8 400

HEMTs fabricated by different vendors. The drain voltage is
increased by 20 V every 120 s; the drain current is monitored 10 -9
Gate, Source and
during the execution of the stress experiment. A catastrophic 10-10 Substrate grounded 200
failure (corresponding to a sudden increase in drain current) is Drain voltage from 0V
10-11
reached for VDS=800 V (Figure 2, top) and for VDS=1020 V to failure, 20V/step
(Figure 2, bottom). These values are well above the 600-650 V 10-12 0
maximum voltage of the transistors currently-available on the 0 1000 2000 3000 4000 5000 6000
market. This result indicates that commercial devices can time (s)
withstand kV-range voltages during a short-term step-stress.
Figure 2: results of an off-state stress test carried out on two commercial
Recent papers indicated that things might be different normally-off devices from two different vendors
during the execution of long-term experiments, due to the fact

3B-2.3
 Figure 3: (a) Constant voltage stress performed on a representative device
at gate voltage = –5 V, drain voltage = 600 V, and source and substrate
grounded. (b) Diode current–voltage curve monitored after four defined steps
during the stress, as reported in (a). @2017 IEEE. Reprinted, with permission,
from I. Rossetto, M. Meneghini, S. Pandey, M. Gajda, G. A. M. Hurkx, J. A. Figure 4: Emission microscopy evaluated during stress with VGS = –5 V
Croon, J. Šonský, G. Meneghesso, and E. Zanoni, “Field-Related Failure of and VDS = 600 V. The three frames are referred to increasing stress times,
GaN-on-Si HEMTsௗ: Dependence on Device Geometry and Passivation,” shown in Figure 3. The portion cut for the TEM evaluation in Figure 5 is
IEEE Trans. Electron Devices, vol. 64, no. 1, pp. 73–77, 2017. highlighted in yellow @2017 IEEE. Reprinted, with permission, from I.
Rossetto, M. Meneghini, S. Pandey, M. Gajda, G. A. M. Hurkx, J. A. Croon,
J. Šonský, G. Meneghesso, and E. Zanoni, “Field-Related Failure of GaN-on-
Si HEMTsௗ: Dependence on Device Geometry and Passivation,” IEEE Trans.
Electroluminescence microscopy can be used as a tool to Electron Devices, vol. 64, no. 1, pp. 73–77, 2017.
identify the position of the failure. The results in Figure 4
were obtained during the constant voltage stress in Figure 3,
and demonstrate that the sudden increase in gate/drain current
is correlated to the appearance of a “hot-spot”.
TEM analysis was carried out by cross sectioning the
devices in correspondence of the failed regions identified by
electroluminescence microscopy. The results Figure 5
indicated a severe degradation located at the drain-side gate
edge. Constant voltage stress induced the generation of a
short-circuit path between the gate-head edge and the 2DEG.
The time-dependent degradation of the transistors can
therefore be ascribed to the failure of the silicon nitride at the
gate head, where the electric field has a peak and reaches
values higher than 6 MV/cm [16]. A substantial improvement
in reliability can be obtained by adding a graded SiN
passivation under the gate-head, as proposed and
demonstrated in [9].
Figure 5: (a) TEM performed on a cross section corresponding to the hot
spot indicated in Figure 4, after the constant voltage test, showing a severe
degradation in the gate side/edge. (b) Enlargement of the damaged portion of
III. HEMTS WITH P-GAN GATE: ROBUSTNESS TOWARDS the device @2017 IEEE. Reprinted, with permission, from I. Rossetto, M.
POSITIVE GATE STRESS Meneghini, S. Pandey, M. Gajda, G. A. M. Hurkx, J. A. Croon, J. Šonský, G.
Meneghesso, and E. Zanoni, “Field-Related Failure of GaN-on-Si HEMTsௗ:
Normally-off devices must be able to withstand a positive Dependence on Device Geometry and Passivation,” IEEE Trans. Electron
gate bias without showing degradation. Commercially Devices, vol. 64, no. 1, pp. 73–77, 2017.
available devices have an absolute maximum gate voltage
swing of -10 V/4.5 V (for [17]), -10 V/7 V (for [5]),
depending on the manufacturer. It is therefore important to Figure 6 reports the results of a step-stress experiment
evaluate how/if the devices show a failure when they are carried out on a commercially-available GaN-based transistor
submitted to positive gate stress, and to identify the related submitted with positive gate bias. The gate voltage was
degradation modes and mechanisms. increased by 0.25 V every 120 s, and the corresponding gate
current was continuously monitored. The staircase represents
the voltage applied to the gate of the device. As can be
noticed, failure is reached at VGS=10 V, i.e. above the
maximum rating of the devices.
The step-stress induced both a gradual and a permanent
degradation. Gradual degradation consists mostly in a negative

3B-2.4
shift in threshold voltage (-0.6 V total, see Figure 7) that can
be ascribed to the accumulation of positive charge within the 0.10
structure. A possible source of positive charge can be the holes 0.05
injected from the gate with positive gate bias. Reducing gate
0.00
leakage can limit hole injection, and therefore reduce this
-0.05
negative threshold shift.

Treshold Voltage (V)

-0.10
100 11 -0.15

10-1 -0.20
10
-0.25
10-2 9 -0.30
10-3 8 -0.35

Gate Stress Voltage (V)

Gate Current (A)

10-4 -0.40
7 -0.45
10-5
6 -0.50
10-6 -0.55 Vth measured at VDS=3 V
5
-7 -0.60
10 0 1 2 3 4 5 6 7 8 9 10 11
4
10-8 Gate Voltage Stress (V)
Drain, Source and 3
10-9
Figure 7: variation of threshold voltage during the step-stress of a
10-10
Substrate grounded 2 normally-off commercially-available GaN HEMT (same device as in Figure
Gate voltage from 0V 6)
10-11 1
to failure, 0.25V/step
10-12 0 100
0 1000 2000 3000 4000 5000 GS DIODE
-1
10 VG = 10.75V
time (s) 10 -2

Figure 6: results of a positive gate step-stress carried out on a commercial 10-3

Gate Current (A)

normally-off device. The gate voltage was increased by 0.25 V every 120 s
until failure 10-4

10-5
Increasing
A possible way to reduce gate leakage is to use a Schottky- 10-6 Gate Voltage
type metal/semiconductor contact to p-GaN [18]. It is worth during the stress
10-7
noticing that no significant change in the I-V curves of the
gate diode is detected before catastrophic failure (see Figure 10-8
8). 10-9

Recent studies carried out on suitable test structures [12], 10-10

[19], [20], [21], [22] demonstrated that the degradation of 10-11
GaN-HEMTs with p-type gate can be a time-dependent -6 -5 -4 -3 -2 -1 0 1 2 3 4
process. In Figure 9 we report the results obtained in an early Gate Voltage (V)
study on the topic, obtained by submitting a transistor to
constant voltage stress. During stress, gate current shows a Figure 8: variation of the I-V characteristics of the gate diode during the
gradual/stepwise increase, until failure is reached. The EL step-stress of a normally-off commercially-available GaN HEMT (same
pattern shown in Figure 9 indicate that failure occurs in a device as in Figure 6)
localized region, where a short circuit path is generated.
Different mechanisms have been proposed as responsible The time-to-failure was found to be Weibull-distributed
for the degradation: [19], and strongly influenced by the stress voltage applied to
1. The time-dependent breakdown of the p-GaN layer, the gate. A careful optimization of the growth and processing
due to the high electric field reached during positive conditions permits to obtain a 20 years lifetime at voltages
gate stress [23] higher than 5-7 V [24], [23], thus satisfying the requests from
the market.
2. Avalanche breakdown processes, that may lead to a
significant increase in the gate leakage current [23] IV. STRESS IN SEMI-ON CONDITIONS
3. The generation of donor-like traps in the p-GaN, close
to the interface with AlGaN, causing a local lowering In hard switching conditions, GaN HEMTs may be
of the electric field in the AlGaN and providing simultaneously subject to high drain voltage and non-
localized leakage paths [19] negligible drain current. Electrons injected from the source

3B-2.5

Figure 9: Constant voltage stress for a representative device under test
(source and chuck grounded, gate voltage = 8 V, drain connected to the source
through the 2DEG). (a) Gate current monitored during the stress and (b)
corresponding false color image of the electroluminescence (EL) signal
monitored during the stress (I–IV) at defined time levels (blue lines) @2016
IEEE. Reprinted, with permission, from I. Rossetto, M. Meneghini, O. Hilt, E.
Bahat-treidel, C. De Santi, S. Dalcanale, J. Wuerfl, E. Zanoni, and G.
Meneghesso, “Time-Dependent Failure of GaN-on-Si Power HEMTs With p-
GaN Gate,” IEEE Trans. Electron Devices, vol. 63, no. 6, pp. 2334–2339,
2016
may be accelerated by the electric field thus becoming
“hot”. Hot electrons may induce both a recoverable
degradation, when they are trapped in the gate-drain access
region [25], or a permanent worsening of the electrical
performance of the transistors, if their energy is sufficient to
promote the generation of lattice defects [26], [27].
Several methods can be used to investigate the impact of
hot electrons on the performance/stability of the devices,
including testing in hard switching conditions [14]. Recently,
we have proposed a simple method to evaluate if the HEMTs
suffer from hot electron degradation, based on high
temperature source current (HTSC) stress tests [28]. In a
conventional high temperature reverse bias (HTRB)
experiment, the transistor is biased in the off-state. In this way
it is possible to evaluate the impact of high electric field on the
stability of the devices, in absence of hot electrons.
On the other hand, during a HTSC stress, both high drain
bias and a measurable drain-source current are present. The
idea is to bias the devices in the semi-on state, with a high
drain bias, by pulling a constant current IS out of the source. In
this way, it is possible to inject a controllable flow of hot
electrons. The density of hot electrons is proportional to
source current, while the energy of hot electrons is defined by
the drain voltage. The variation of on-resistance and of
threshold-voltage can be monitored by on-the-fly
measurements, during the execution of the stress experiments.
Figure 10 shows representative data obtained by stressing
GaN MIS-HEMTs with a drain voltage of VDS=150 V, in
HTRB conditions (off-state, no drain-source current) and
HTSC conditions (semi-on state, high VDS and measurable
source current). The stress temperature is 150 °C.
Figure 10: Variation of the on resistance measured during (a) the 200 s of
stress and (b) 5000 s of recovery (during recovery the normalized Ron of the
sample stressed at VGS = í10 V - HTRB - is smaller than 1 possibly due to the
detrapping of electrons from the dielectric/AlGaN interface; the same effect is
responsible for the negative Vth shift) ©2016 IEEE. Reprinted, with
permission, from M. Ruzzarin, M. Meneghini, I. Rossetto, M. Van Hove, S.
Stoffels, T. L. Wu, S. Decoutere, G. Meneghesso, and E. Zanoni, “Evidence of
Hot-Electron Degradation in GaN- Based MIS-HEMTs Submitted to High
Temperature Constant Source Current Stress,” IEEE Electron Device Lett.,
vol. 37, no. 11, pp. 1415–1417, 2016.
As can be noticed, HTRB stress did not induce any
significant degradation in the on-resistance of the devices. On
the other hand, HTSC stress was found to favor a
(recoverable) increase in on-resistance, that becomes stronger
by increasing the current pulled from the source.
Under HTSC conditions, the increase in on-resistance is
due to the injection/trapping of hot electrons from the source.
With increasing temperature, the increase in on-resistance
becomes less prominent [28], since the average energy of hot
electrons is reduced by the increased scattering with the
lattice.
V. CONCLUSIONS
In summary, GaN-based HEMTs are almost ideal devices
for application in power converters. The reliability of these
transistors can still be limited by the existence of specific
degradation processes, that impact on the static and on the
dynamic performance of the devices. In this paper we have
summarized recent results on the physical origin of
degradation in GaN-based transistors, showing that through
careful optimization of the structure/design of the devices it is
possible to minimize the effects of stress.
ACKNOWLEDGEMENTS
This activity was partly supported by the ENIAC project
E2COGAN (Energy Efficient Converters using GaN Power
Devices).
3B-2.6

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