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INTRODUCTION TO VHDL
•
The acronym VHDL stands for VHSIC-HDL (Very High Speed Integrated Circuit
Hardware Description Language).
•
VHDL is a hardware description language that is used to describe the behavior and structure
of digital systems.
•
VHDL is a general-purpose hardware description language which can be used to describe
and simulate the operation of a wide variety of digital systems, ranging in

complexity from a few gates to an interconnection of many complex integrated

circuits.
•
VHDL can describe a digital system at several different levels—behavioral, data flow,
and structural.

What is HDL?

•
HDL stands for Hardware Description Language. It is a programming language that is
used to describe, simulate, and create hardware like digital circuits
(ICS).
•
HDL is mainly used to discover the faults in the design before implementing it in the

hardware.
•
Today, there are many HDLs available in the market, but VHDL and Verilog are the most
popular HDLs.

What is VHDL?

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•
VHDL stands for Very High-Speed Integration Circuit HDL (Hardware Description
Language).
•
It is an IEEE (Institute of Electrical and Electronics Engineers) standard hardware
description language that is used to describe and simulate the behavior of complex digital
circuits.
•
The most popular examples of VHDL are Odd Parity Generator, Pulse Generator,
Priority Encoder, Behavioral Model for 16 words, 8bit RAM, etc.
What is Verilog?

•
Verilog is also a HDL (Hardware Description Languages) for describing electronic

circuits and systems. It is used in both hardware simulation and synthesis.

•
The most popular examples of Verilog are network switch, a microprocessor, a memory, a
simple flip-flop, etc.

Difference between VHDL and Verilog

VHDL Program Structure

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Basic Elements of VHDL are

1. Entity
The Entity is used to specify the input and output ports of the circuit. An Entity
usually has one or more ports that can be inputs (in), outputs (out), input-outputs
(inout), or buffer.

Entity Declaration

You can declare an entity using the following syntax:

Simplified syntax

entity entity_name is
port (
Port_1_name : mode data_type;
Port_2_name : mode data_type;
.......

Port_n_name : mode data_type;

);
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end entity_name;

Example:
entity orgate is

port (
a : in std_logic;
b : in std_logic; c:
out std_logic
);
end orgate;
2. Architecture
Architecture is the actual description of the design, which is used to describe
how the circuit operates. It can contain both concurrent and sequential
statements.

Architecture Declaration
An architecture can be declared using the following syntax:
architecture architecture_name of entity_name is

begin

(concurrent statements )

end architecture_name;

Example: architecture
og of orgate is

begin
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c <= a OR b; end
og;

VHDL Operators

• VHDL Operators are used for constructing the expressions.

• There are the following types of operators in VHDL

1. Logical Operators

• Logical Operators are used to control the program flow. When the logical operators
combined with signals or variables, then it is used to create combinational logic.
• VHDL supports the following logical operators

  and
  or
  nand
  nor
  xor

  xnor

  not

2. Relational Operators

In VHDL, relational operators are used to compare two operands of the same

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data type, and the received result is always of the Boolean type.

VHDL supports the following Relational Operators

• = Equal to

• /= Not Equal to
• < Less than
• > Greater than
• <= Less than or equal to
• >= Greater than or equal to
3. Arithmetic Operators

Arithmetic Operators are used to perform arithmetic operations. These

operators are numeric types, such as integer and real.

VHDL uses the following Arithmetic Operators

o + Addition

o - Subtraction
o * Multiplication o / Division o & Concatenation o mod
Modulus
o rem Remainder

o abs Absolute Value

• ** Exponentiation

4. Shift Operators

In VHDL, shift operator is used to perform the bit manipulation on the data by
shifting and rotating the bits of its first operand right or left.

VHDL supports the following Miscellaneous Operators

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o Sll shift logical left

o Srl shift logical right
o Sla shift arithmetic
left o Sra shift
arithmetic right
o Rol rotate left o Ror
rotate right Types of
Modeling styles in
VHDL

There are 3 types of modeling styles in VHDL. Consider the following logic diagram.

• Data flow modeling (Design Equations)

Data flow modeling can be described based on the Boolean expression. It
shows how the data flows from input to output. It works on Concurrent execution.
The expression for the above logic diagram is
C <= A and B ;
E <= C or D ;

• Behavioral modeling (Explains Behaviour)

Behavioral modeling is used to execute statements sequentially. It shows that how
the system performs according to the current statement.
Behavioral modeling may contain Process statements, Sequential statements,
Signal assignment statements, and wait s tatements.
The expression for the above logic diagram is
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E <= D or (A and B);
• Structural modeling (Connection of sub modules)
Structural modeling is used to specify the functionality and structure of
the circuit. Structural modeling contain signal declarations, component instances, and port
maps in component instance.
The expression for the above logic diagram is
Gate1: AND2 port map (A, B, C);
Gate2: OR2 port map (C, D, E);
“ if ” Statement

There are boolean expressions after the keywords “if” and “elsif”. These boolean
expressions are either true or false. The boolean expressions will be evaluated successively
until a true expression is found. The assignment corresponding to this

true expression will be performed. If none of these expressions are true, the assignment
after the “else” keyword will be executed.

Syntax:

4 to 1 MUX using if Statement

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The “Case” Statement

Syntax:

The value of the control_expression, which comes between the keywords “case” and “is”,
will be compared with the n possible options, i.e., option_1, option_2, ..., option_n. When
a match is found, the assignment corresponding to that particular option will be
performed.

4 to 1 MUX using CASE Statement

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VHDL MODELS FOR MULTIPLEXERS

The following Figure shows a 4-to-1 multiplexer (MUX) with four data inputs, two
control input, and one output.

The logic equation for the 4 -to-1 MUX is 𝐹 = 𝐴′ 𝐵′𝐼0 + 𝐴′ 𝐵𝐼1 + 𝐴𝐵′𝐼2 + 𝐴𝐵𝐼3.
We can write VHDL code in 3 different ways.

1) Using Data flow Description

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F <= ((not A) and (not B) and I0) or
((not A) and B and I1) or
(A and (not B) and I2) or
(A and B and I3);

2) Using Conditional assignment statement

Syntax

Output_signal <= value_1 when expression_1

else value_2 when expression_2
else value_n;

In this type of statement value_1 is assigned to output signal for expression 1, value_2 is
assigned to output signal for expression 2 and value n is assigned to output signal for last
condition.
Example Using Conditional assignment statement

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3) Using Selected signal assignment statement

Syntax

with control_expression select

Output_signal <= value_1 when option_1,
value_2 when option_2,

... value_n when others;

In this type of statement value_1 is assigned to output signal for option 1, value_2 is
assigned to output signal for option 2 and value n is assigned to output signal for
others.
Example Using Selected signal assignment statement

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Structural description Example

Four-Bit Adder

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Fig. 4-Bit Full Adder

Four bit adder consists of four full adders connected to form a 4-bit binary adder.

Full adder Program

Four-Bit Adder Program

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