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    Mahender Veshala
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    The document outlines the units and topics covered in a semester-long course on VLSI digital design, including building blocks for digital design, building blocks with memory, design methods, case studies, hierarchical modeling concepts, FPGA architecture, and the design process flow. Key topics include adders, ALUs, registers, RAM, ROM, PLA, PAL, state machines, multiplexer controllers, behavioral modeling, FPGA types from Xilinx and Altera, and the design capture, validation, and implementation steps. The course will be evaluated based on a 3-hour university exam worth 100 marks and sessionals worth 50 marks.

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    The document outlines the units and topics covered in a semester-long course on VLSI digital design, including building blocks for digital design, building blocks with memory, design methods, case studies, hierarchical modeling concepts, FPGA architecture, and the design process flow. Key topics include adders, ALUs, registers, RAM, ROM, PLA, PAL, state machines, multiplexer controllers, behavioral modeling, FPGA types from Xilinx and Altera, and the design capture, validation, and implementation steps. The course will be evaluated based on a 3-hour university exam worth 100 marks and sessionals worth 50 marks.

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    8 views1 page

    9667 Syllabus

    Uploaded by

    Mahender Veshala
    The document outlines the units and topics covered in a semester-long course on VLSI digital design, including building blocks for digital design, building blocks with memory, design methods, case studies, hierarchical modeling concepts, FPGA architecture, and the design process flow. Key topics include adders, ALUs, registers, RAM, ROM, PLA, PAL, state machines, multiplexer controllers, behavioral modeling, FPGA types from Xilinx and Altera, and the design capture, validation, and implementation steps. The course will be evaluated based on a 3-hour university exam worth 100 marks and sessionals worth 50 marks.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    e\A,lFIa)

    gtr7
    VLSI 12 Digital Design
    Class: M.Tech I Semester
    Branch: CSE Lectures :3periods
    Duration of Univ. Exam: 3 Hours Univ.Exam :l00Marks
    Sessionals : S0 Marks

    UNIT - I
    Building Blocks for Digital Design:
    Demurritrr"'"rr, DJcoders, Encoders, comparators,
    l[t'1|il:T' Adders, ALU, carry-

    Brilding Blocks with Memory:


    building brocks, register-buirding brocks,
    RAM, RoM, pLA, pAL, Timining
    [T*::
    r"sign \Iethocls:
    UNIT - II
    ,
    Ekments of design styre, top-down Machines,
    ASM chart notations.
    Realizing ASMS:
    Traditional synthesis from ASM chart.
    multiplexer controller method, on-shot
    ROlvl based method. method,

    Ihsftn Case Studies:


    singlepuisar, system clock, serialto parallel
    data conversion, traffic Iight controller.

    UNIT - III
    Hierarchiar Modeiling Concepts:
    Design methodologies, Modulesl Module
    parts of a simulation, Design
    simulus blocks Gate rever, data flow, behaviourar,
    -instances, and
    nodeling, PLI, delays.
    *"o.rilg techniques, switch lever

    UNIT - IV
    fpga Architecture:
    clunner+ype FpGA's
    - Xirinx, Acter, programmabre
    - Argotronix, |.,:l.ly:o
    computational Logic Arays array rogic, Altera
    vLSI primitive!, Benchmarking.
    Ilcsfun Process FIow:
    Desig capture, validation, Physical design, placement
    and routing and wireability.

    Tcrt Books:

    r- Prosser, winker,"The A* orDigitar Design,,, prentice


    2- Ken Martin,"Digitar Integrated Lircuit
    Har,rgg4.
    DJsign,,, o.i"ro university press,
    i- Oldfield, Dorf,,'FpGA,s,,, prent iceHall,
    1997.
    2aa2.
    4' Samir Palnitkar.''verilog HDL". Pearson
    Education Asia, New Delhi, 2001

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