Failing to Fail - Achieving Success
in Advanced Low Power Design using UPF
Rick Koster Sushma Honnavara Prasad
Mentor Graphics Broadcom Corporation
13355 Noel Road, Suite #500 2431 Mission College Blvd
Dallas, TX 75240 Santa Clara, CA 95124
+1-972-391-2419 +1-408-505-5823
rick_koster@mentor.com sushma@broadcom.com
ABSTRACT
Low power designs demand aggressive power management, which
adds complexity and creates both verification and implementation
challenges. IEEE Standard 1801 Unified Power Format (UPF)
enables early capture of power intent, early verification of power
management, and automated implementation of power intent in low
power systems. This tutorial presents a high-level overview of UPF
concepts, commands, applications, and flows, for both IP blocks and
systems. Attendees will become familiar with basic power
management concepts, how UPF captures power architecture, UPF
commands, a methodology for modeling IP power intent and
reusing that at a system level, and how to leverage UPF to verify
power management.
Categories and Subject Descriptors
D.3.3 [Programming Languages]: Language Constructs and
Features
B.7.0 [Hardware]: Integrated Circuits - General
Keywords
Low power design and verification, UPF
1. INTRODUCTION
Power density on a system on chip (SoC) is increasing with every
new process node due to shrinking geometries and an increase in
design frequencies. Form-factor limited chips are becoming
thermally constrained, calling for aggressive power reduction
techniques. Every new generation of SoCs is adding more and more
features, and demanding more performance that needs to be met
under aggressive schedules to remain competitive in the ever
changing consumer/technology market. These collectively result in
aggressive power management schemes that tend to make the design
and verification process complex. Enabling early capture of power
intent is therefore critical for complex low power SoCs. UPF is a
standard that is used to define power intent of a design, describe the
power management and enable early modeling of the power intent.
This tutorial gives a high level overview of the concepts, command
and applications of UPF, and how these can be applied at an IP level
and reused at a system level for both implementation as well as
verification.
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ISLPED'14, August 11–13, 2014, La Jolla, CA, USA.
ACM 978-1-4503-2975-0/14/08.
http://dx.doi.org/10.1145/2627369.2631637
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2. UPF
UPF is an evolving standard; it started as Accellera UPF1.0 and
eventually became IEEE1801-2009 aka UPF2.0, and the latest
version of the standard is IEEE1801-2013. UPF is a standard format
for defining power management of a design. It is an extension of
Tool Command Language (TCL). It is defined separately from the
HDL, thus making the HDL power-agnostic. It enables early
verification of power intent, drives verification and implementation
from RTL to Layout.
Using UPF, one can describe the power distribution architecture,
which is composed of power-domains, supply rails and the power
control signals. Power state tables and operating voltages are
captured in the UPF. Special power management cells like isolation,
level shifters, power switches and retention registers are also
described using UPF commands. Power intent is different from
functional intent in that functional intent specifies design
architecture, logic functionality and IP usage.
2.1 Power Domains
A power domain is a collection of instances that are treated as a
group for power management purposes. The instances of a power
domain typically, but do not always, share a primary supply.
2.2 Power Supply Network
Power supply network describes the logical connectivity of the
power supplies, or power rails in the design. This may include
connectivity through power switches. The major components of the
power supply network are: supply ports, supply nets, supply sets
and power switches. Supply sets are a group of related supply nets
that contain functions to represent the supply nets, which can be
defined later and constitute an electrically complete model. Some
supply sets are created implicitly upon creation of a power domain;
these are also called predefined supply sets.
2.3 Strategies
Strategies are rules that specifies where and how to apply isolation,
level-shifting, state retention, and buffering in the implementation of
power intent.
2.3.1 Isolation Strategies
Isolation is a technique used to provide defined behavior of a logic
signal when its driving logic is not active. An Isolation cell is used
to pass normal logic value during normal operation and clamps its
output to some specified logic value when a control signal is
asserted.
Two power domains interact if one contains logic that is the driver
of a net and the other contains logic that is a receiver of the same
net. If the driving logic is powered down, the input to the receiving
logic may float between 1 or 0. This can cause significant current to
flow through the receiving logic, which can damage the circuit. To
avoid this problem, isolation cells are inserted at the boundary of a
power domain to ensure that receiving logic always sees an
unambiguous 1 or 0 value.
2.3.2 Level Shifting Strategies
Two interacting power domains may also be operating with
different voltage ranges. In this case, a logic 1 value might be
represented in the driving domain using a voltage that would not be
seen as an unambiguous 1 in the receiving domain. Level-shifters
are inserted at a domain boundary to translate from a lower to a
higher voltage range, and sometimes from a higher to a lower
voltage range as well. The translation ensures the logic value sent by
the driving logic in one domain is correctly received by the
receiving logic in the other domain.
3. IP POWER INTENT MODELING
IPs are a piece of functionality optimized for power, area and
performance. Soft IPs are handed off as synthesizable HDL
(technology agnostic), while hard IPs are handed off as LEF/GDS
(technology specific). Soft IPs are typically handed off with their
full design UPF, while Hard IPs can be delivered as either UPF
power models or Liberty models.
IP power intent goes through a process of incremental refinement
from constraints to final delivery. The first step involves creation of
IP level constraints, which in turn the following actions:
• Identify "atomic" power domains in the design
• Identify state elements to be retained
• Identify isolation clamp values on ports
• Specify legal power states and sequencing
In the next step, the constraints are configured along with the RTL.
In this step, we do the following:
• Uniquify power domains based on RTL configuration
• Merge power domains
• Create the required power-management ports
• Create isolation strategies to fulfill isolation needs
• Create retention strategies to fulfill retention needs
• Update power states and power transitions
The final step involves implementing the configured power intent.
This is composed of the following:
• Create supply ports and nets
• Update supply set functions
• Update power states with supply values
• Create power switches
• Map strategies to technology specific library cells
4. POWER AWARE VERIFICATION
Traditionally verification of non-Power-Managed design involves
verifying the functionality of the design statically or dynamically
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using vectors which do not involve voltage transitions. Power
Aware verification means verifying Power Managed (or Low
Power) designs which involves verifying the complex Power
management schemes of the Power Controller and make sure that
the design can successfully operate in all the Power states it is
designed for. During the process of verification, various kinds of
bugs are detected which can be categorized into Structural, Control
Sequence and Architectural issues.
4.1 Static Verification
Static Verification is used at both RTL and implemented netlist
level to catch structural Low Power bugs in the design.
Static verification relies on the possible power states of the design.
The objective of static verification is to validate that the design can
function properly in all the possible Power states.
Examples of structural bugs are
a) Missing Isolation on a path that connects a shutdown
domain to a ON domain.
b) Missing Level Shifter between two Power Domains
operating at different voltages.
c) Power Control signals for a block that is ON is driven
from a shutdown block.
d) Incorrect supplies to Always ON buffers, ISO cells
e) Incorrect PG connectivity
4.2 Power Aware Simulation
Power Aware Simulation is used to catch Control sequence and
Architectural Low Power bugs in the design. Power Aware
simulation on top of functional simulation does the following.
a) Simulation of the Supply Network described in the UPF.
b) Shutdown Corruption: When a Power Domain is
shutdown, the gates and registers that are a part of the
domain propagate ‘X’ values during simulation.
c) Virtual Isolation Insertion: Virtual Isolation is simulated
in RTL as described in UPF using Isolation Strategies.
d) Retention Simulation: Retention flops are simulated in
RTL based on retention strategies in UPF by instantiating
shadow latch if required.
Examples of Control Sequence and Architectural bugs are
a) Delayed Isolation Control enable or early Isolation Control
disable
b) Save Restore signal sequencing
c) Corrupt on Activity Simulation: When a Power Domain is in
the Corrupt on Activity state, the inputs to the domain need to
be stable since the domain cannot handle switching. Any input
change in this state is illegal.
d) Illegal Transitions of the Power states
5. REFERENCE
[1] IEEE Standard for Design and Verification of Low-Power
Integrated Circuits (IEEE 1801TM-2013), IEEE, New York,
NY