UNIT-4

Input Output Interface

Input-Output Interface is used as a method which helps in transferring of information
between the internal storage devices i.e. memory and the external peripheral device. A
peripheral device is that which provide input and output for the computer, it is also
called Input-Output devices. For Example: A keyboard and mouse provide Input to the
computer are called input devices while a monitor and printer that provide output to
the computer are called output devices. Just like the external hard-drives, there is also
availability of some peripheral devices which are able to provide both input and output.

In micro-computer base system, the only purpose of peripheral devices is just to

provide special communication links for the interfacing them with the CPU. To resolve
the differences between peripheral devices and CPU, there is a special need for
communication links.
The major differences are as follows:
1. The nature of peripheral devices is electromagnetic and electro-mechanical. The
nature of the CPU is electronic. There is a lot of difference in the mode of operation
of both peripheral devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of
peripheral devices are slow than CPU.
3. In peripheral devices, data code and formats are differ from the format in the CPU
and memory.
4. The operating mode of peripheral devices are different and each may be controlled
so as not to disturb the operation of other peripheral devices connected to CPU.

There is a special need of the additional hardware to resolve the differences between
CPU and peripheral devices to supervise and synchronize all input and output devices.

Functions of Input-Output Interface:

1. It is used to synchronize the operating speed of CPU with respect to input-output

devices.
2. It selects the input-output device which is appropriate for the interpretation of the
input-output device.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also convert digital data into analog signal and vice-versa.

Modes of Transfer

We store the binary information received through an external device in the memory unit.
The information transferred from the CPU to external devices originates from the
memory unit. Although the CPU processes the data, the target and source are always the
memory unit.
We can transfer this information using three different modes of transfer.

1. Programmed I/O
2. Interrupt- initiated I/O
3. Direct memory access( DMA)

Programmed I/O

Programmed I/O uses the I/O instructions written in the computer program. The
instructions in the program initiate every data item transfer. Usually, the data transfer is
from a memory and CPU register. This case requires constant monitoring by the
peripheral device's CPU.

What is the Need?

To understand the need and functioning of the programmed I/O consider a scenario of
human and computer interaction where the human types something on the keyboard.
Now the processor has to save this data into the memory and has to display the same
data on the display device.

With the programmed I/O this entire functioning is regulated with the help of a
program. This action of transferring the typed characters from the keyboard to memory
and then to the display module must happen at the right time.

Let us take this in more detail the input from the keyboard is accepted when the key is
being pressed on the keyboard by the user. And the output can be sent to the display
module only when the module is ready to accept it.

Here the speed at which the data is transferred from the keyboard to the computer
memory depends on the typing speed of the computer. On the other hand, the speed at
which the output data from memory is transferred to the display module is very high.
The speed at which the character can be transmitted and displayed on the display
module is still much slower if compared to the speed of the processor. So, to overcome
the difference in the speed of the processor and I/O device a mechanism must be
implemented to synchronize the transfer of data between the processor and I/O
modules. This is we require programmed I/O

Functioning of programmed I/O

Consider the situation that the processor is busy executing any program. Meanwhile, it
encounters an I/O instruction. To execute the encountered instruction the process supply
an appropriate I/O command to the corresponding I/O module. Accepting the issued
command, the I/O module performs the desired task and sets some appropriate bits of
its I/O status registers. As we have seen in our previous content, the bus structure that
each I/O interface has a set of registers.

Further, the I/O module does not notify the processor that it has performed the desired
task. Moreover, it’s the processors’ responsibility to periodically check the status of the
I/O module till it finds that the I/O has successfully completed the desired task.
If you have observed the function of the programmed I/O it involves two things the I/O
command that is provided by the processor to the I/O module and the I/O instruction that
is encountered and executed by the processor. Let us discuss these two things.

I/O Commands

Whenever the processor experience the I/O related instruction, to execute this I/O
instruction the processor issues two things I/O command and address on the bus which
is decoded by every I/O module connected to the system. Whichever I/O module is
addressed by the processor recognizes this address respond to the issued I/O command.

The processor issue the I/O commands to the I/O module can be of four types.
1. Control: This I/O command activates the I/O module addressed by the processor and
directs it to the task it has to perform. This command can be customized depending upon
the type of peripherals.
2. Test: This I/O command tests the status of the I/O module and its peripherals to ensure
that the addressed peripheral is powered on and available for the task. This command
also tests whether the most recent I/O operation has completed successfully or if any
error has occurred.
3. Read: This I/O command lets the I/O module extract the data from the corresponding
peripheral and store it in its internal buffer. Further, the I/O module can place this data
over the data bus on the processor’s demand.
4. Write: This I/O command lets the I/O module accept the data over the data bus and
transmit it to the corresponding peripheral.

Advantages:
• Programmed I/O is simple to implement.
• It requires very little hardware support.
• CPU checks status bits periodically.

Disadvantages:
• The processor has to wait for a long time for the I/O module to be ready for either
transmission or reception of data.
• The performance of the entire system is severely degraded.

Interrupt-initiated I/O

In the above section, we saw that the CPU is kept busy unnecessarily. We can avoid this
situation by using an interrupt-driven method for data transfer. The interrupt facilities
and special commands inform the interface for issuing an interrupt request signal as soon
as the data is available from any device. In the meantime, the CPU can execute other
programs, and the interface will keep monitoring the i/O device. Whenever it determines
that the device is ready for transferring data interface initiates an interrupt request signal
to the CPU. As soon as the CPU detects an external interrupt signal, it stops the program
it was already executing, branches to the service program to process the I/O transfer, and
returns to the program it was initially running.

Working of CPU in terms of interrupts:

 • CPU issues read command.
• It starts executing other programs.
• Check for interruptions at the end of each instruction cycle.
• On interruptions:-
o Process interrupt by fetching data and storing it.
o See operation system notes.
• Starts working on the program it was executing.

Functioning of Interrupt Driven I/O

In this section, we will study how with the approach of interrupt-driven I/O the data is
exchanged between memory and I/O through the processor. We will first see this entire
scenario from the I/O module’s point of view and then from the processors point of view.

Consider that the data has to be stored in the main memory from the I/O module
as input from the I/O module’s point of view.

1. For this, the processor issues a READ I/O command to the corresponding I/O module
and proceeds with some other useful tasks. It does not wait for the I/O module to get
ready with the desired data.

2. The I/O module then processes this READ I/O command and reads the data from the
addressed peripheral device. The I/O module stores the read data into its data register
and issues an interrupt signal to the processor over the control line in the system bus.

By sending the interrupted signal, the I/O module indicates the processor that now it is
ready for transmitting the data. But, the I/O module has to wait until the processor asks
for the data from the I/O module.

3. When the processor requests the data from the I/O, it places the data over the data
line of the system bus. Once the I/O module transfers the data to the processor it set itself
ready for another I/O transfer.

Now let us discuss this transfer of data between processor and I/O from the professor’s
point of view.

1. So let’s again start, to retrieve data from the I/O module the processor issues a READ
command and proceeds in doing something else.
For example, it starts executing some other program as it may be working on multiple
programs at a time.

2. As we know that whenever the processor is executing any program, after every
instruction cycle it checks for interrupts that have occurred. If it finds the pending
interrupts it responds and serves the occurred interrupt.

3. The moment processor finds the interrupts by the I/O module, it suspends its current
execution and saves the context (e.g., program counter, processor register) to serve the
interrupt.

4. Now processor request data from the I/O module and accept the word of data over the
data line. The processor stores this data onto the memory and restores the context of the
program it was working on and resumes its execution.

The figure below shows you how with the help of interrupt I/O the data transfer is carried
out between memory and I/O. Though it is more efficient than programmed I/O still it
wastes some of the processor’s time. As the transfer of data from memory to the I/O
module or from the I/O module to memory passes through the processor.
 Interrupt Servicing

Till now we have seen the transfer of data between the I/O and memory where the I/O
module signals the processor by issuing an interrupt. Issuing an interrupt triggers many
other events in processors hardware and software which we will discuss in detail in this
section.

1. The I/O device completes the task that the processor has issued to it through the I/O
command and then it signals an interrupt to the processor.
2. The processor executes its current instruction and then check for the interrupt.
3. When the processor determines an interrupt it signals the corresponding I/O device with
an acknowledgment that it has received an interrupt. Receiving the acknowledgment
from the processor, the I/O device withdraw its interrupt signal.
4. The processor now has to transfer the control to the interrupt service routine. But before
switching the control it has to save the information it requires to resume the execution
of the program it was working on at the point of interrupt.
The least information that the processor will require to resume its work at the point of
interrupt is the current status of the processor and the address of the next instruction to
be executed. The processor saves its status in the register program status word (PSW) and
the address of the next instruction to be executed in the program counter. The processor
put this information onto the system control stack.
5. The processor loads the program counter with the address of the entry location of the
appropriate interrupt service routine that will serve the occurred interrupt.
6. Well depending on the computer architecture and the type of operating system you have
there may be a single interrupt handling program for all types of interrupt or there may
be a different program for each type of interrupt.
7. In the case of several interrupt handling programs the processor has to determine which
interrupt handling routine it has to invoke and this information is present in the interrupt
signal issued to the processor by the I/O module. Once this information is acquired the
processor starts the execution of the program service routine.
8. The interrupt service routine serves the occurred interrupt for that the processor checks
the status of the I/O device that signals the interrupt or the event that cause the interrupt.
While serving the interrupt the processor may send some additional commands or
acknowledge to the I/O device.
9. When the interrupt is processed completely the processor restores its register values
from the stack.
10.Finally, the values of the program counter and program status word are restored from
the stack and resume the execution of the interrupted program.

Advantages:
• It is faster and more efficient than Programmed I/O.
• It requires very little hardware support.
• CPU does not check status bits periodically.

Disadvantages:
• It can be tricky to implement if using a low-level language.
• It can be tough to get various pieces of work well together.
• The hardware manufacturer / OS maker usually implements it, e.g., Microsoft.
 Direct Memory Access (DMA)

The data transfer between any fast storage media like a memory unit and a magnetic disk
gets limited with the speed of the CPU. Thus it will be best to allow the peripherals to
directly communicate with the storage using the memory buses by removing the
intervention of the CPU. This mode of transfer of data technique is known as Direct
Memory Access (DMA). During Direct Memory Access, the CPU is idle and has no control
over the memory buses. The DMA controller takes over the buses and directly manages
data transfer between the memory unit and I/O devices.

What is DMA and why it is used?

Direct memory access (DMA) is a mode of data transfer between the memory and I/O
devices. This happens without the involvement of the processor. We have two other
methods of data transfer, programmed I/O and Interrupt driven I/O. Let’s revise each
and get acknowledge with their drawbacks.

In programmed I/O, the processor keeps on scanning whether any device is ready for
data transfer. If an I/O device is ready, the processor fully dedicates itself in transferring
the data between I/O and memory. It transfers data at a high rate, but it can’t get
involved in any other activity during data transfer. This is the major drawback of
programmed I/O.

In Interrupt driven I/O, whenever the device is ready for data transfer, then it raises
an interrupt to processor. Processor completes executing its ongoing instruction and
saves its current state. It then switches to data transfer which causes a delay. Here, the
processor doesn’t keep scanning for peripherals ready for data transfer. But, it is fully
involved in the data transfer process. So, it is also not an effective way of data transfer.

The above two modes of data transfer are not useful for transferring a large block of data.
But, the DMA controller completes this task at a faster rate and is also effective for
transfer of large data block.

1. Burst Mode: Here, once the DMA controller gains the charge of the system bus, then it
releases the system bus only after completion of data transfer. Till then the CPU has to
wait for the system buses.
2. Cycle Stealing Mode: In this mode, the DMA controller forces the CPU to stop its
operation and relinquish the control over the bus for a short term to DMA controller.
After the transfer of every byte, the DMA controller releases the bus and then again
requests for the system bus. In this way, the DMA controller steals the clock cycle for
transferring every byte.
3. Transparent Mode: Here, the DMA controller takes the charge of system bus only if
the processor does not require the system bus.

Direct Memory Access Controller & it’s Working

DMA controller is a hardware unit that allows I/O devices to access memory directly
without the participation of the processor. Here, we will discuss the working of the DMA
controller.

Below we have the diagram of DMA controller that explains its working:
1. Whenever an I/O device wants to transfer the data to or from memory, it sends the DMA
request (DRQ) to the DMA controller. DMA controller accepts this DRQ and asks the CPU
to hold for a few clock cycles by sending it the Hold request (HLD).
2. CPU receives the Hold request (HLD) from DMA controller and relinquishes the bus and
sends the Hold acknowledgement (HLDA) to DMA controller.
3. After receiving the Hold acknowledgement (HLDA), DMA controller acknowledges I/O
device (DACK) that the data transfer can be performed and DMA controller takes the
charge of the system bus and transfers the data to or from memory.
4. When the data transfer is accomplished, the DMA raise an interrupt to let know the
processor that the task of data transfer is finished and the processor can take control over
the bus again and start processing where it has left.

Now the DMA controller can be a separate unit that is shared by various I/O devices, or
it can also be a part of the I/O device interface.
 Direct Memory Access Diagram

After exploring the working of DMA controller, let us discuss the block diagram of the
DMA controller. Below we have a block diagram of DMA controller.

Whenever a processor is requested to read or write a block of data, i.e. transfer a block
of data, it instructs the DMA controller by sending the following information.

1. The first information is whether the data has to be read from memory or the data has to
be written to the memory. It passes this information via read or write control lines that is
between the processor and DMA controllers control logic unit.
2. The processor also provides the starting address of/ for the data block in the memory,
from where the data block in memory has to be read or where the data block has to be
 written in memory. DMA controller stores this in its address register. It is also called
the starting address register.
3. The processor also sends the word count, i.e. how many words are to be read or written.
It stores this information in the data count or the word count register.
4. The most important is the address of I/O device that wants to read or write data. This
information is stored in the data register.

Direct Memory Access Advantages and Disadvantages

Advantages:

1. Transferring the data without the involvement of the processor will speed up the read-
write task.
2. DMA reduces the clock cycle requires to read or write a block of data.
3. Implementing DMA also reduces the overhead of the processor.

Disadvantages

1. As it is a hardware unit, it would cost to implement a DMA controller in the system.

2. Cache coherence problem can occur while using DMA controller.
Asynchronous Data Transfer in Computer Organization
The internal operations in an individual unit of a digital system are synchronized using clock pulse.
It means clock pulse is given to all registers within a unit. And all data transfer among internal
registers occurs simultaneously during the occurrence of the clock pulse. Now, suppose any two
units of a digital system are designed independently, such as CPU and I/O interface.

If the registers in the I/O interface share a common clock with CPU registers, then transfer
between the two units is said to be synchronous. But in most cases, the internal timing in each
unit is independent of each other, so each uses its private clock for its internal registers. In this
case, the two units are said to be asynchronous to each other, and if data transfer occurs between
them, this data transfer is called Asynchronous Data Transfer.

But, the Asynchronous Data Transfer between two independent units requires that control
signals be transmitted between the communicating units so that the time can be indicated at
which they send data. These two methods can achieve this asynchronous way of data transfer:

o Strobe control: A strobe pulse is supplied by one unit to indicate to the other unit when
the transfer has to occur.
o Handshaking: This method is commonly used to accompany each data item being
transferred with a control signal that indicates data in the bus. The unit receiving the data
item responds with another signal to acknowledge receipt of the data.

The strobe pulse and handshaking method of asynchronous data transfer is not restricted to I/O
transfer. They are used extensively on numerous occasions requiring the transfer of data between
two independent units. So, here we consider the transmitting unit as a source and receiving unit
as a destination.

For example, the CPU is the source during output or write transfer and the destination unit during
input or read transfer.

Therefore, the control sequence during an asynchronous transfer depends on whether the
transfer is initiated by the source or by the destination.

So, while discussing each data transfer method asynchronously, you can see the control sequence
in both terms when it is initiated by source or by destination. In this way, each data transfer
method can be further divided into parts, source initiated and destination initiated.
Asynchronous Data Transfer Methods

The asynchronous data transfer between two independent units requires that control signals be
transmitted between the communicating units to indicate when they send the data. Thus, the
two methods can achieve the asynchronous way of data transfer.

1. Strobe Control Method

The Strobe Control method of asynchronous data transfer employs a single control line to time
each transfer. This control line is also known as a strobe, and it may be achieved either by source
or destination, depending on which initiate the transfer.

a. Source initiated strobe: In the below block diagram, you can see that strobe is initiated by
source, and as shown in the timing diagram, the source unit first places the data on the data bus.

After a brief delay to ensure that the data resolve to a stable value, the source activates a strobe
pulse. The information on the data bus and strobe control signal remains in the active state for a
sufficient time to allow the destination unit to receive the data.
The destination unit uses a falling edge of strobe control to transfer the contents of a data bus to
one of its internal registers. The source removes the data from the data bus after it disables its
strobe pulse. Thus, new valid data will be available only after the strobe is enabled again.
In this case, the strobe may be a memory-write control signal from the CPU to a memory unit.
The CPU places the word on the data bus and informs the memory unit, which is the destination.
 b. Destination initiated strobe: In the below block diagram, you see that the strobe initiated
by destination, and in the timing diagram, the destination unit first activates the strobe
pulse, informing the source to provide the data.

The source unit responds by placing the requested binary information on the data bus. The
data must be valid and remain on the bus long enough for the destination unit to accept it.
The falling edge of the strobe pulse can use again to trigger a destination register. The
destination unit then disables the strobe. Finally, and source removes the data from the
data bus after a determined time interval.
In this case, the strobe may be a memory read control from the CPU to a memory unit. The
CPU initiates the read operation to inform the memory, which is a source unit, to place the
selected word into the data bus.

2. Handshaking Method

The strobe method has the disadvantage that the source unit that initiates the transfer has no
way of knowing whether the destination has received the data that was placed in the bus.
Similarly, a destination unit that initiates the transfer has no way of knowing whether the source
unit has placed data on the bus.

So this problem is solved by the handshaking method. The handshaking method introduces a
second control signal line that replays the unit that initiates the transfer.
In this method, one control line is in the same direction as the data flow in the bus from the
source to the destination. The source unit uses it to inform the destination unit whether there
are valid data in the bus.

The other control line is in the other direction from the destination to the source. This is because
the destination unit uses it to inform the source whether it can accept data. And in it also, the
sequence of control depends on the unit that initiates the transfer. So it means the sequence of
control depends on whether the transfer is initiated by source and destination.

o Source initiated handshaking: In the below block diagram, you can see that two
handshaking lines are "data valid", which is generated by the source unit, and "data
accepted", generated by the destination unit.

The timing diagram shows the timing relationship of the exchange of signals between the
two units. The source initiates a transfer by placing data on the bus and enabling its data
valid signal. The destination unit then activates the data accepted signal after it accepts the
data from the bus.
The source unit then disables its valid data signal, which invalidates the data on the bus.
After this, the destination unit disables its data accepted signal, and the system goes into
 its initial state. The source unit does not send the next data item until after the destination
unit shows readiness to accept new data by disabling the data accepted signal.
This sequence of events described in its sequence diagram, which shows the above
sequence in which the system is present at any given time.
o Destination initiated handshaking: In the below block diagram, you see that the two
handshaking lines are "data valid", generated by the source unit, and "ready for data"
generated by the destination unit.
Note that the name of signal data accepted generated by the destination unit has been
changed to ready for data to reflect its new meaning.

The destination transfer is initiated, so the source unit does not place data on the data bus
until it receives a ready data signal from the destination unit. After that, the handshaking
process is the same as that of the source initiated.
The sequence of events is shown in its sequence diagram, and the timing relationship
between signals is shown in its timing diagram. Therefore, the sequence of events in both
cases would be identical.
Advantages of Asynchronous Data Transfer

Asynchronous Data Transfer in computer organization has the following advantages, such as:

o It is more flexible, and devices can exchange information at their own pace. In addition,
individual data characters can complete themselves so that even if one packet is corrupted,
its predecessors and successors will not be affected.
o It does not require complex processes by the receiving device. Furthermore, it means that
inconsistency in data transfer does not result in a big crisis since the device can keep up
with the data stream. It also makes asynchronous transfers suitable for applications where
character data is generated irregularly.

Disadvantages of Asynchronous Data Transfer

There are also some disadvantages of using asynchronous data for transfer in computer
organization, such as:

o The success of these transmissions depends on the start bits and their recognition.
Unfortunately, this can be easily susceptible to line interference, causing these bits to be
corrupted or distorted.
o A large portion of the transmitted data is used to control and identify header bits and thus
carries no helpful information related to the transmitted data. This invariably means that
more data packets need to be sent.