Electronic Circuits and Logic Design Laboratory List of Experiments Part A Sl.No 1 Experiment Name a.

To study the working of positive clipper, double ended clipper and positive clamper using diodes. OR b. To build and simulate the above circuits using a simulation package a. To determine the frequency response, input impedance, output impedance, and bandwidth of a CE amplifier. OR b. To build the CE amplifier circuit using a simulation package and determine the voltage gain for two different values of supply voltage and for two different values of emitter resistance. a.To determine the drain characteristics and transconductance characteristics of an enhancement-mode MOSFET. OR b. To implement a CMOS inverter using a simulation package and verify its truthtable. a. To design and implement a Schmitt trigger using Op-Amp for given UTP and LTP values. OR b. To implement a Schmitt trigger using Op-Amp using a simulation package for two sets of UTP and LTP values. a. To design and implement a rectangular waveform generator (Op-Amp relaxation oscillator) for given frequency. OR b. To implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a simulation package and observe the change in frequency when all resistor values are doubled. To design and implement an astable multivibrator circuit using 555 timer for a given frequency and duty cycle. To implement a +5V regulated power supply using full-wave rectifier and 7805 IC regulator in simulation package. Find the output ripple for different values of load current.

6 7

Part B 1 a. Given any 4-variable logic expression, simplify using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC. b. Write the Verilog /VHDL code for an 8:1 multiplexer. Simulate and verify its working. a. Realize a full adder using 3-to-8 decoder IC and 4 input NAND gates. b. Write the Verilog/VHDL code for a full adder. Simulate and verify its working. a. Realize a J-K Master/Slave Flip-Flop using NAND gates and verify its truth table. OR 1

2 3

b. Write the Verilog/VHDL code for D Flip-Flop with positive-edge triggering. Simulate and verify its working. a. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs. OR b. Write the Verilog/VHDL code for mod-8 up counter. Simulate and verify its working. a. Design and implement a ring counter using 4-bit shift register. b. Write the Verilog/VHDL code for switched tail counter. Simulate and verify its working. Design and implement an asynchronous counter using decade counter IC to count up from 0 to n (n<=9). Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy and resolution.

5 6 7

GENERAL INTRODUCTION TO PSPICE Why simulate circuits?

In order to ensure a successful circuit design and mitigate costly and potentially dangerous design flaws, careful planning and evaluation must occur at every stage of the process. Circuit simulation provides a cost-effective and efficient method for identifying faults before moving to the more expensive and time-consuming prototyping stage. Including simulation in the design process reduces design errors and speeds the design cycle by allowing you to predict and better understand circuit behavior. The main purpose of simulation is to predict and understand the behavior of electronic circuits. Experiment with What-if Scenarios.

Limitations of simulation
Simulation is never meant to replace prototyping. Certain real-world effects, like cross-talk, electromagnetic noise, and spurious line noise, can be too difficult, time-consuming, or costly to model in simulation. Note: While a prototype helps you to verify and validate your design in the real world, simulation helps you catch design errors before spending money and time on prototyping.

SPICE is program that simulates electronic circuits on your PC. WHY USE SPICE? SPICE is a great tool for learning electronics. You can increase your understanding of
circuits as you play and tinker with them. Modify the circuit and see what happens. Change a component value and see the effect on a circuit in seconds. PSPICE by OrCAD is one of the most popular circuit simulators.

Orcad 9.2 Lite Edition Installation

1. Insert Cadence CD into CD-ROM drive 2. Select Products to install Capture Schematic entry application it must be installed

Capture CIS Should be grayed out. PSpice For conducting mixed-signal analog and digital simulations Layout For creating PC Board layouts from schematics Then follow the instructions as it appears on the monitor and complete the installation

The steps to simulation:

1. Create a simulation project 2. Draw schematic to simulate 3. Establish a simulation profile 4. Set up simulation type 5. Simulate circuit 6. Analyze results in Probe To start a simulation session 1. On the start menu select ORCAD FAMILY RELEASE 9.2 LITE EDITION - CAPTURE LITE EDITION 2. Once the capture window appears, select FILE - NEW - PROJECT The following window appears:

3. Give the project a descriptive name (spaces can be included). 4. Select ANALOG OR MIXED-SIGNAL CIRCUIT WIZARD. 5. Specify a location where the project is to be stored a. Click Browse to change the location the files will be stored 6. Click OK.

The following window appears:

7. Select Create a blank project and click OK. The following window appears:

8. To place parts, click PLACE PART (Shift+P) The following window appears: 4

If Libraries are not appearing in the window then click Add Library. The library files will generally be available in the following path by default C:\Program Files\Orcad_Demo\Capture\Library\Pspice.Select all Library files by pressing Ctrl A and then press Open. All the Library files will appear in the window.

9. Select the part you wish to place in the schematic. Insert as many as

needed 10. Right Click and select END MODE to stop inserting parts

11. To wire parts together, click Place Wire Icon from the Right hand side vertical Icons list (Shift+W). Place cursor over boxes at ends of parts and draw wires connecting parts.When done, right click and select End Wire. 12. To insert a ground node, click Place Ground IconWindow appears with caption Place Ground with only ground nodes available for selection.

Altenative method:Click on place Net alias Icon N1 on the Right hand side vertical Icons list.

Always select 0/SOURCE for the ground node of an analog circuit every analog circuit must contain atleast one 0 ground. This is not a requirement for digital circuits. 13. To change component values that are displayedDouble click the displayed value Change the desired value in the dialog box that appears.

To set up a simulation profile Select PSPICE ---NEW SIMULATION PROFILE from the menu 7

Give a descriptive name to the type of simulation . Select the desired parameters for the particular circuit and then click OK Place voltage, current, and power markers from the PSPICE --- MARKERS menu where needed

Click PSPICE -- RUN.

Simulation Experiments
General procedure for all experiments: 1. 2. 3. 4. Select the required components from the menu. Place all the required components in the schematic. Simulate the circuit using RUN option from the menu. Observe the waveforms form the output

1 a. To study the working of positive clipper, double ended clipper and positive clamper using diodes. COMPONENTS REQUIRED: Diode (BY-127 / IN4007), Resistors-10 K regulated power supply (for Vref), Signal generator (for Vi) and CRO. CIRCUIT DIAGRAM OF POSITIVE CLIPPER & 3.3k , DC

Fig.1 a Positive clipper Circuit

b. Transfer Characteristics

Clippers clip off a portion of the input signal without distorting the remaining part of the waveform. In the positive clipper shown above the input waveform above Vref is clipped off. If Vref = 0V, the entire positive half of the input waveform is clipped off. Plot of input Vi (along X-axis) versus output Vo (along Y-axis) called transfer characteristics of the circuit can also be used to study the working of the clippers. Choose R value such that R

R f Rr where Rf = 100 and Rr = 100k are the resistances

of the forward and reverse diode respectively. Hence R = 3.3k . Let the output resistance RL = 10k . The simulations can be done even without RL. WAVEFORMS

Fig. 2. Input and output waveform for positive Clipper

DOUBLE ENDED CLIPPER

Fig.3 Double ended clipper Circuit

b. Transfer Characteristics

Fig.4. Input and output waveform for double-ended clipping circuit Note: The above clipper circuits are realized using the diodes in parallel with the load (at the output), hence they are called shunt clippers. The positive (and negative) clippers can also be realized in the series configuration wherein the diode is in series with the load. These circuits are called series clippers. POSITIVE CLAMPER COMPONENTS REQUIRED: Diode (BY-127), Resistor of 200 K , Capacitor - 0.1 F, DC regulated power supply, Signal generator, CRO

Fig. 5 Positive Clamper The clamping network is one that will clamp a signal to a different DC level. The network must have a capacitor, a diode and a resistive element, but it can also employ an independent DC supply (Vref) to introduce an additional shift. The magnitude of R and C must be chosen such that time constant =RC is large enough to ensure the voltage across capacitor does not discharge significantly during the interval of the diode is non-conducting.

Aim: To simulate clipper circuit

POSITIVE CLIPPER
Components to be placed in the schematic: ac voltage source, diode IN 4002, Resistor 10k and 3.3k

10

R1 3.3k v1 VOFF = 0 VAMPL = 5v FREQ = 1khz

V V

R2 D1 D1N4002 10k

0
Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

5.0V

0V

-5.0V 0s 0.5ms 1.0ms V(V1:+) V(R2:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

POSITIVE CLIPPER WITH REFERENCE VOLTAGE

Components to be placed in the schematic: ac voltage source, diode IN 4002, Resistor 10k, Resistor 3.3k,dc voltage source

11

R1 3.3k v1 VOFF = 0 VAMPL = 5v FREQ = 1khz 2V

V V

D1 D1N4002

R2 10k

0
Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

5.0V

0V

-5.0V 0s 0.5ms 1.0ms V(V1:+) V(R2:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

NEGETIVE CLIPPER
Components to be placed in the schematic: ac voltage source, diode IN 4002, Resistor 10k, Resistor 3.3k

12

R1 3.3k v1 VOFF = 0 VAMPL = 5v FREQ = 1khz

V V

D1 D1N4002

R2 10k

0
Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

5.0V

0V

-5.0V 0s 0.5ms 1.0ms V(V1:+) V(R2:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

NEGETIVE CLIPPER WITH REFERENCE VOLTAGE

Components to be placed in the schematic: ac voltage source, diode IN 4002, Resistor 10k,Resistor 3.3k, dc voltage source

13

R1 3.3k v1 VOFF = 0 VAMPL = 5v FREQ = 1khz 2V

V V

D1 D1N4002

R2 10k

0
Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

5.0V

0V

-5.0V 0s 0.5ms 1.0ms V(V1:+) V(R2:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

DOUBLE ENDED CLIPPER

14

R1 3.3k v1 VOFF = 0 VAMPL = 5v FREQ = 1khz

V V

D1 D2 D1N4002 D1N4002

R2 10k

0
Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec
5.0V

0V

-5.0V 0s 0.5ms 1.0ms V(V1:+) V(R1:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

DOUBLE ENDED CLIPPER WITH REFERENCE VOLTAGE

R1 3.3k V3 VOFF = 0 VAMPL = 5v FREQ = 1khz
V

D1N4002 D2

D1 D1N4002 V1 2V

R2 10k V2 2V

15

5.0V

0V

-5.0V 0s 0.5ms 1.0ms V(V1:+) V(R1:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

CLAMPER
C2 .1uf V5 VOFF = 0 VAMPL = 5v FREQ = 1khz
V V

D1 D1N4002

R2 250k

0
Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

16

10V

5V

0V

-5V 0s 0.5ms 1.0ms V(V1:+) V(C1:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

CLAMPER WITH REFERENCE VOLTAGE

C2 .1uf V5 VOFF = 0 VAMPL = 5v FREQ = 1khz
V V

D1 D1N4002 V6 1v

R2 250k

0
Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 5msec step size:0.01msec

15V

10V

5V

0V

-5V 0s 0.5ms 1.0ms V(V1:+) V(C1:2) 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

17

2b. To build the CE amplifier circuit using a simulation package and determine the voltage gain for two different values of supply voltage and for two different values of emitter resistance.

Components required:- transistor(QN3904),resistor,VAC,VDC,capacitor

V2 R4 10v 0 3.6k C1 R3 600

V

R1 10k Q1

C2 .47uf R2 2.2k 0V

2.2uf Q2N3904

R6V 10k

V7 1mv 0Vdc

0
R5 1k C4 10uf

The single stage common emitter amplifier circuit shown above uses what is commonly called "Voltage Divider Biasing". This type of biasing arrangement uses two resistors as a potential divider network and is commonly used in the design of bipolar transistor amplifier circuits. This method of biasing the transistor greatly reduces the effects of varying Beta, ( ) by holding the Base bias at a constant steady voltage level allowing for best stability. The quiescent Base voltage (Vb) is determined by the potential divider network formed by the two resistors, R1, R2 and the power supply voltage Vcc as shown with the current flowing through both resistors. Then the total resistance RT will be equal to R1 + R2 giving the current as I = Vcc/RT. The voltage level generated at the junction of resistors R1 and R2 holds the Base voltage (Vb) constant 18

at a value below the supply voltage. Then the potential divider network used in the common emitter amplifier circuit divides the input signal in proportion to the resistance. This bias reference voltage can be easily calculated using the simple voltage divider formula below:

The same supply voltage, (Vcc) also determines the maximum Collector current, Ic when the transistor is switched fully "ON" (saturation), Vce = 0. The Base current Ib for the transistor is found from the Collector current, Ic and the DC current gain Beta, of the transistor.

The voltage gain of an electronic circuit as a function of frequency.

Av = Vout/Vin

Analysis Type: Ac Sweep Start Frequency: 10hz End Frequency:100meg Points/Decade: 40

When the supply voltage is 1mv Voltage gain Av= 80mv

80mV

40mV

0V 10Hz V(R6:2)

100Hz V(C2:2)

1.0KHz

10KHz

100KHz Frequency

1.0MHz

10MHz

100MHz

19

When the supply voltage is changed to 2mv Voltage gain Av= 150mv
150mV

100mV

50mV

0V 10Hz V(R6:2)

100Hz V(C2:2)

1.0KHz

10KHz

100KHz Frequency

1.0MHz

10MHz

100MHz

When the supply voltage is 1mv and the emitter resistor value is 1k Voltage gain Av= 80mv

80mV

40mV

0V 10Hz V(R6:2)

100Hz V(C2:2)

1.0KHz

10KHz

100KHz Frequency

1.0MHz

10MHz

100MHz

When the supply voltage is 1mv and the emitter resistor value is 2.2k Voltage gain Av= 40mv

40mV

20mV

0V 10Hz V(R6:2)

100Hz V(C2:2)

1.0KHz

10KHz

100KHz Frequency

1.0MHz

10MHz

100MHz

20

3.b To implement a CMOS inverter using a simulation package and verify its truthtable.

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 100usec

5.0V

step size:0.1usec

2.5V SEL>> 0V V(V1:+) 5.0V

2.5V

0V V(R1:2) 5.0V

2.5V

0V 0s V(V1:+) 10us 20us V(R1:2) 30us 40us 50us Time 60us 70us 80us 90us 100us

21

4b. To implement a Schmitt trigger using Op-Amp using a simulation package for two sets of UTP and LTP values.
COMPONENTS REQUIRED: IC A 741, Resistor of 10K, 90K, DC regulated power supply, Signal generator, CRO Theory: Open loop gain of op amp is defined as: AOL = Vo / VD where VD = Vin Vref Open loop gain of op amp is very high (ideally infinite). Any small difference between VNI and VINV results into saturation of output voltage VSAT Value of VSAT is limited by the supply voltage of op amp DESIGN: From theory of Schmitt trigger circuit using op-amp, we have the trip points,

UTP & LTP

R1Vref R1 R1 R2 R1Vref R2

R2Vsat whereVsat is the positive saturation of the opamp 90% of Vcc R1 R2 R2Vsat R1 R2

Hence given the LTP & UTP values to find the R1 , R2 & Vref values, the following design is used. UTP LTP UTP LTP Let Vsat Let R2 2 R1Vref R1 R2 - - - - - -(1)

2 R1Vsat - - - - - -(2) R1 R2 9 R2 90 K (UTP LTP)(R1 2 R1 R2 ) 3.33V

10V, UTP 4V & LTP 2V, then equation (2) yields R1 10 K , then R1

From equation (1) we have Vref

UTP=-1 V LTP=-3v Vref=-2.2v

22

V2

V3 R1 3.3v 10k U1 10v

V+

OS2

5 R2 6 1 90k
V

OUT -

V4
20ms Time

2
V

OS1

uA741

V1 VOFF = 0 VAMPL = 5v FREQ = 50hz V4

10v

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 40msec step size:0.1msec

UTP=4v LTP=2v Vref=3.3v

10V

5V

0V

-5V

-10V 0s V(V1:+) 5ms V(U1:OUT) 10ms 15ms 25ms 30ms 35ms 40ms

Hysteresis Curve
23

To get the Hysterisis curve 1. Choose Axis settings from Plot menu 2. Under X-axis select axis variable 3. Select the input wave 4. Click Apply and ok 5. From the output check the UTP and LTP values 6. When Vin >UTP The o/p changes from +vsat(10v) to vsat(-10v) 7. When vin< LTP the o/p changes from -vsat(10v) to +vsat(-10v)
10V

5V

0V

-5V

-10V -5.0V -4.0V -3.0V V(V1:+) V(U1:OUT)

-2.0V

-1.0V

0.0V V(V1:+)

1.0V

2.0V

3.0V

4.0V

5.0V

UTP=-1 V LTP=-3v Vref=-2.2v

10V

5V

0V

-5V

-10V 0s V(V1:+) 5ms V(U1:OUT) 10ms 15ms 20ms Time 25ms 30ms 35ms 40ms

Hysteresis Curve
24

10V

5V

0V

-5V

-10V -5.0V -4.0V -3.0V V(V1:+) V(U1:OUT)

-2.0V

-1.0V

0.0V V(V1:+)

1.0V

2.0V

3.0V

4.0V

5.0V

25

5.b. To implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a simulation package and observe the change in frequency when all resistor values are doubled.
RELAXATION OSCILLATOR
0
R3 10k R2 10k

0
V1 12v OS2 5 6 1
V

U1 3 +

V4

2 uA741 V

V+

OUT OS1 V2 12v C1 .1uf

0
R1

0
1k

TYPE OF ANALYSIS : TIME DOMAIN RUN TO TIME : 4ms MAXIMUM STEP SIZE : 0.01ms
20V

10V

0V

-10V

-20V 2.0ms V(R3:1)

2.5ms V(R3:2)

3.0ms

3.5ms Time

4.0ms

4.5ms

5.0ms

Time period =.3ms Frequency=3.3 KHz Resistor values Doubled

26

20V

10V

0V

-10V

-20V 2.0ms V(R3:1)

2.5ms V(R3:2)

3.0ms

3.5ms Time

4.0ms

4.5ms

5.0ms

Time period =.5ms Frequency= 2khz Conclusion:As the resistor values are increased Time period increases and so the frequency decreases

27

6. To design and implement an astable multivibrator using 555 Timer for a given frequency and duty cycle. COMPONENTS REQUIRED: 555 Timer IC, Resistors of 3.3K, 6.8K, Capacitors of 0.1 F, Regulated power supply, CRO

Capacitance This is a measure of a capacitor's ability to store charge. A large capacitance means that more charge can be stored. Capacitance is measured in farads, symbol F. Three prefixes (multipliers) are used, (micro), n (nano) and p (pico): means 10-6 n means 10-9 p means 10-12

Capacitor Number Code for Electrolytic capacitors A number code is often used on small capacitors where printing is difficult: the 1st number is the 1st digit, the 2nd number is the 2nd digit, the 3rd number is the number of zeros to give the capacitance in pF. Ignore any letters - they just indicate tolerance and voltage rating. For example: 102 means 1000pF = 1nF (not 102pF!) 101 means 100pF=.1nF Colour Coding For Resistors Resistor values are always coded in ohms ( symbol ), capacitors in picofarads (pF)

A 100 k, 5% band A is first significant figure of component value band B is the second significant figure band C is the decimal multiplier band D if present, indicates tolerance of value in percent (no color means 20%) 28

Color Black Brown Red Orange Yellow Green Blue Violet Gray White Gold Silver None

Significant Multiplier figures 0 100 1 101 2 102 3 103 4 104 5 105 6 106 7 107 8 108 9 109 10-1 10-2

Tolerance 1% 2% 0.5% 0.25% 0.1% 0.05% 5% 10% 20% F G

D C B A J K M

Temp. Coefficient (ppm/K) 250 U 100 S 50 R 15 P 25 Q 20 Z 10 Z 5 M 1 K

DESIGN: Given frequency (f) = 1KHz and duty cycle = 60% (=0.6) The time period T =1/f = 1ms = tH + tL Where tH is the time the output is high and tL is the time the output is low. For an astable multivibrator using 555 Timer we have tL = 0.693 RB C ------(1) tH = 0.693 (RA + RB)C ------(2) T = tH + tL = 0.693 (RA +2 RB) C Duty cycle = tH / T = 0.6. Hence tH = 0.6 T = 0.6ms and tL = T tH = 0.4ms. Let C=0.1F and substituting in the above equations, So RB= tL/0.693 x C =0.4 x 10-3/0.693 x .1x10-6=5.8k RA = tH - 0.693 x Cx RB / 0.693 x C =0.6 x 10-3 x0.693 x5.8 x 103 0.1x x10-6/0.693 x .1x10-6=2.9k RB = 5.8K (from equation 1) and RA = 2.9K (from equation 2 & RB values). The Vcc determines the upper and lower threshold voltages (observed from the capacitor voltage 2 1 waveform) as VUT VCC & VLT VCC . 3 3 29

Note: The duty cycle determined by RA & RB can vary only between 50 & 100%. If RA is much smaller than RB, the duty cycle approaches 50%.

Circuit Diagram Connect the pin 2 to the CRO to get the capacitor waveform check the amplitude from the waveform to get the UTP and LTP values Connect pin 3 to CRO to get the output. Find out the TH and TL values PROCEDURE: 1. Before making the connections, check the components using multimeter. 2. Make the connections as shown in figure and switch on the power supply. 3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO. 4. Observe the output waveform at 3rd pin of 555 timer on CRO (shown below). 5. Note down the amplitude levels, time period and hence calculate duty cycle. Example 2: frequency = 1kHz and duty cycle =75%, RA = 7.2k & RB =3.6k, Duty cycle = tH / T = 0.75. Hence tH = 0.75T = 0.75ms and tL = T tH = 0.25ms. Let C=0.1F and substituting in the above equations, So RB= tL/0.693 x C =0.25 x 10-3/0.693 x .1x10-6=3.6k RA = (tH - 0.693 x RB x C) /0.693 x C =0.75 x 10-3 x 0.693 x 3.6 x 103 x 0.1x 10-6 / 0.693 x .1x10-6=7.2k Choose RA = 6.8k and RB = 3.3k. RESULT: The frequency of the oscillations = _1KHz. WAVEFORMS 30

THEORY: Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output waveform is rectangular. The multivibrators are classified as: Astable or free running multivibrator: It alternates automatically between two states (low and high for a rectangular output) and remains in each state for a time dependent upon the circuit constants. It is just an oscillator as it requires no external pulse for its operation. Monostable or one shot multivibrator: It has one stable state and one quasi stable. The application of an input pulse triggers the circuit time constants. After a period of time determined by the time constant, the circuit returns to its initial stable state. The process is repeated upon the application of each trigger pulse. Bistable Multivibrators: It has both stable states. It requires the application of an external triggering pulse to change the output from one state to other. After the output has changed its state, it remains in that state until the application of next trigger pulse. Flip flop is an example. Threshold voltage theoretical practical VUT (2/3 x Vcc)=3.3V VLT (1/3 x Vcc)=1.6V

Each division in oscilloscope is 0.2 Time=no of div in x-axis x time base Amplitude= no of div in y-axis x volt/div Duty cycle= (Ton/Ton +Toff) *100 Duty cycle Theoretical Practical Duty cycle 75% Ton .6ms Toff .4ms

31

Type of analysis: TIME DOMAIN (TRANSIENT) Run to time: 100msec step size:0.01msec

32

Waveforms:Load Resistor RL=1k

10V

5V

0V

-5V 0s V(D2:2) 10ms V(R1:2) 20ms 30ms 40ms 50ms Time 60ms 70ms 80ms 90ms 100ms

RL=500
10V

5V

0V

-5V 0s V(D2:2) 10ms V(R1:2) 20ms 30ms 40ms 50ms Time 60ms 70ms 80ms 90ms 100ms

RL=100
10V

5V

0V

Conclusion: when The resistor values are decreases Load current increases and the ripple -5V 0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90ms 100ms increases V(D2:2) V(R1:2)
Time

33

1.a. Given a four variable expression, simplify using Entered Variable Map (EVM) and realize the simplified logic using 8:1 MUX.
E.g., Simplify the function using MEV technique f(a,b,c,d)=m(2,3,4,5,13,15)+dc(8,9,10,11) Components used: IC 74 LS151, patch chords, power chords, trainer kit. Theory The term multiplex means many to one. A multiplexer (MUX) has n inputs. Each line is used to shift digital data serially. There is a single output line. Pin diagram of IC 74LS151

Decimal 0}0 1 1}2 3 2}4 5 3}6 7 4}8 9 5}10 11 6}12 13 7}14 15

LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

f 0 0 1 1 1 1 0 0 X X X X 0 1 0 1

MEV map entry 0------Do 1------D1 1-----D2 0-----D3 X-----D4 X-----D5 d----D6 d----D7 ( Solution is given below)

34

DMap Entered Variable

ABC
000 0000 001 0010 1 0011 1 D1=1 010 0100 1 0101 1 D2=1 011 0110 0 0111 0 D3=0 100 1000 X 1001 X D4=X 101 1010 X 1011 X D5=X 110 1100 0 1101 1 D6=d 111 1110 0 1111 1 D7=d

0 0001 0 D0=0

Circuit Diagram 0

04 D0

Vcc 16

03 D1 02 D2 01 D3 15 D4 14 D5

GND 8

Y5

O/p

` D

13 D6

12 D7

7 STROBE
Low

9 S2

10 S1

11 S0

35

Procedure:
1. 2. 3. 4. 5. Verify all components & patch chords whether they are in good condition or not. Make connections as shown in the circuit diagram. Give supply to the trainer kit. Provide input data to circuit via switches. Verify truth table sequence & observe outputs.

36

VHDL
VHDL stands for Very High Speed Integrated Circuit Hardware Description Language. It describes the behavior of an electronic circuit or system, from which the physical circuit or system can then be implemented VHDL was originally intended to serve 2 main purposes It was used as a documentation language for describing the structure of complex digital circuits. VHDL provides features for modeling the behavior of a digital circuit.

General Features of VHDL

The language can be used as an exchange medium between chip vendors and CAD tool user and can be used as communication medium between CAD and CAE tools. It supports hierarchy. It is not a case sensitive language. It is strongly type checked language. It provides design portability and flexible design methodologies: top down, bottom up or mixed It supports both synchronous and asynchronous timing models. Nominal Propagation delays, min-max delays, setup and hold timing constraint and spike detection can be described in this language.

Usage of the Tool It is one of most popular software tool used to synthesize VHDL code. This tool Includes many steps. To make user feel comfortable with the tool the steps are given below:Select NEW PROJECT in FILE MENU. Enter following details as per your convenience Project name : sample (should be same as the entity name in your VHDL code Project location : C:\example( As per convenience use default Top level module : HDL In NEW PROJECT dropdown Dialog box, Choose your appropriate device specification. Example is given below: Device family : cyclone Device : EP1C6Q240 Package : PQFP Pincount :240 Speed grade 8 On File Drop down menu choose new Vhdl file Type the Vhdl code Under the Processing Drop down menu choose Start compilation If there are errors go back to the VHDL code and correct it. Once the compilation is successfull

37

Under the processing drop down box select simulator tool select the simulator mode to functional and click on generate functional simulation netlist. we Get the success message. Under simulator tool click on open. In the empty location right click . Click on insert on NODE or BUS. Then click on NODE finder. In the window opened select pins to unassigned. Click on List . IT will list all the Net list seloct all and click ok. The input and output appears give appropriate input. On the simulator tool click on start simulation. Simulation success message will be prompted on simulator tool click on report to see the output. Create a new project for every new VHDL code

The primary data type std_ulogic (standard unresolved logic) consists of nine character literals in the following order: 'U' - uninitialized 'X' - strong drive, unknown logic value '0' - strong drive, logic zero '1' - strong drive, logic one 'Z' - high impedance 'W' - weak drive, unknown logic value 'L' - weak drive, logic zero 'H' - weak drive, logic one '-' - don't care

38

1.b. Write the verilog /VHDL code for 8:1 MULTIPLEXER. Simulate and verify its working.

I 8

MULTIPLEXER

8 TO 1

Zout

3
TruthTable INPUTS SEL (2) 0 0 0 0 1 1 0 1 SEL (1) 0 0 1 1 0 0 1 1

SEL
SEL (0) 0 1 0 1 0 1 1 1

OUTPUTS Zout I(0) I(1) I(2) I(3) I(4) I(5) I(6) I(7)

VHDL code for 8 to 1 mux (Behavioral modeling). library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux1 is Port ( I : in std_logic_vector(7 downto 0); sel : in std_logic_vector(2 downto 0); zout : out std_logic); end mux1; architecture Behavioral of mux1 is begin zout<= I(0) when sel="000" else I(1) when sel="001" else I(2) when sel="010" else I(3) when sel="011" else I(4) when sel="100" else I(5) when sel="101" else I(6) when sel="110" else I(7);

end Behavioral;

39

40

2.a. Realize a full adder using 3-8 decoder IC and 4 input NAND.
Components used: IC 74 LS138, IC 74LS20, patch chords, power chords, trainer kit. Pin diagram of ICs used:

41

Theory: The simplest Binary adder is a half adder. It has 2 inputs and 2 output bits. One is the sum and the other is carry. A half adder has no provision to add carry of lower order bits when binary numbers are added. When two input bits and a carry are to be added, the number of input bits become 3 and input combination increases to 8. For this a full adder is used. Like half adder, it has 2 outputs. One is sum and the other is carry. New carry generated is denoted as Cn and carry generated from addition of previous lower order bits is denoted as C n-1

Function table A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1

Circu it Diag ram

42

Procedure:
1.Verify all components & patch chords whether they are in good condition or 2. Make connections as shown in the circuit diagram. 3. Give supply to the trainer kit. 4. Provide input data to circuit via switches. 5. Verify truth table sequence & observe outputs. not.

43

2.b. Write the verilog/ VHDL code for FULL ADDER. Simulate and verify its working.

X Y Z

FULL ADDER

S Cout

Truth Table INPUTS X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 OUTPUTS CARRY 0 0 0 1 0 1 1 1

Expression: Sum(S)=X Carry(Cout) = XY +YZ + ZX

44

VHDL code for Full adder using data flow

library IEEE; use IEEE.STD_LOGIC_1164.ALL use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fa IS Port (X, Y, Z : in STD_LOGIC; Cout, S : out STD_LOGIC); End fa; ARCHITECTURE df OF fa IS Begin Cout<= (X AND Y) OR( Y AND Z) OR (X AND Z); S<= (X XOR Y) XOR Z; End df;

45 SUM CARRY

3.a.Realize a J-K Master/Slave FF using NAND gates and verify its truth table.
Components used: IC 74 LS00, IC 74LS10, patch chords, trainer kit. Pin diagram of ICs used: 7400

7410

Clk

J 0 0 1 1

K 0 1 0 1

Q Q0 0 1 Q0

--Q ---Q0 1 0 Q0

comment No change Reset Set toggle

46

Theory: The circuit below shows the solution. To the RS flip-flop we have added two new connections from the Q and Q' outputs back to the original input gates. Remember that a NAND gate may have any number of inputs, so this causes no trouble. To show that we have done this, we change the designations of the logic inputs and of the flip-flop itself. The inputs are now designated J (instead of S) and K (instead of R). The entire circuit is known as a JK flip-flop.

In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q' outputs will only change state on the falling edge of the CLK signal, and the J and K inputs will control the future output state pretty much as before. However, there are some important differences. Since one of the two logic inputs is always disabled according to the output state of the overall flip-flop, the master latch cannot change state back and forth while the CLK input is at logic 1. Instead, the enabled input can change the state

of the master latch once, after which this latch will not change again. This was not true of the RS flip-flop. If both the J and K inputs are held at logic 1 and the CLK signal continues to change, the Q and Q' outputs will simply change state with each falling edge of the CLK signal. (The master latch circuit will change state with each rising edge of CLK.) We can use this characteristic to advantage in a number of ways. A flip-flop built specifically to operate this way is typically designated as a T (for Toggle) flip-flop. The lone T input is in fact the CLK input for other types of flip-flops. The JK flip-flop must be edge triggered in this manner. Any level-triggered JK latch circuit will oscillate rapidly if all three inputs are held at logic 1. This is not very useful. For the same reason, the T flip-flop must also be edge triggered. For both types, this is

47

the only way to ensure that the flip-flop will change state only once on any given clock pulse. Because the behavior of the JK flip-flop is completely predictable under all conditions, this is the preferred type of flip-flop for most logic circuit designs. The RS flip-flop is only used in applications where it can be guaranteed that both R and S cannot be logic 1 at the same time. At the same time, there are some additional useful configurations of both latches and flip-flops. In the next pages, we will look first at the major configurations and note their properties. Then we will see how multiple flip-flops or latches can be combined to perform useful functions and operations. Master Slave Flip Flop: The control inputs to a clocked flip flop will be making a transition at approximately the same times as triggering edge of the clock input occurs. This can lead to unpredictable triggering. A JK master flip flop is positive edge triggered, where as slave is negative edge triggered. Therefore master first responds to J and K inputs and then slave. If J=0 and K=1, master resets on arrival of positive clock edge. High output of the master drives the K input of the slave. For the trailing edge of the clock pulse the slave is forced to reset. If both the inputs are high, it changes the state or toggles on the arrival of thepositive clock edge and the slave toggles on the negative clock edge. The slave does exactly what the master does.

Procedure:
1Verify all components & patch chords whether they are in good condition or not. 1. Make connections as shown in the circuit diagram. 2. Give supply to the trainer kit. 3. Provide input data to circuit via switches. 5. Verify truth table sequence & observe outputs.

Write the verilog/ VHDL code for D Flip-Flop with positive- edge triggering. Simulate and verify its working.
3.b.

Truth table

clk -

D(input) 0

Q(output)

QBar No change

48

1 0 1

0 1

No change 1 0

VHDL code for D Flip Flop Counter.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dff is Port ( D,Clk : in std_logic; Q : out std_logic; Qbar : out std_logic:='1'); end dff; architecture Behavioral of dff is begin process(clk) begin if rising_edge(clk) then Q<= D; Qbar<= not D; end if; end process; end Behavioral;
D-ff Simulation Results

49

4.a. Design and implement a mod n (a<8)synchronous up counter using JK FF.

Components used: IC 74 LS76, IC 74LS08, patch chords, trainer kit.

PIN DIAGRAM OF JK FLIP FLOP 74LS76 ICS ( TWO JK FLIP FLOP IN ONE ICS))

FOR

INITIALIZATION EITHER FOR 1S OR FOR 0S

PR1,PR2-Preset Used To Store 1 By Making PR=LOW AND CLR=HIGH CLR1,CLR2-Clear Used To Store 0 By Making CLR= LOW AND PR=HIGH FOR NORMAL OPERATION THAT IS ,DEPENDS ON INPUT:PR1 ,PR2,CLR1,CLR2=HIGH

for initialization

for normal

50

PIN DIAGRAM OF 74LS08 ICS( 2 INPUT AND GATE( FOUR AND IN ONE ICS))

FUNCTIONAL TRUTH TABLE FOR J-K FLIP FLOP

J 0 0 1 1 K 0 1 0 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 0 1 1 1 0

STATE SYNTHESIS TABLE FOR JK FLIP FLOP

Present state 0 0 1 1 Next state 0 1 0 1 J 0 1 X X K X X 1 0

51

Theory: The ripple counter requires a finite amount of time for each flip flop to change state. This problem can be solved by using a synchronous parallel counter where every flip flop is triggered in synchronism with the clock, and all the output which are scheduled to change do so simultaneously. The counter progresses counting upwards in a natural binary sequence from count 000 to count 100 advancing count with every negative clock transition and get back to 000 after this cycle.

Synchronous counter design

To successfully design synchronous counters we may employ the following six basic steps:

1. Create the state transition diagram. 2. Create a present state-next state table (often referred to as the next state table). 3. Expand the table to form the transition table for each flip-flop in the circuit. The transition table shows the flip-flop inputs required to make the counter go from present state to the desired next state. This is also referred to as the excitation table. 4. Determine the logic functions of the J and K inputs as a function of the present states. 5. Analyse the counter to verify the design. 6. Construct and test the counter. Let us employ these techniques to design a MOD-8 counter to count in the following sequence: 0, 1, 2, 3, 4, 5, 6, 7. Step1: Creating state transition diagram.

52

Step 2: Creating present state-next state table Present State Qc 0 0 0 0 1 1 1 1 Qb 0 0 1 1 0 0 1 1 Qa 0 1 0 1 0 1 0 1 Qc 0 0 0 1 1 1 1 0 Next State Qb 0 1 1 0 0 1 1 0 Qa 1 0 1 0 1 0 1 0

Step 3: Expand the present state-next state table to form the transition table. Present State Qc 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 QA 0 1 0 1 0 1 0 1 Next State QC 0 0 0 1 1 1 1 0 QB 0 1 1 0 0 1 1 0 QA 1 0 1 0 1 0 1 0 JC 0 0 0 1 X X X X Kc X X X X 0 0 0 1 Present inputs JB 0 1 X X 0 1 X X KB X X 0 1 X x 0 1 JA 1 X 1 X 1 X 1 X KA X 1 X 1 X 1 X 1

X indicates a "dont care" condition.

53

Step 4: Use Karnaugh maps to identify the present state logic functions for each of the inputs. BA

C c 0 1
X

00 X

01 1 X

11 X

10

Jc=QaQb BA

C 0 1
X

00 X

01 X 1

11 X

10

Kc=QaQb BA

C 0 1
0 0

00 1 1

01 X X

11 X X

10

JB=Qa AB

C 0 1
X X

00 X X

01 1 1

11 0 0

10

Kb=Qa AB

C 0 1
1 1

00 X X

01 X X

11 1 1

10

Ja=1

54

BA

C 0 1
X X

00 1 1

01 1 1

11 X X

10

Ka=1 Step 5: Trace through indicates circuit should work correctly. Step 6: Constructing Circuit

A three-bit synchronous counter *NOTE:-CONNECT PRESET AND CLEAR TO HIGH TO WORK ON NORMAL OPERATION

4.b. Write the verilog/ VHDL code for mod-8 up counter. Simulate and verify its working.

Truth table

rst 1 0 0 0 0

clock x

Q2 0 0 0 0 1
55

Q1 0 0 1 1 0

Q0 0 1 0 1 0

0 0 0 0

1 1 1 0

0 1 1 0

1 0 1 0

VHDL code for Mod-8 Counter. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mod8 is Port ( rst,clk: in std_logic; q : buffer std_logic_vector(2 downto 0):="000"); end mod8; architecture Behavioral of mod8 is begin process(clk,rst) is begin IF (CLK'event and clk='0') then If(rst='1') then q<="000"; Else q <= q+1; End if; End if; End process; End Behavioral;

56

Mod 8 Counter Simulation Results

Output

57

5.a. Design and Implement a Ring Counter using 4 bit Shift Register. Components used: IC 74 LS95, patch chords, trainer kit. Pin diagram of ICs used: Pin Diagram of IC: 7495

Mode Control Input : If Mc= 1 Parallel input Mc=0 Serial input

Theory: Ring Counter is a basic register with direct feedback such that contents of the register simply circulate around the register when the clock is running. Here last output Qd in a shift register is connected back to the serial input. Function Table: Clk 0 1 2 3 Qa 1 0 0 0 Qb 0 1 0 0 Qc 0 0 1 0 Qd 0 0 0 1

58

Circuit Diagram: Qd Vcc Qa Qb Qc

CLK(Mono pulse)

14

13

12

11

10

IC 7495
1 2 3 4 5 6 7

MC

gnd

1. Make Mc=1 Give parallel input 1000 through ABCD 2. Then make Mc=0 for shift operation

Procedure:
1 Verify all components & patch chords whether they are in good condition or not. 2 Make connections as shown in the circuit diagram. 3 Give supply to the trainer kit. 2 Provide input data to circuit via switches . 4. Verify truth table sequence & observe outputs.

59

5.b. Write the verilog/ VHDL code for switched tail counter. Simulate and verify its working.

Truth table clk 0 1 1 1 1 1 1 1 1 1 1 1 1 Q3 0 0 0 0 1 1 1 1 0 0 0 0 1 Q2 0 0 0 1 1 1 1 0 0 0 0 1 1 Q1 0 0 1 1 1 1 0 0 0 0 1 1 1 Q0 0 1 1 1 1 0 0 0 0 1 1 1 1

60

VHDL code for Johnson counter. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jc is Port ( clk : in std_logic; Q : buffer std_logic_vector(3 downto 0)); end jc; architecture Behavioral of jc is begin process(clk) begin IF (CLK'event and clk='1') then Q(3 downto 1)<=Q(2 downto 0); Q(0)<=not Q(3); end if; end process; end behavioral;

Johnson Counter Simulation Results

61

OUTPUT

62

6) Design and implement asynchronous counter using decade counter IC to count up from 0 to n (n9). Components used: IC 74 LS90, patch chords, trainer kit. Pin Diagram of 7490 Theory: Asynchronous counter is a counter in which the clock signal is connected to the clock input of only first stage flip flop. The clock input of the second stage flip flop is triggered by the output of the first stage flip flop and so on. This introduces an inherent propagation delay time through a flip flop. A transition of input clock pulse and a transition of the output of a flip flop can never occur exactly at the same time. Therefore, the two flip flops are never simultaneously triggered, which results in asynchronous counter operation.

1.Cp0(pin 14) to be connected to clock 2.Cp1(pin1) to be connected to Q0.( The output of the first flip flop drives the second clock)

63

For decade counter(mod 10)

MR1 AND MR2-CLEAR ALL FILPFLOP (HIGH ACTIVE AND LOW FOR NOT ACTIVE) MS1 AND MS2- SET ALL FLIP FLOP (HIGH ACTIVE AND LOW FOR NOT ACTIVE) CPO-CLOCK PULSE TO FIRST FLIP FLOP CP1-CLOCK PULSE TO SECOND FLIP FLOP (OUTPUT OF FIRST FLIP FLOP CLOCK FOR SECOND FILP FLOP)

For mod 9 connect Q0 and Q3 to reset(clear) through an AND gate. Note :reset should not be connected to the switch For mod8 Connect Q3 to reset For mod7 Connect Q2, Q1,Q0 to reset through an And Gate For Mod 6 Connect Q2 and Q1 to reset through an AND gate

64

For mod 5 Connect Q0 and Q2 to reset through an AND gate For Mod 4 Connect Q2 to reset through an AND gate For mod 3 Connect Q1 and Q0 to reset through an AND gate For mod 2 Connect Q1 to reset Function Table: Clock 0 1 2 3 4 5 6 8 9 10 Q3 0 0 0 0 0 0 0 0 1 1 Q2 0 0 0 0 1 1 1 1 0 0 Q1 0 0 1 1 0 0 1 1 0 0 Q0 0 1 0 1 0 1 0 1 0 1

Procedure:
1 Verify all components & patch chords whether they are in good condition or not. 2. Make connections as shown in the circuit diagram. 3. Give supply to the trainer kit. 4. Provide input data to circuit via switches. 5. Verify truth table sequence & observe outputs.

65

7.Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy and resolution.

AIM: EQUIPMENTS AND COMPONENTS REQUIRED: Op-amp 741, Resistors , dual power supply, VRPS ,CRO, Bread board.

PROCEDURE: 1. The circuit is connected as per the diagram 2. Give digital inputs from 0000 (2) to 1111(2) in steps using switch arrangement and note down the corresponding analog voltage. 3. For each case verify the theoretical value with practical value. 4. To find linearity plot the practical analog output values Vs digital inputs on a graph sheet. A straight line connecting input and output values is drawn. DESIGN: Analog output voltage Vo for 4-bit DAC is given by

Vo = (8 D3 + 4 D2+2 D1+1 D0)*V Where V = Vref. (2R) /24 . (3R) = Vref/ 24 =5/24=0.20833
Example:

For Digital input D1D,D,D0 1 011 Vo=(8+0+2 1 ) 0.20833 Vo= 2.291 volts. Resolution: This is the number of possible output levels the DAC is designed to reproduce.
This is usually stated as the number of bits it uses, which is the base two logarithm of the number of levels. Resolution is related to the effective number of bits (ENOB) which is a measurement of the actual resolution attained by the DAC.

66

Example:1 bit DAC is designed to reproduce 2 (21) levels while an 8 bit DAC is designed for 256 (28) levels. (a)Resolution for 4bit DAC is designed to reproduce 16(24) levels (b)Accuracy formula= 100-(Theoretical value- Practical value) Example:100-(3.12-3.00)=100-.12=99.88% Decimal Equivalent 0 1 2 3 4 5 6 7 8 9 10 Digital Input D1 Analog Output voltage Theoretical Practical

D3

D2

D0

11 12 13 14 15

67

68