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BMI BRG-100RF X-Ray - Circuit Diagrams
BMI BRG-100RF X-Ray - Circuit Diagrams
INVERTER
SEE MD-0788
SHEET 1, 2
DC BUS FOR
DUAL SPEED
STARTER
J1
J4
TO T2 ROOM
INTERFACE E17
J3
TRANSFORMER
SEE MD-0788, E21 J6 TO T1 POWER SUPPLY
SHEET 1, 2 AUXILIARY TRANSFORMER
J5 SEE MD-0788, SHEET 1, 2
TO J5 OF HT TANK
J11
(SHEET 2)
J7 J8 J9 J10
DRAWN DATE
G. SANWALD 02 MAR 2004
INTERCONNECT
CHECKED
DIAGRAM
(INDICO 100)
DES.\MFG.\AUTH.
L. FOSKIN 02 MAR 2004 MD-0843 REV H
SHEET 1 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
FROM J1, OUTPUT CURRENT
SENSE TRANSFORMER,
ON RESONANT BOARD
(SHEET 3)
J1
J2 J1 J2 J1 J1 J5 J6
TB3
TO TUBE 1 / TUBE 2 STATOR
TERMINALS. SEE MD-0765, SHEET 1
J9
AND CHAPTER 2 OF SERVICE MANUAL
FILAMENT SUPPLY FILAMENT SUPPLY TB2
BOARD BOARD AUXILIARY BOARD
ASSEMBLY 731407 ASSEMBLY 731407 ASSEMBLY 732221
SCHEMATIC 731405 SCHEMATIC 731405 SCHEMATIC 732219
DUAL SPEED
STARTER BOARD
(OPTIONAL)
SOME MODELS WILL HAVE ONLY
J4 ASSEMBLY 728877
ONE FILAMENT SUPPLY BOARD
SCHEMATIC 728875
J3 J2 J7
J5 J5 J10 J4
J5
INVERTER BOARD
ASSEMBLY 731804 SCH 731802
ASSEMBLY 732813 SCH 732811
FROM J2 AUXILIARY TO J13 CONTROL
BOARD (SHEET 2) BOARD (SHEET 2)
J1
J9 J13 J10 J11 J12 J1
J14
K1
TO J2 AUXILIARY THERMAL SWITCH
J1 BOARD (SHEET 2) (R&F UNITS ONLY) T4
J15
CONTROL BOARD
ASSEMBLY 732816 J16
SCHEMATIC 732814
RESONANT ASSEMBLY
R/F:
J2 ASSEMBLY 732964 SCH 732962
J2
J3 J8 J4 J6 J7 RAD:
ASSEMBLY 732808 SCH 732806
INVERTER BOARD
ASSEMBLY 731804 SCH 731802
ASSEMBLY 732813 SCH 732811
J1
J4
J3
J5
J2
E10
E9
INVERTER BOARD
ASSEMBLY 731804 SCH 731802
ASSEMBLY 732813 SCH 732811 HT TANK
J1 E17 E18
mA/mAs PORT
J3
TO J15
GENERATOR
INTERFACE BOARD TB7 TB8 TB9 TB10
J11 J12
J10 GND 24 VDC 110 VAC 220 VAC
J9
DIGITAL INTERFACE BOARD (OPTIONAL)
J8 * ROOM INTERFACE BOARD
SEE NOTE ASSEMBLY 733184
ASSY 733752 SCH 733750 2
J6 SCHEMATIC 733182
ASSY 733947, 735921 SCH 733946 * SEE NOTE 3 J18 FOR FUTURE USE
ASSY 735406 SCH 735404
ASSY 736153 SCH 736151 J14
ASSY 736894 SCH 736892 SEE NOTE 1: J17 J7 *
TO A2EC2. SEE
J4 MD-0757 SHEET 1
ASSY 737950 SCH 737948
J15
J16
REFER TO MD-0767 J2
AND DIGITAL IMAGING J13 J3
SUPPLEMENT IN FRONT J1 J1
OF SERVICE MANUAL
J5
J2
FROM X-RAY TUBE THERMAL SWITCH. GENERATOR INTERFACE BOARD
SEE MD-0787 AND CHAPTER 2 J1 ASSEMBLY 732177
SCHEMATIC 732175
OF SERVICE MANUAL
PHASE 1 F5B
K5 D1
~ +
E23 INVERTER BOARDS DEPENDING ON GENERATOR OUTPUT POWER
R18, R19
~
REFER TO PAGE 5 FOR LOGIC LEVELS, E1 + E1 + E1 +
R20
PHASE 2 F5A DC BUS INVERTER INVERTER INVERTER
NOTES, ETC, REFERENCED BY OUT BOARD BOARD BOARD
HEXAGONAL SYMBOL: 3 PHASE AC E2 - E2 - E2 -
~
PHASE 3 F5C
MAINS INPUT E11
-
NEUTRAL
R16, R17
E15 E9 F2
GROUND + DUAL SPEED STARTER
IS OPTIONAL. LOW SPEED
-**
560 VDC
E8 E10 F1 STARTER IS STANDARD
IN INDICO 100 GENERATORS
K1
DC BUS CHARGED DC BUS DUAL SPEED STARTER BOARD
+12V
SENSING DISCHARGE
F2
JW3 CIRCUIT CIRCUIT
1 (R5-R8, D3) (Q1, D10) T1
SOFT START OK F1 F7 J6-1 380/400/480 VAC
*
R48
JUMPER NOT 2 +12V
PROTECTION
FITTED
(ALL MODELS)
CIRCUIT 1 5 1
U2
3 (U1C, Q7, ETC) 240 VAC
RN2
2 J4-10 J4-10 U1
+12VDC 4 5
4 2 DS1 OK 208 VAC
K1 D3 J4-8 J4-8 N/C
2 1
DC BUS
DS2 J6-5 120 VAC
S.S. +12V +12V OK
OK CONTINUED ON
JW2 +12V 94 VAC PAGE 3
1 LS1
R31
RN2
SOFT START J2-1 P2-1
JUMPER NOT 2 J6-6 73 VAC
DRIVER BUZZER
FITTED CIRCUIT
3 CNCTR ANNUNCIATOR
(ALL MODELS) 3 D2 CLOSED DS4 D4 K5
(U3B, Q6, ETC) +12V (R33-R35, R46, R47, 52 VAC
J4-13 J4-13 J2-2 P2-2 Q3, Q4)
J6-7 F1 RETURN
J4-2 J4-2 RN1 +12V
DS6 K1
D8 K2 J1-1 F1
SOFT START K2 120 / 240 VAC
RN1
R1, R2
RN2
FAULT SIGNAL J4-1 J4-1
TO AUXILIARY J5-3 J1-3 F2
K1 J4-4 J4-4 D5 52 / 73 / 94 VAC
BOARD, PAGE 3
1 5 J5-4 J1-4 F3
RN1 RN1 COMMON
R32
4 U3 Q2 +12V
DS7 +12V +12V
+12V J4-3 J4-3 RN1
2 4 +12V J3-3 J2-3 TP4
J4-14 J4-14 +12V J3-4 J2-4
RN1
TP1
J4-15 J4-15 J3-2 J2-2
TP1
J4-16 J4-16
J4-18 J4-18 D7
DS3
TUBE 1 / TUBE 2 SELECT 5 J3-9 J2-9
COMMAND TO MD-0787 REFER TO MD-0764
K3
J4-17 J4-17 LOW SPEED STARTER BOARD
J10-3
COOLING FAN(S) USED ON SOME
+12V MODELS. DEPENDING ON THE APPLICATION,
D37 +12V K4 F6
R72
FLUORO 6 J10-1 ONE, TWO, OR THREE FANS MAY BE USED
FAN ON RN1
J4-5 J4-5
FLUORO FAN K3
TIMER / DRIVER F8 J11-4 F2 J5-4 TUBE 1 /TUBE 2
CIRCUIT *** JW1 D6 SOLENOID
K4 J11-6 J5-6 (TWO TUBE HT
(U11, Q9, ETC) DS5 3 PHASE POWER INPUT BOARD
R&F GENERATORS (REFER TO PAGE 2 FOR 1 PHASE THREE FAN TANKS ONLY)
ONLY UNITS ONLY H.T. TANK
E21 E17 POWER INPUT BOARD)
J8-3
J5-6 J5-7 J5-3 J5-4 J1-6 J1-5 J1-3
AUXILIARY BOARD JW1 fitted on units ***
200V
200V
240V
180V
J9-4
J9-5
J9-2
J9-1
DRAWN DATE
E14 E18
THIS VOLTAGE IS APPROXIMATELY 560 VDC FOR 400 V GENERATORS, AND APPROXIMATELY G. SANWALD 10 MAR 2000 DC BUS & POWER
** 680 VDC FOR 480 V GENERATORS CHECKED________ ________ DISTRIBUTION
ROOM POWER KIT OPTION FOR FUTURE USE DES.\MFG.\AUTH.
REFER TO SEPARATE SUPPLEMENT,
IF APPLICABLE HTW 10 MAR 2000 MD-0788 REV AB
CONTINUED
ON PAGE 4 SHEET 1 OF 6
Use and disclosure is subject to the restrictions on the title page of this CPI document.
SINGLE PHASE INDICO 100 GENERATORS USE
ONE OR TWO INVERTER MODULES DEPENDING
K5 ON GENERATOR OUTPUT POWER
E33
LINE 1 F5A
230 MAINS BUS 650 VDC E1 + E1 +
1 PHASE AC LINE 2 VAC RECTIFIER CAPACITORS OUT
F5B E34 INVERTER INVERTER
MAINS INPUT BOARD BOARD
VOLTAGE DOUBLER CIRCUIT E2 - E2 -
GROUND
R11
R10
DC BUS ASSEMBLY
K1
J12-4 J12-1 NO CONNECTION
F2 240 VAC
J6-3
DC BUS CHARGED
F1 208 VAC
SENSING CIRCUIT
(R6-R8, R16-R21, D3, ETC)
1 J6-5 120 VAC
CONTINUED ON
J4-10 J4-10 PAGE 3
94 VAC
5 1
J4-8 J4-8
U1 J6-6 73 VAC
+12V 4 2 DS1
52 VAC
+12V DC BUS
OK
R36
J6-7 F1 RETURN
J2-1 P2-1 K2
DS4 D4 K5
J4-13 J4-13 J2-2 P2-2
+12V
J4-2 J4-2 R39 +12V +12V J5-3
K2 DS6
J5-4
R38
D8
LOW SPEED
R34
J4-1 J4-1 K1 +12V
AUXILIARY BOARD +12V STARTER BOARD
R12
J4-4 J4-4
D5
REFER TO PAGE 1 R33
1 5 DS7 F4 J3-3 REFER TO PAGE 1
R40
J3-4
R29
U2 Q1 DS2
R35 J3-2
J4-3 J4-3 +12VDC
2 4
J4-14 J4-14 OK
DS3
J4-15 J4-15 J3-9
J4-16 J4-16 +12V
J4-18 J4-18
J10-3 COOLING FAN(S) USED ON SOME
D7 K3 K4
J4-17 J4-17 J10-1 MODELS. DEPENDING ON THE APPLICATION,
ONE, TWO, OR THREE FANS MAY BE USED
+12V
6 R37 K3
J11-4
J11-6
H.T. TANK
J4-5 J4-5
D6 REFER TO PAGE 1
K4 DS5
J8-3
E21 E17 1 PHASE POWER OPTIONAL 230 VAC
INPUT BOARD J8-1
* T2FOR(SHOWN TAPPED
240 VAC MAINS)
F3 J7-1
J7-3 230 VAC
T1 / T2 MUST BE TAPPED IN ACCORDANCE WITH
* THE NOMINAL AC MAINS VOLTAGE. REFER TO
F4
J7-5
GROUND
OPTIONAL
180V
200V
0V
240V
0V
E14 E18
DRAWN DATE
G. SANWALD 10 MAR 2000 DC BUS & POWER
ROOM POWER KIT OPTION CHECKED________ ________ DISTRIBUTION
REFER TO SEPARATE SUPPLEMENT,
IF APPLICABLE DES.\MFG.\AUTH.
HTW 10 MAR 2000 MD-0788 REV AB
CONTINUED SHEET 2 OF 6
ON PAGE 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+35V
T1 +12V +12V
J7-1 F4 R71 +5V
26 VAC J6-4 J7-4 U34 TP16
R65
0V J7-3 C22 D31 J6-5 J7-5 +5 V
+/-35V REGULATOR
D32
26 VAC J7-6 F3 TP5
+12V +12V
R64
C21 D28
FROM J4-1 J1-1
PAGE 1, 2 TP7 J6-1 J7-1
J4-3 J1-3
J7-2
+12V TP1 TP15 J4-5 J1-5 +5V
15 VAC U5,U6
-35V -12V -12V J4-7 J1-7 U27
J7-4 F1 R70 J6-2 J7-2
+12 VDC
0V TP8 REGULATOR J4-9 J1-9 +5 V
D33 C24, D29 J6-3 J7-3 REGULATOR
J7-5
C25 D27
15 VAC J4-11 J1-11
U4 +12V
TO PAGE 1 J4-12 J1-12
TP9 TP10 R68
-12 VDC
REGULATOR J4-13 J1-13
F2
J4-15 J1-15
TO MD-0786 D30
C19 D16 +12V J4-17 J1-17
-12V
-12V J4-19 J1-19
R32
J5-6 J5-7 J5-3 J5-4 J1-6 J1-5 J1-3
AUXILIARY BOARD D1
+12V +12V +/- 12V/SS FAULT
D19 J5-5 J6-5 +/- 12V/SS FAULT TO GENERATOR DUAL SPEED STARTER BOARD
5.1V REF READY DETECTOR CIRCUIT ON
CONTROL BOARD, SEE MD-0761
J6-6 J6-7 J6-3 J6-4 J8-6 J8-5 J8-3 DUAL SPEED STARTER IS
-
18 CONTROL BOARD OPTIONAL. LOW SPEED
TO MD-0786 + STARTER IS STANDARD IN
U3C INDICO 100 GENERATORS
9 +35V +35V
8 -
JW1 J9-1 J1-1 F2
JUMPER POSITION:
+ +12V +12V
5 U3D
7 TUBE 1/TUBE 2 FLUORO RAD GENERATORS
SELECT SIGNAL -12V J9-4 J1-4
JUMPER "RAD"
TO MD-0765 RAD R&F GENERATORS -
CONTACTOR
CLOSED JUMPER "FLUORO" +
J9-3 J1-3
SIGNAL TO +12V U3A
MD-0765 R22 +12V J9-2 J1-2 F1
-12V -12V
+12V
R223
R227
J9-6 J1-6
R21
FROM AUXILIARY
BOARD, PAGE 1
AUXILIARY BOARD FILAMENT BOARD ONE FILAMENT BOARD IS
+12V 4 5 4 5 4 5
Q16 STANDARD IN INDICO 100
R228
+35V
RN2D
RN2C
R226
R225
U7 U40 U41
R2
R11
R10
J1-1 F2 +12V
CONTROL
BOARD J1-25 J1-6 J1-10 J1-29 J1-18 J1-19 J2-14 J2-6 J2-15 J2-7 J1-4
J1-3
+5V J10-25 J10-6 J10-10 J10-29 J10-18 J10-19 J3-14 J3-6 J3-15 J3-7 J1-2 F1
13 +5V
-12V
+15V
R27, R32
RN7F
J1-5
10 +5V TP2
-35V
D1 +5V +5V J1-6
CONT. 11 12
R14
RN11A
RN11I
DS9 DS10
U9
R9
Q4 FILAMENT BOARD
12 11
GRN RED P/S ON Q1
2 1
TO 2.1 V DS34 DS35 DRIVER DRIVER DS22 DS23 DS2 DS4
R13
4 5 -15V
CURRENT 4 5
SINK 2 1 GRN RED
TO 2.1 V
U16
TUBE 1/TUBE 2
SELECT SIGNAL
U16 FLUORO FLUORO
TO 2.1 V
LOW HIGH
TO 2.1 V
* THE POWER SUPPLY ON COMMAND (P/S ON) WHICH ENERGIZES
K1 / K2 ON THE POWER INPUT BOARD IS ISSUED BY THE GENERATOR
CPU BOARD AFTER THE +5 VDC RAIL IS DETECTED BY THE CPU.
14 U17 15 CURRENT 16 CURRENT 17 CURRENT
R33
TO MD-0787
SINK SINK SINK THE DC RAILS, INCLUDING THE +5 VDC RAIL, ARE ESTABLISHED
U24 WHEN THE SYSTEM ON COMMAND IS RECEIVED. REFER TO MD-0762.
DATA LATCH,
U27, U19 DATA LATCH DATA DATA
BUFFER BUFFER, &
DRIVER
& U16 & BUFFER LATCH LATCH
U27, U19 U27 U49 DRAWN DATE
DATA BUS
*
BIT 0 BIT 2 BIT 7 BIT 3
G. SANWALD
CHECKED________
10 MAR 2000
________
DC BUS & POWER
DISTRIBUTION
D0..D7 DES.\MFG.\AUTH.
HTW 10 MAR 2000 MD-0788 REV AB
GENERATOR CPU BOARD
PAGE 3 SHEET 3 OF 6
Use and disclosure is subject to the restrictions on the title page of this CPI document.
J4-12 J5-12
REFER TO SYSTEM ON, MD-0762 +5V
24 VDC RETURN J4-14 J5-14
TP11 +3.3V
TP8 CONSOLE BOARD & LCD DISPLAY
K3 TP7 +1.2V
24 VDC J4-13 J5-13
+ 5V, + 3.3V, +1.2V TP12 ASSEMBLY SHOWN WITHIN DASHED
AND - 15V LINES USED ON 31 X 42 CM CONSOLE
J4-15 J5-15 F1 POWER SUPPLY TP2
ONLY. REFER TO PAGE 5 FOR
+24V +15V CIRCUITS
(U9, U10, U11, 23 X 56 CM CONSOLE AND FOR
TP13 U5 TP1 D1-D6, L1, ETC.) RAD-ONLY CONSOLE.
TP13 R1
+15 V TP10
T2 J1-2 D3 REGULATOR
18 VAC F5 TP9 19
R81
+5V +5V -15V
C10 TP3 TP2
J1-1 J16-3
0V R3 +12V
+5 / +16VDC TO RAD-ONLY 300 VAC J10-1
R2
POWER SUPPLY CONSOLE BACKLIGHT FLUORESCENT LAMP
F6 U3 J16-8
CIRCUIT (PAGE 5) POWER SUPPLY
J1-3 F3 (U47, Q4, T1, (Q2, Q3, T1,
+12 V J10-4
18 VAC C16 D17, D18, ETC.) REGULATOR C61, ETC)
FROM K2 D1
J1-4 LCD DISPLAY ASSEMBLY
PAGE 1, 2 0V TP7
U2
J1-5 F4 R6
-12 V
18 VAC REGULATOR
CONSOLE BOARD (31 X 42 CM CONSOLE)
J1-7 F2
110 VAC U4 -12V TP5
R5
R4 220 VAC 220 VAC
J1-9 F1 -15 V
220 VAC -24V REGULATOR 110 VAC J2-1 J1-1 110 VAC
TP6 J2-3 J1-3 +24VDC
+24V
-15V
J2-6 J1-6
110 VAC U40 R7
R78 J2-7 J1-7
K1 ZERO CROSS LINE SYNC DS1
220 VAC DETECTOR TO MD-0767 J2-8 J1-8
D15 POWER ON
J2-9 J1-9
+12V +12V
K1
+24V +24V
J10-13
J10-19
J10-11
K2 REFER TO SYSTEM ON, MD-0762 REFER TO MD-0757 (AEC) FOR
J10-16 PINOUTS OF THE DC RAIL CONNECTIONS
J10-17 ON THE AEC BOARD
-12V -12V
-24V -24V
K3
+24V
AEC BOARD
J17-3
TO COIL OF POWER DISTRIBUTION
RELAY (CUSTOMER SUPPLIED) +5V +15V +24V +15V +15V
J17-4 TP17 +15V +12V +5V
MAXIMUM 100 MA +12V
+12V J3-3 J13-3 R77 +12V
TP19
R78
R86
R76
-15V +5V J3-6 J13-6 R85 +5V J11-1
TP16
J3-1 J13-1 R75 TO REMOTE FLUORO
J13-9 J13-21 J13-23 J13-11 J13-13 J13-17 J13-15 DS36 DS38 DS33 CONTROL, PAGE 5
J11-5
GENERATOR INTERFACE BOARD J3-8 J13-8
R81
R90
PINOUTS OF THE DC RAIL CONNECTIONS +5V +15V +24V -15V
SHOWN TO THE RIGHT OF THIS TEXT J3-2 J13-2
J3-4 J13-4
+5V +5V
J1-17 J2-17
+12V +12V
J1-18 J2-18
J1-15 J2-15
J1-19 J2-19
J1-20 J2-20
J10-5
DRAWN DATE
G. SANWALD 10 MAR 2000 DC BUS & POWER
CONSOLE BOARD (RAD-ONLY CONSOLE) LCD DISPLAY ASSEMBLY CHECKED________ ________ DISTRIBUTION
DES.\MFG.\AUTH.
HTW 10 MAR 2000 MD-0788 REV AB
SHEET 5 OF 6
Use and disclosure is subject to the restrictions on the title page of this CPI document.
NOTE
REMARKS
REFERENCE
1 THIS VOLTAGE WILL BE APPROXIMATELY 0 VDC WHEN THE DC BUS CAPACITORS ARE NOT CHARGED. THIS WILL RISE TO APPROXIMATELY 6 VDC WHEN THE DC BUS CAPACITORS ARE FULLY CHARGED.
THE DC BUS CAPACITORS MUST CHARGE WITHIN APPROXIMATELY 0.25 SECONDS OF THE GENERATOR BEING SWITCHED ON. IF THE DC BUS CAPACITORS DO NOT CHARGE NORMALLY, THE SOFT START
2 OK PROTECTION CIRCUIT ENERGIZES RELAY K1 (SEE # 4) AND INHIBITS OPERATION OF THE SOFT START DRIVER CIRCUIT (SEE # 3).
“LOW” (APPROXIMATELY 0 VDC) COMMANDS THE MAIN CONTACTOR K5 ON THE POWER INPUT BOARD TO CLOSE. “HIGH” (APPROXIMATELY 12 VDC) = CONTACTOR OPEN. THIS OUPUT WILL NOT SWITCH
3
“LOW” IF THE DC BUS CAPACITORS ARE NOT CHARGED (SEE # 1 & 2).
K1 REMAINS DE-ENERGIZED (CONTACTS AS SHOWN) IF NO SOFT-START FAULT IS DETECTED. THEREFORE, K1 AND K2 ON THE POWER INPUT BOARD WILL ENERGIZE WHEN THE GENERATOR IS SWITCHED
4
ON. A SOFT-START FAULT ENERGIZES K1 ON THE AUXILIARY BOARD, DE-ENERGIZING K1 ON THE POWER INPUT BOARD. THIS WILL INHIBIT FURTHER DC BUS CHARGING.
5 “LOW” (APPROXIMATELY 0 VDC) = TUBE 2 SELECTED, “HIGH” (APPROXIMATELY 12 VDC) = TUBE 1 SELECTED.
“LOW” (APPROXIMATELY 0 VDC) = FLUORO FAN(S) ON, “HIGH” (APPROXIMATELY 12 VDC) = FLUORO FAN(S) OFF. FAN(S) ARE SWITCHED ON DURING PULSED OR CONTINUOUS FLUORO OPERATION, AND
6
REMAIN ON FOR APPROXIMATELY 20 MINUTES AFTER SWITCHING TO RAD MODE.
7 “LOW” INDICATES CONTACTOR CLOSED (SEE # 3). THE CONTACTOR CLOSED SIGNAL OCCURS APPROXIMATELY 10 SECONDS AFTER INITIAL GENERATOR TURN-ON, ASSUMING NORMAL DC BUS CHARGING.
8 “HIGH” (APPROXIMATELY 12 VDC) = RAD / PULSED FLUORO MODE. “LOW” (APPROXIMATELY 0 VDC) = CONTINUOUS FLUORO MODE. USED ON R&F GENERATORS ONLY.
9 “HIGH” (APPROXIMATELY 12 VDC) = PULSED FLUORO / LOW POWER MODE. “LOW” (APPROXIMATELY 0 VDC) = HIGH POWER RAD MODE. NOT USED ON ALL MODELS, REFER TO MD-0786 FOR DETAILS.
10 24 VDC (APPROXIMATELY) ENERGIZES K1 AND / OR K2 ON THE POWER INPUT BOARD, INITIATING THE POWER-ON SEQUENCE. SEE # 4.
11 “HIGH” (APPROXIMATELY 5 VDC) = TUBE 2 SELECTED. “LOW” (APPROXIMATELY 0 VDC) = TUBE 1 SELECTED.
12 “HIGH” (APPROXIMATELY 5 VDC) = RAD / PULSED FLUORO MODE. “LOW” (APPROXIMATELY 0 VDC) = CONTINUOUS FLUORO MODE. USED ON R&F GENERATORS ONLY.
13 “HIGH” (APPROXIMATELY 5 VDC) = PULSED FLUORO / LOW POWER MODE. “LOW” (APPROXIMATELY 0 VDC) = HIGH POWER RAD MODE. NOT USED ON ALL MODELS, REFER TO MD-0786 FOR DETAILS.
14 DS9 LIT = CONTACTOR CLOSED, DS10 LIT = CONTACTOR NOT CLOSED.
15 DS34 LIT = GENERATOR ON COMMAND ISSUED (CONSOLE PASSED ALL SELF TESTS). DS35 LIT = GENERATOR ON COMMAND NOT ISSUED (DURING CONSOLE SELF TESTS, OR IF SELF TESTS FAILED).
16 DS22 LIT = FLUORO SELECTED, DS23 LIT = RAD SELECTED.
17 DS2 LIT = PULSED FLUORO / LOW POWER MODE. DS4 LIT = HIGH POWER RAD MODE. SEE # 13.
18 D1 LIT INDICATES + OR - 12 VDC FAULT, OR SOFT START FAULT.
19 THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE 1 BELOW.
18 s
4V
FIGURE 1
-8 V
DRAWN DATE
G. SANWALD 10 MAR 2000 DC BUS & POWER
CHECKED________ ________ DISTRIBUTION
DES.\MFG.\AUTH.
HTW 10 MAR 2000 MD-0788 REV AB
SHEET 6 OF 6
Use and disclosure is subject to the restrictions on the title page of this CPI document.
24 VDC RETURN
T2 F5 D3
+ 24 VDC J17-1 J17-2
*
S3
Q1 LOCKOUT NORMAL
R15
24 VDC SUPPLY FOR Q2 D4 K3
SYSTEM ON/OFF.
SEE MD-0788, PAGE 4
S1 D16
OFF REFER TO DC BUS &
K2 POWER DISTRIBUTION,
Q3 MD-0788, PAGE 4
R13
S2
DS1
ON
K1
3
JUMPER POSITION:
TO ENERGIZE K1 ONLY WHEN
THE CONSOLE IS SWITCHED ON
JUMPER JW1 PINS 1-2
TO ENERGIZE K1 AT ALL TIMES THAT
JW1
P1-3 J5-10 1 3 2 1 THE GENERATOR AC MAINS IS ON
J3-3 J4-10
JUMPER JW1 PINS 2-3
(K1 SWITCHES THE 110 & 220 VAC
R & F MEMBRANE SUPPLIES TO THE ROOM
INTERFACE BOARD)
CONSOLE
ON P1-2 J3-2 J5-11 J4-11 2
OFF
P1-1 J3-1 J5-12 J4-12
CONSOLE
KEYBOARD ASSEMBLY BOARD
RAD-ONLY
CONSOLE ON P1-16 J7-16 J8-7 J16-7
OFF
P1-17 J7-17 J8-3 J16-3
CONSOLE
KEYBOARD ASSEMBLY BOARD
TOUCH SCREEN USE DRAWING DC BUS & POWER DISTRIBUTION, MD-0788, IN CONJUNCTION WITH THIS DOCUMENT
CONSOLE J1-4 J16-4 J28-10 J4-10
* TO CONNECT AN EMERGENCY-OFF SWITCH, REMOVE JUMPER FROM J17-1 TO J17-2. THEN CONNECT
THE EMERGENCY OFF SWITCH TO J17-1 AND J17-2.
OFF J1-5 J16-5 J28-11 J4-11
SW1 ON
SW2
J1-6 J16-6 J28-12 J4-12 DRAWN DATE
G. SANWALD 02 JUN 2000
CHECKED_________ SYSTEM ON
_________
TOUCH SCREEN
FRONT PANEL BOARD BOARD DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000
MD-0762 REV H
SHEET 1 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.
NOTE
REMARKS
REFERENCE
MOMENTARILY PRESSING ON CONNECTS THIS LINE TO “24 VDC RETURN”. THIS LATCHES RELAY DRIVERS ON THE GENERATOR INTERFACE BOARD,
1 ENERGIZING K2 AND K3, AND POSSIBLY K1 (DEPENDING ON JW1 SETTING). SEE NOTE ADJACENT TO JW1 ON THIS DOCUMENT.
MOMENTARILY PRESSING OFF CONNECTS THIS LINE TO “24 VDC RETURN”. THIS UNLATCHES RELAY DRIVERS ON THE GENERATOR INTERFACE BOARD,
2 DE-ENERGIZING K2 AND K3, AND POSSIBLY K1 (DEPENDING ON JW1 SETTING).
DS1 LIT INDICATES THE PRESENCE OF THE 24 VDC SUPPLY SHOWN. THIS 24 VDC SUPPLY WILL BE PRESENT IF THE GENERATOR IS CONNECTED TO A
3
LIVE AC MAINS SUPPLY.
DRAWN DATE
G. SANWALD 02 JUN 2000
CHECKED_________ SYSTEM ON
_________
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000
MD-0762 REV H
SHEET 2 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+24V
NOTE *
TB1-5 J2-15 J9-15
SPARE / 4 3 2 1 JW7
TABLE TB1-4 J2-16 J9-16
STEPPER +24V 1 5
NOTE * U7, U12, U18,
R53 U21
TB2-5 J2-13 J9-13 U19, U25
+24V R54
BUCKY 4 3 2 1 JW10 2 4
NOTE *
CONTACTS TB2-4 J2-14 J9-14
4 3 2 1 JW9 1 5
TB2-7 J2-11 J9-11 R55 U31
1 5 R56
COLLIMATOR 2 4
INTERLOCK TB2-6 J2-12 J9-12 R66
U29 +24V
R67 2 4 NOTE *
TB3-5 J2-24 J9-24
4 3 2 1 JW2
REMOTE TOMO SEE
SELECT TB3-4 J2-25 J9-25 MD-0761 J12-1 J6-1
D0
R23
TB3-7 J2-22 J9-22 U8
TOMO
U10 J12-2 J6-2
EXPOSURE TB3-6 J2-23 J9-23 D1
R21
+24V
TB4-4 J2-21 J9-21
1 5
ROOM DOOR U14 +24V
D2 J12-3 J6-3
INTERLOCK *** TB4-5 +24V NOTE *
R29 R38 2 4 1 5 JW3
TB4-6 J2-20 J9-20 U13 4 3 2 1
D3 J12-4 J6-4
THERMAL R34 R36 +24V 1 5
2 4
SWITCH 2 TB4-7
R32 BUFFER, DRIVER
U9
T2 FROM MD-0787 R22 AND ADDRESS
TB4-8 J2-19 J9-19 U16 2 4
DECODER CIRCUITS D4 J12-5 J6-5
R33 R37
THERMAL
SWITCH 1 TB4-9
T1 FROM MD-0787
TB5-12 J2-17 J9-17 D5 J12-6 J6-6
REMOTE
PREP TB6-7 J2-6 J9-6 +24V
NOTE *
TB6-10 J2-3 J9-3
4 3 2 1 JW14
REMOTE
+24V
EXPOSURE TB6-9 J2-4 J9-4 R75
NOTE * 1 5
U28
4 3 2 1 JW15
TP14 J2-1 J9-1 R74 2 4
REFER TO PAGE R77 **
3 FOR DEFINITION J2-2 J9-2
OF INPUTS U41,
R76 U43
THIS PAGE SHOWS THE ROOM INTERFACE INPUTS. ROOM INTERFACE OUTPUTS ARE SHOWN ON PAGE 2 * * DRAWN DATE
** ADDITIONAL CIRCUITS ARE USED IN THE AREAS INDICATED **. THESE CIRCUITS ARE NOT 24 VDC EXTERNAL INPUT POSITION DRY CONTACT INPUT POSITION G. SANWALD 13 APR 2000 ROOM
FOR JW2, JW3, JW6, JW7, JW8, JW9, FOR JW2, JW3, JW6, JW7, JW8, JW9, CHECKED
RELEVANT TO THIS ROOM INTERFACE DIAGRAM, HOWEVER, THEY ARE PART OF THE X-RAY JW10, JW14, JW15 SHOWN. JW10, JW14, JW15 SHOWN. JUMPER S. BLAKE 14 APR 2000
INTERFACE
EXPOSURE FUNCTION AND ARE SHOWN ON MD-0761 JUMPER CONNECTS PINS 2-3; 24 VDC CONNECTS PINS 1-2 AND 3-4; AN DES.\MFG.\AUTH.
APPLIED EXTERNALLY ACTIVATES EXTERNAL DRY CONTACT CLOSURE MD-0763 REV K
THE INPUT(S) BY ENERGIZING THE ACTIVATES THE INPUT(S) BY ENERGIZING L. FOSKIN 13 APR 2000
*** REFER TO “ROOM DOOR INTERLOCKS” ON SHEEET 3. APPROPRIATE OPTO-COUPLER. THE APPROPRIATE OPTO-COUPLER.
SHEET 1 OF 3
Use and disclosure is subject to the restrictions on the title page of this CPI document.
FOR +24 VDC SOURCE, REFER TO +24V +24V
MD-0788, PAGE 4, ON
GENERATOR INTERFACE BOARD J9-40 J2-40 C2
TB1-2
U6, U7, U11, U12 J9-39 J2-39 R2 JW12 ***
U24, U25, U34 TOMO / BUCKY 4
K1 TB1-1
SELECT
TP1
DRIVE 1 J9-30 J2-30
C1
K1 TB1-11
JW1 1 2 3 4 5 6 7 8 R1 JW9 ***
TP2 BUCKY 3
DRY * LIVE * K2 TB1-12
SELECT
DRIVE 2 J9-29 J2-29
K2
TP3 TB11
JW2 1 2 3 4 5 6 7 8
R5
LIGHT
TP9 JW13
DRIVE 9 J9-36 J2-36
JW5 1 2 3 4 5 6 7 8 TB4-1 TUBE 1 / TUBE 2
J6-7 J12-7 K9
D6 DRY * LIVE * INDICATOR (COMM)
TP10 K7 TB4-3
TUBE 1 INDICATOR
DRIVE 10 J9-37 J2-37
TB4-2
K10 NOTE THE FOLLOWING IF USING JW1, JW2, TUBE 2 INDICATOR
J6-8 J12-8 +24V
D7 24 VDC E6 JW3, JW4, OR JW5 IN THE LIVE CONTACT
TP11 POSITION: TB5-2
TB8
J9-38 J2-38 A JUMPER WIRE MUST BE CONNECTED TO K9 TB5-4
DRIVE 11 JW6 1 2 3 4 MAG 3
TB11 PIN 1, 2, 3, 4 OR 5 AS APPROPRIATE
DATA BUS K11 TB5-3
FROM TB8, TB9, OR TB10 IN ORDER TO
DO..D7 SUPPLY 24 VDC, 110 VAC, OR 220 VAC DRY **
TP12
FROM THE SELECTED OUTPUT K10 TB5-7
LIVE 24 VDC **
DRIVE 12 J9-33 J2-33
TB5-6
K12 MAG 2
TP13 TB5-5
THIS PAGE SHOWS THE ROOM INTERFACE * LIVE CONTACT LIVE CONTACT ** LIVE CONTACT 24VDC LIVE CONTACT 24VDC
*** DRAWN DATE
OUTPUTS. ROOM INTERFACE INPUTS ARE THESE JUMPERS MAY NEED TO BE INSERTED G. SANWALD 13 APR 2000 ROOM
IN SOME APPLICATIONS. REFER TO CHECKED
SHOWN ON PAGE 1 CHAPTER 3B FOR DETAILS. S. BLAKE 14 APR 2000
INTERFACE
DRY CONTACT DRY CONTACT
DRY CONTACT DRY CONTACT DES.\MFG.\AUTH.
DRY CONTACT POSITION FOR LIVE CONTACT 24VDC POSITION
DRY CONTACT POSITION LIVE CONTACT POSITION JW6 TO JW8 SHOWN. FOR JW6 TO JW8 SHOWN. L. FOSKIN 13 APR 2000 MD-0763 REV K
Use and disclosure is subject to the restrictions FOR JW1 TO JW5 SHOWN. FOR JW1 TO JW5 SHOWN. JUMPER CONNECTS JUMPERS CONNECT
JUMPER CONNECTS PINS 4-6 JUMPER CONNECTS PINS 6-8 PINS 2-3 PINS 1-2 AND 3-4 SHEET 2 OF 3
on the title page of this CPI document.
INPUT DESCRIPTION
SPARE / TABLE STEPPER INPUT When used with the table stepper / kV-mAs reduction for peripheral angiography option (used for peripheral runoff studies), this input
tells the generator to advance to the next kV/mAs step.
When the above option is not enabled, this input may be programmed as a spare input.
BUCKY CONTACTS This indicates that the Bucky is ready for an exposure (the grid is moving). The outputs of all Buckys must be connected in parallel to this single
input.
COLLIMATOR INTERLOCK This is the input for the collimator interlock. This may be programmed to inhibit exposures if this input is not active.
REMOTE TOMO SELECT This input, when active, remotely selects tomography.
TOMO EXPOSURE Requests a tomographic exposure when this input is active. The exposure starts when the input is activated, and stops when the input is
deactivated.
ROOM DOOR INTERLOCK This is the interlock for the X-ray room door. If programmed, will inhibit an exposure when this input is not active.
THERMAL SWITCH 2 Input for the tube 2 thermal switch. Exposures are inhibited when this input is not active. The power supply is also turned off to prevent rotor
operation.
THERMAL SWITCH 1 Input for the tube 1 thermal switch. Exposures are inhibited when this input is not active. The power supply is also turned off to prevent rotor
operation.
MULTIPLE SPOT EXPOSURE Enables density compensation when doing multiple exposures on a single film. In this mode of operation, the X-ray field is usually coned down
to a small area. Due to the resulting AEC field cutoff, an AEC density offset may be required. This is designated multiple spot compensation.
The function MULT. SPOT COMP in the AEC calibration menus applies the required compensation.
I.I SAFETY / REMOTE HLF SELECT Refer to chapter 3B: On applicable units, if the HLF SELECT input is CONSOLE, this will be the input for the image intensifier position interlock.
If the HLF SELECT input is REMOTE, this will be the high-level fluoro select input.
REMOTE FLUORO EXPOSURE Fluoro foot switch input. Fluoro exposures are requested when this input is active.
REMOTE PREP External PREP request, typically generated by room equipment.
REMOTE EXPOSURE External X-ray EXPOSE command from room equipment (i.e. table or digital imaging system).
Certain inputs will only be active if enabled in programming (per chapter 3C), and / or the generator includes the corresponding option.
DOOR DOOR
Configuration A INTERLOCK Configuration B INTERLOCK
SWITCH SWITCH
TB4-4 TB4-4
Inhibits new exposures if the room Inhibits new exposures if the room
ROOM DOOR INTERLOCK ROOM DOOR INTERLOCK
door is open. Does not interrupt TB4-5 door is open. Stops fluoro exposures TB4-5
exposures in process when the if the room door is opened
door is opened. FLUORO during a fluoro exposure.
FOOT
SWITCH DOOR INTERLOCK SWITCH
TB6-5 TB6-5
(R&F UNITS
ONLY) TB6-6
REMOTE FLUORO EXPOSURE TB6-6
REMOTE FLUORO EXPOSURE
R39, R57
2 4
HOLD CIRCUIT MD-0767, PAGE 1
NOTES, ETC, REFERENCED BY
RN19B
(U39, C30, ETC.)
HEXAGONAL SYMBOL:
1 5
R92
EXP
U42 U25, U12, U7 SWT U28
R82
CPU
DRIVER
4
1 5 BUFFER AND ADDRESS TO 2.1 V
REMOTE FLUORO DECODER (U18, U25) CURRENT 1 5
EXPOSURE INPUT U30 SINK
TP4 TP5 TP6
2 U46
2 4
1 J9-8 R70 2 4
SEE NOTE 1
R15
R16
R14
U18, U25 RN14C
J5-6 J4-6 R19 R20 +24V
BUFFER AND J12-5 J6-5
J5-7 J4-7 1 5 ADDRESS
J5-8 J4-8 DECODER RN14D
U15 5
R24
+5V +5V +5V +24V
J5-9 J4-9 R25 2 4 1 5
U25, U12, U7
R11
R12
R13
U38
U18 2 4 ADDRESS DECODER, J12-7 J6-7 RN14B
J16-3 DATA LATCH, AND
DRIVER
FPGA FROM
4
RAD-ONLY 1 5 U18, U25
CONSOLE J16-4 U37 BUFFER AND J12-4 J6-4 RN14E
(PAGE 3) ADDRESS
J16-5 R18 R72 2 4
DECODER
5
4 1
KV CONTROL
DATA BUS U3 +24V
REFER TO MD-0759
D0..D7 4 1
3 2
U2 4 3 2 1 JW15 SEE NOTE 1
4 1
3 2
J13-7 J9-3
U4
FLUORO MA CONTROL
3 2 R77 REFER TO MD-0760
FOOT J9-4
SWITCH J13-9 1 5
U43 U25, U12, U7
J13-3 2 4 ADDRESS DECODER, J12-5 J6-5 RN14D
PREP DATA LATCH, AND
DRIVER
REMOTE
4
J13-1 1 5 BUFFER AND ADDRESS
HAND EXPOSURE DECODER (U18, U25)
X-RAY
SWITCH INPUT U41
R76 2 4
J13-5
COM
P1-19 R23
PREP J9-25
1 5
J6-8
X-RAY U8 U25, U12, U7 DATA BUS
THE CONSOLE BOARD & P1-20 ADDRESS DECODER, D0..D7
2 4 J12-8
KEYBOARD ASSEMBLY DATA LATCH, AND
SHOWN ON THIS PAGE IS REMOTE DRIVER GENERATOR CPU BOARD
TOMO 4
USED ON THE 31 X 42 CM 1 5 BUFFER AND ADDRESS
SELECT DECODER (U18, U25)
CONSOLE ONLY. REFER TO PAGE INPUT DRAWN DATE
U10
3 FOR THE 23 X 56 CM CONSOLE
R21
G. SANWALD 26 APR 2000 X-RAY EXPOSURE
AND THE RAD-ONLY CONSOLE, KEYBOARD ASSEMBLY 2 4 CHECKED RAD/FLUORO
AND PAGE 4 FOR THE S. BLAKE 26 APR 00
TOUCH SCREEN CONSOLE. DES.\MFG.\AUTH.
GENERATOR INTERFACE BOARD
26 APR 2000
MD-0761 REV L
L. FOSKIN
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 1 OF 4
TUBE 1 / TUBE 2 MISMATCH &
THERMOSTAT OPEN SIGNAL
FROM MD-0787
13
J1-4
AUXILIARY BOARD
RN11D
R174
KV
EN D19 U33F
+5V R173 RESET COMMAND TO MD-0759, PAGE 1 & J9-9 J3-9
DS30 DS31
14 13 12
MD-0760, PAGE 2
DS26 X-RAY TP10 J9-7 J3-7
RN11C
RN2F
U27 TP18
J1-15 RN1C “PREP ENABLED”
DATA BUFFER AND J10-15 DETECTOR CKT PREP COMMAND TO MD-0764 & MD-0765
1 5 (U11B, U10C, ETC) J1-3
LATCH DRIVER
CONTINUED
U2 D24 D25 RN4B J1-22 ON PAGE 3
J10-34 RN1D 2 4
J1-34
“GENERATOR READY” 18 R133
DETECTOR CIRCUIT Q12
11 J10-16 (U10A, Q6, D37, ETC)
DATA BUS
D0..D7 12
EXPOSURE ENABLE COMMAND J10-35 +/- 12V/SS FAULT FROM MD-0788,
FROM PAGE 1 PAGE 3 (CONTROL BOARD)
DRAWN DATE
G. SANWALD 26 APR 2000 X-RAY EXPOSURE
CHECKED RAD/FLUORO
S. BLAKE 26 APR 00
DES.\MFG.\AUTH.
L. FOSKIN 26 APR 2000
MD-0761 REV L
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 2 OF 4
+5V
RN7D
+5V
P/S
READY
DS17 DS18
1
R10
R8
R9
GRN RED
19 TO 2.1 V J5-6
J4-6
CURRENT J5-7
SINK J4-7
OPTO-COUPLER “ON” U24 J5-8
= GENERATOR READY J4-8 TO
1 5 1 5 1 5 GENERATOR
BUFFER INTERFACE
J1-3 J10-3 1 5 U14 U12 U10 BOARD
FROM (PG 1)
U6 2 4 2 4 2 4
PAGE 2 J1-22 J10-22
2 4 J5-9
U3 J4-9
BUFFER
DATA BUS
D0..D7
5 1 5 1 5 1
CONTROL BOARD GENERATOR CPU BOARD
U21 U13 U11
4 2 4 2 4 2
DATA BUS
D0..D7
1
TP12 TP13 TB1-1
FOOT
J8-4 TO SWITCH
+3.3V +3.3V J16-4 GENERATOR TB1-2
J8-5
J16-5 INTERFACE
J8-3 BOARD
J16-3 (PG 1) TB1-3
R56
R55
PREP
U21
HAND TB1-4
X-RAY
SWITCH
FPGA
TB1-5
COM
P1-2 Use and disclosure is subject to the restrictions on the title page of this CPI document.
PREP
X-RAY
P1-1 DRAWN DATE
G. SANWALD 26 APR 2000 X-RAY EXPOSURE
CHECKED RAD/FLUORO
KEYBOARD ASSEMBLY CIRCUITS SHOWN WITHIN S. BLAKE 26 APR 00
DASHED LINES ARE USED DES.\MFG.\AUTH.
ON RAD-ONLY CONSOLE. L. FOSKIN 26 APR 2000
MD-0761 REV L
SHEET 3 OF 4
J30-1
X-RAY
J30-3 HAND
PREP SWITCH
J30-5
COM
PREP
SW1 J2-3 J21-3 J28-7 TO J4 ON
EXP GENERATOR
SW2 J2-4 J21-4 J28-8 INTERFACE
BOARD
J2-5 J21-5 J28-9 (PG 1)
NOTE
REMARKS
REFERENCE
“LOW” (APPROXIMATELY 1 VDC) AT THESE POINTS INDICATES FOOT SWITCH INPUT CLOSED, PREP SWITCH PRESSED, OR X-RAY SWITCH PRESSED RESPECTIVELY. “HIGH” (APPROXIMATELY 24 VDC) =
1 OPEN CIRCUIT (I.E. NOT PRESSED) FOOT SWITCH, OR PREP SWITCH, OR X-RAY SWITCH. FOR RAD-ONLY CONSOLE, “LOW” INDICATES PREP SWITCH PRESSED, OR X-RAY SWITCH PRESSED, RESPECTIVELY.
2 “LOW” (APPROXIMATELY 1 VDC) = AN X-RAY EXPOSURE HAS BEEN REQUESTED VIA ONE OF SEVERAL EXPOSURE INPUTS. “HIGH” (APPROXIMATELY 24 VDC) = NO X-RAY EXPOSURE HAS BEEN REQUESTED.
3 EXPOSURE ENABLE LINE. “LOW” (APPROXIMATELY 0 VDC) INDICATES AN X-RAY EXPOSURE REQUEST, “HIGH” (APPROXIMATELY 5 VDC) = NO X-RAY EXPOSURE HAS BEEN REQUESTED.
THE CATHODE OF THE ASSOCIATED LED IS HELD “LOW” UNDER CPU CONTROL DURING AN X-RAY EXPOSURE REQUEST ONLY. NO MEANINGFUL MEASUREMENTS CAN BE MADE ON THIS LINE AS THIS IS A
4 DATA LINE. THE REQUIRED DATA IS LATCHED BY THE REGISTER CIRCUIT(S) AT THE APPROPRIATE TIME.
THE OUTPUT OF THE ASSOCIATED LED IS LATCHED BY A REGISTER. THIS IS THEN READ BY THE DATA BUS AT THE APPROPRIATE TIME. AS THIS IS A DATA LINE, NO MEANINGFUL MEASUREMENTS CAN BE
5 MADE AT THIS CONNECTION.
6 DS30 LIT = KV ENABLE REQUEST SENT. THIS IS NECESSARY TO MAKE AN X-RAY EXPOSURE. DS31 LIT = KV ENABLE NOT REQUESTED.
7 DS27 LIT = PREP REQUEST SENT. DS28 LIT = PREP NOT REQUESTED.
8 DS26 LIT = X-RAY EXPOSURE IN PROCESS.
9 “HIGH” (APPROXIMATELY 5 VDC) = KV ENABLED, “LOW” (APPROXIMATELY 0 VDC) = KV NOT ENABLED.
10 “HIGH” (APPROXIMATELY 5 VDC) = PREP REQUESTED. “LOW” (APPROXIMATELY 0 VDC) = PREP NOT REQUESTED.
11 “HIGH” (APPROXIMATELY 5 VDC) = X-RAY REQUESTED. “LOW” (APPROXIMATELY 0 VDC) = X-RAY NOT REQUESTED.
12 “LOW” = X-RAY EXPOSURE REQUESTED AS PER # 3. THIS LINE MUST BE “LOW” IN ORDER FOR THE X-RAY EXPOSURE LED’S ON THE CONTROL BOARD TO BE ENERGIZED (SEE # 16).
13 “LOW” = (APPROXIMATELY 0 VDC) = TUBE 1 / TUBE 2 MISMATCH OR THERMOSTAT OPEN FAULT. “HIGH” (APPROXIMATELY 12 VDC) = NO FAULT.
14 “HIGH” (APPROXIMATELY 12 VDC) = KV ENABLED, “LOW” (APPROXIMATELY 0 VDC) = KV NOT ENABLED.
15 “HIGH” (APPROXIMATELY 12 VDC) = PREP REQUESTED, “LOW” (APPROXIMATELY 0 VDC) = PREP NOT REQUESTED.
16 “HIGH” (APPROXIMATELY 12 VDC) = X-RAY REQUESTED, “LOW” (APPROXIMATELY 0 VDC) = X-RAY NOT REQUESTED.
17 “HIGH” (APPROXIMATELY 5 VDC) = OUTPUT DRIVE ENABLED, “LOW” (APPROXIMATELY 0 VDC) = OUTPUT DRIVE DISABLED.
ALL INPUTS TO THE “GENERATOR READY DETECTOR CIRCUIT” MUST BE AT THE CORRECT LOGIC LEVEL IN ORDER TO BE ABLE TO MAKE AN X-RAY EXPOSURE. THIS MEANS ALL FOUR FAULT INPUTS SHOWN
18
MUST BE CLEARED, AND THE KV ENABLE AND PREP COMMANDS MUST BE PRESENT.
DS17 LIT INDICATES GENERATOR READY TO MAKE AN EXPOSURE. THIS REQUIRES THAT ALL CONDITIONS PER # 18 BE SATISFIED. DS18 LIT INDICATES A “GENERATOR READY DETECTOR CIRCUIT” INPUT IS
19
NOT SATISFIED TO ENABLE AN X-RAY EXPOSURE.
DRAWN DATE
G. SANWALD 26 APR 2000 X-RAY EXPOSURE
CHECKED RAD/FLUORO
S. BLAKE 26 APR 00
DES.\MFG.\AUTH.
L. FOSKIN 26 APR 2000 MD-0761 REV L
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 4 OF 4
2 R53
2
TP9 TP8 R68 -
2
TP6 TP8 1 R49 J9-6
+
3
6 R91 R67
R41
-
R42
7 R26 RN4A U12A
R36
R35
5
R52
+ J9-5
R48
U15B RN2A R24 2
2 J10-31 J1-12 1 -
6
- R89 -
R31
1 3 7
R215
+
+
3 +
5 J9-7 KV FEEDBACK SIGNAL
J10-12 J1-31 U16A FROM PAGE 3
U15A U16B
RN2B R23 R54
R37
RN4B
R69 -
6
7
R72
RESET COMMAND 5 R50 J9-8
+
FROM MD-0761, PG 2
U12B
R221
HIGH KV / INVERTER FAULT
R220
TO GENERATOR READY
DETECTOR CIRCUIT ON
CONTROL BOARD, D92 ANODE OVERVOLTAGE
SEE MD-0761, PG 2 +12V SIGNAL TO MD-0760, PG 2
+12V +12V +12V
HV ON SIGNAL D80 D81 D82 D93 CATHODE OVERVOLTAGE
R172
U37 TO MD-0767, PG 1 SIGNAL TO MD-0760, PG 2
10
A/D
INV 3 INV 2 INV 1
R208
R209
R210
CONVERTER 3 U33E
D69
kV INVERTER 1 J14-1
TP26 INVERTER 1
11
FAULT LATCH &
HIGH KV FAULT DETECTOR
LOGIC INVERTER J14-3
D63 DETECTOR (T3, U36, D83, ETC)
(U39B, U35F)
AND LATCH
(U31, U32A, U33A)
HV ON DETECTOR
CIRCUIT (U30C INVERTER 2 J15-1
JW3 INVERTER 2
U30D, Q6, ETC) “OR” FAULT LATCH & INVERTER FAULT SIGNALS
125kV 150kV FAULT DETECTOR
LOGIC LOGIC INVERTER J15-3 FROM PAGE 2
(T4, U37, D84, ETC)
JUMPER POSITION: (U39C, U35E)
125kV GENERATORS
JUMPER “125kV” D87-D89, U35C
150 kV GENERATORS
JUMPER “150kV” INVERTER 3 J16-1
INVERTER 3
FAULT LATCH &
FAULT DETECTOR
D86 LOGIC INVERTER J16-3
(T5, U38, D85, ETC)
TP2 (U39D, U35D)
1
4
R25
R46
U22 +5V TP17 TP19
2 R26, R45
- 1 J10-7 J1-7
D/A 3+ D48
R132
CONVERTER 2- ERROR AMPLIFIERS
R171
R180
U14A 1 R71 R70
3+ INCLUDES U13B, U21A
R106 U24A U26A
2
J10-26 J1-26 R25, R44 U13A - D49 3 2 7
D35 - R107 6- 1
+ VCO
7
U13B
+
5+ INCLUDES U19, U20, DRIVE PULSES
R43
+12V U21A U23, U25, U27, Q10 U24B U26B CONTINUED ON PAGE 2
U21B 5 6 4 5
R108
4
R175
D66
D70
DATA BUS Ir
D0..D7
R66
DRIVE ENABLE
T1 T2 COMMAND FROM
MD-0761, PAGE 2
-12V
J13-4 J13-1
GENERATOR CPU BOARD CONTROL BOARD
DRAWN DATE
H.T. PRIMARY CURRENT SENSE G. SANWALD 18 MAY 2000 KV CONTROL &
FROM PAGE 2 CHECKED
S. BLAKE 18 MAY 2000 FEEDBACK
DES.\MFG.\AUTH.
L. FOSKIN 18 MAY 2000 MD-0759 REV E
SHEET 1 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
E1: 560 / 650 VDC (+) REFER TO MD-0786 FOR
K1 DRIVE CIRCUITS
* USED ON R&F K1 *
GENERATORS ONLY
J2-1
TO J14-1 INVERTER FAULT
J2-3 SIGNAL, TO PAGE 1
TO J14-3
E3
J10-3 J1-3
J10-4 J1-4 MOSFET MOSFET
SWITCHES SWITCHES
*
E4
J2-1
TO J15-1 INVERTER FAULT
J2-3 SIGNAL, TO PAGE 1
TO J15-3
E4
J2-1
TO J16-1 INVERTER FAULT
J2-3 SIGNAL, TO PAGE 1
TO J16-3
E3
J12-3 J1-3
J12-4 J1-4 MOSFET MOSFET
DRIVE PULSES SWITCHES SWITCHES
FROM PAGE 1
E4
+12V
K2
REFER TO E2: 560 / 650 VDC (-) J1-1 J1-4
MD-0786
RESONANT BOARD
CONTROL BOARD INVERTER BOARD #3
H.T. PRIMARY CURRENT TO J13-1
INDICO 100 GENERATORS USE ONE, TWO, OR THREE INVERTER SENSE, TO PAGE 1 TO J13-4
MODULES DEPENDING ON GENERATOR OUTPUT POWER
DRAWN DATE
G. SANWALD 18 MAY 2000 KV CONTROL &
CHECKED FEEDBACK
S. BLAKE 18 MAY 2000
DES.\MFG.\AUTH.
L. FOSKIN 18 MAY 2000 MD-0759 REV E
SHEET 2 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
HV ANODE
BOARD
J1
ANODE
C S
L
J3-8
TO J9-8 HV MULT
ASSY +
J3-7 (ANODE)
KV FEEDBACK TO J9-7
SIGNAL
TO PAGE 1 J3-5
TO J9-5
J3-6
TO J9-6
E9
HV MULT
ASSY-
E10 (CATHODE)
FROM
PAGE 2 L
C
S
HV CATHODE J2
TANK LID CATHODE
BOARD
BOARD
12 VDC
0 VDC
FIGURE 1
DRAWN DATE
G. SANWALD 18 MAY 2000 KV CONTROL &
CHECKED FEEDBACK
S. BLAKE 18 MAY 2000
DES.\MFG.\AUTH.
18 MAY 2000
MD-0759 REV E
L.FOSKIN
SHEET 4 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V J2-8 5.5 A 6.5 A JW1 SELECTS MAXIMUM
JW1 1 2 3 FILAMENT CURRENT
5.5 OR 6.5 AMPS
RN7C
J2-7
RN2H
CURRENT OPTO-COUPLER TP1
U24 “ON” = NO FILAMENT FILAMENT FAULT J2-10
SINK C22
FAULT J10-4 J1-4 TO MD-0761, PAGE 2
BUFFER BUFFER /
5 1 J2-4 AMPLIFIER & T1 J5-4
+5V FILAMENT
FILAMENT CURRENT CURRENT RMS SMALL FILAMENT DRIVE
U7
FEEDBACK SIGNAL COMPARATOR CONVERTER J4 J5-3 CONTINUED ON PAGE 2
(SM) TO PAGE 2 J2-3
RN7E
4 2 J10-23 J1-23 RN4D CIRCUIT
R137 J3-10
HV Q15
+12V
DS11 DS12 RN2G
3 FILAMENT SUPPLY BOARD (SMALL)
J10-5 J1-5
GRN RED 5 1
TO 2.1 V U8 RN4C
CURRENT R136 HV / MA FAULT J2-6 5.5 A 6.5 A JW1 SELECTS MAXIMUM
U24 4 2 J10-24 J1-24 Q14 FROM MD-0761, JW1 1 2 3 FILAMENT CURRENT
SINK
PAGE 2 5.5 OR 6.5 AMPS
J2-5
BUFFER
OPTO-COUPLER
“ON” = NO HV / MA J3-2 J2-2 J3-8 BUFFER &
J2-9 CURRENT LIMIT
FAULT ERROR
CIRCUIT AMPLIFIER &
J3-10 J2-10 J3-7 DRIVER CIRCUIT
TP3
1 TP2
3
R10
J3-9 TP1
R5
U18 J2-10
13 - R7 C22
14 TP21 BUFFER /
D/A 12 + AMPLIFIER &
J2-2 T1 J5-2
CONVERTER FILAMENT
U14D TP1
1 FILAMENT CURRENT CURRENT RMS LARGE FILAMENT DRIVE
R17 FEEDBACK SIGNAL COMPARATOR CONVERTER J8 J5-1 CONTINUED ON PAGE 2
(LG) TO PAGE 2 J2-1 CIRCUIT
R11
JW5 JUMPER POSITION: INDICO 100 GENERATORS WITH STANDARD SINGLE FILAMENT BOARD (TYPICALLY USED IN RAD
INDICO GENERATORS ONLY GENERATORS) USE THE FILAMENT BOARD CONFIGURATION SHOWN BELOW
JUMPER PINS 1-2
DS24 DS25 DO NOT USE JUMPER
POSITION 2-3
J2-6 5.5 A 6.5 A JW1 SELECTS MAXIMUM
LARGE SMALL JW5 JW1 1 2 3 FILAMENT CURRENT
OPTO-COUPLER
5.5 OR 6.5 AMPS
TO 2.1 V 1 2 3 “ON” = LARGE FOCUS J2-5
CURRENT SELECTED
U27 SINK U19, U16 “LG/SM REQUEST” 4 BUFFER &
J3-11 J2-9 CURRENT LIMIT
2 J10-17 J1-17 RN1A DETECTOR CKT TO J3-6, J3-5, J3-9, J3-10 ERROR
DATA BUFFER AND (U11C, Q2, ETC) ON CONTROL BOARD CIRCUIT AMPLIFIER &
LATCH DRIVER 1 5 DRIVER CIRCUIT
J10-36 J1-36 3
+5V U1 TP1
RN1B 2 4 J2-10
T1 C22
RN6E
OPTO-COUPLER
U24 “ON” = SMALL FOCUS +12V J2-4 RMS
BUFFER /
SELECTED RN2E FIL CURRENT FEEDBACK CONVERTER
J10-8 J1-8 J2-3 AMPLIFIER &
BUFFER SIGNAL (SM) TO PAGE 2 FILAMENT CIRCUIT J5-3
5 1 J2-2 CURRENT SMALL FILAMENT DRIVE
FIL CURRENT FEEDBACK COMPARATOR J5-4 CONTINUED ON PAGE 2
U10 SIGNAL (LG) TO PAGE 2 J2-1 TP2 +12V
DATA BUS 4 2 RN4A J5-1
J10-27 J1-27 K1
D0..D7 R75 J2-11 LARGE FILAMENT DRIVE
K1
Q3 J5-2 CONTINUED ON PAGE 2
FILAMENT SUPPLY BOARD (UNIVERSAL)
GENERATOR CPU BOARD CONTROL BOARD
DUE TO SPACE RESTRICTIONS, THIS PAGE SHOWS
DRAWN DATE
ONLY THE MAJOR FILAMENT BLOCKS. REFER TO
REFER TO PAGE 4 FOR LOGIC LEVELS, PAGE 3 FOR A MORE DETAILED FUNCTIONAL
G. SANWALD 12 MAY 2000 FILAMENT DRIVE
CHECKED & MA CONTROL
NOTES, ETC, REFERENCED BY DIAGRAM OF THE FILAMENT SUPPLY BOARD. S. BLAKE 12 MAY 2000
HEXAGONAL SYMBOL: DES.\MFG.\AUTH.
L. FOSKIN 15 MAY 2000 MD-0760 REV G
SHEET 1 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
J3-4 J2-3
FILAMENT CURRENT FROM J2-4
FEEDBACK SIGNAL SM FILAMENT FEEDBACK
J3-3 J2-11 CONTINUED ON PAGE 3
(SM) FROM PAGE 1 FROM J2-3
J2 **
J5-1 J4-1 CATHODE
LARGE J5-2 J4-2 S
C J3-2 J1-13
L FILAMENT CURRENT FROM J2-2
FEEDBACK SIGNAL LG FILAMENT FEEDBACK
J3-1 J1-32 CONTINUED ON PAGE 3
(LG) FROM PAGE 1 FROM J2-1
FROM PAGE 1 5
8
J5-3 J4-3
TP4 TP5
SMALL J5-4 J4-4
R163
R5
R6
CATHODE
H.T. BOARD 6- R4 J1-11
7
5+
RAD MA FEEDBACK
R216 U30B R3 J1-30 CONTINUED ON PAGE 3
FILAMENT SUPPLY
R165
R164
BOARD H.T.TANK R213
2
- 6 9
R33, R32 3 TP6 TP7
J1 HV ANODE +
ANODE BOARD U9
R36
HIGH MA FAULT TO
GENERATOR READY
R17
R16
S C 7 +12V DETECTOR CIRCUIT
L TP2 TP3 ON CONTROL BOARD, R15
SEE MD-0761, PAGE 2 J2-1
R34 R212
R179
FLUORO MA FEEDBACK
R14 J2-9 CONTINUED ON PAGE 3
R7
R9
10
ANODE OVERVOLTAGE D72
SIGNAL FROM MD-0759, PG 1 U33E
J3-1 J9-1 RN6C, RN6D R19 ANODE I
11
ANODE OVER- HIGH ANODE
6- CURRENT LATCH
7 CURRENT DETECTOR
& LOGIC INVERTER
R8
5+ (U18, RN9E-H, ETC.)
(U32C, U33C) D65
J3-2 J9-2 RN6A, RN6B U6B D95
R38
mA
TEST
E18 JACK
-
RESET COMMAND
+ FROM MD-0761, PG 2
E17
+12V
R177
R39 CATHODE OVERVOLTAGE D71
SIGNAL FROM MD-0759, PG 1
J3-4 J9-4 RN6G, RN6H CATHODE
HIGH CATHODE
CATHODE OVER-
2- CURRENT LATCH
1 CURRENT DETECTOR
R18
L C
R40
S H.T.TANK
J2
CATHODE HV CATHODE TANK LID
BOARD BOARD DRAWN DATE
G. SANWALD 12 MAY 2000 FILAMENT DRIVE
CHECKED & MA CONTROL
PART OF HV OIL TANK CONTROL BOARD S. BLAKE 12 MAY 2000
DES.\MFG.\AUTH.
** ONE TUBE H.T. OUTPUTS ARE SHOWN. TWO TUBE L. FOSKIN 15 MAY 2000 MD-0760 REV G
TANKS WILL HAVE A SECOND PAIR OF H.T. OUTPUTS
SHEET 2 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
MAXIMUM FILAMENT CURRENT SET MAX
LIMIT CIRCUIT CURRENT
6 ERROR AMPLIFIER, PWM REGULATOR,
JW1 AND FILAMENT CURRENT DRIVERS
TP25 TP24
3
R61 +
6.5 A
R57
2
-
1 5.5 A
RN8D U1A +35V
-12V
J3-11 RN9D 6-
7 R63
SM FILAMENT FEEDBACK 5 +
FROM ON PAGE 2 J3-3
U30B D6
R62
RN9C R72 11
RN8C
Q6 Q12
J2-8 R63 6- TP3
7 R95 R77 U3
5+ -
U4B PWM
TP23 TP22 REGULATOR
R71
R67 J2-6 R65
R64
J2-5 R66
RN8B Q13
J10-32 RN9B 2- Q7
1 R59
LG FILAMENT FEEDBACK 3
R85
+ C22
FROM ON PAGE 2 J10-13
U30A
R60
J2-9
RN9A
RN8A
-35V
3 TP1 10
U37
11 J2-10 TP2 TP4 J5-2
R84
R39 J5-4
CONVERTER K1 IS FITTED ON “UNIVERSAL” (LARGE/SMALL) K1
R38
RN2C 12 +
RN1C
U15D
R23
T1
J2-4 R67 D12, 13
Q1 U7 D27, 28
U4A RMS
J2-3 R68 +
12 1.7 V CONVERTER
U2A Ref -
TP11 TP14 -
J2-2 R69 +
R50
R45
J2-1 R70
RN4C
-
J3-9 RN5C 2-
1 R79 +
FLUORO MA FEEDBACK 3+ U2B R21
FROM ON PAGE 2 J3-1
U23A
R88
RN5D
RN4D
DATA BUS
D0..D7
GENERATOR CPU BOARD FILAMENT SUPPLY BOARD
DRAWN DATE
G. SANWALD 12 MAY 2000 FILAMENT DRIVE
CHECKED & MA CONTROL
S. BLAKE 12 MAY 2000
DES.\MFG.\AUTH.
L. FOSKIN 15 MAY 2000 MD-0760 REV G
SHEET 3 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
NOTE
REMARKS
REFERENCE
1 FILAMENT REFERENCE OUTPUTS, GENERATED BY THE CPU. SCALING IS 1 VOLT OUT = 1 AMP OF FILAMENT CURRENT.
2 “HIGH” (APPROXIMATELY 5 VDC) = LARGE FOCUS SELECTED, “LOW” (APPROXIMATELY 0 VDC) = SMALL FOCUS SELECTED. THIS SIGNAL IS USED IN SINGLE FILAMENT SUPPLY GENERATORS ONLY.
3 “HIGH” (APPROXIMATELY 12 VDC) = FILAMENT FAULT (FILAMENT CURRENT < 2 A). “LOW” (APPROXIMATELY 0 VDC) = NO FILAMENT FAULT.
4 “HIGH” (APPROXIMATELY 12 VDC) = LARGE FOCUS SELECTED, “LOW” (APPROXIMATELY 0 VDC) SMALL FOCUS SELECTED.
5 PRIMARY FILAMENT CURRENT AT THESE POINTS MAY BE CONFIRMED USING A CURRENT PROBE ON ONE OF THE OUTPUT LEADS ON THE SMALL OR LARGE PAIR OF OUTPUTS.
6 THE VOLTAGE AT THESE TEST POINTS WILL BE APPROXIMATELY 1 VDC = 1 AMP OF FILAMENT CURRENT.
7 THESE TEST POINTS ALLOW MEASUREMENT OF A VOLTAGE PROPORTIONAL TO ANODE CURRENT. THE SCALING IS 0.4 VDC = 100 mA. SHORT EXPOSURE TIMES MUST BE CONSIDERED AND APPROPRIATE
MEASUREMENT TECHNIQUES MUST BE USED.
8 THESE TEST POINTS ARE SCALED 1 VDC = 100 mA OF X-RAY CURRENT.
9 THESE TEST POINTS ARE SCALED 1 VDC = 2.5 mA OF X-RAY CURRENT (R&F GENERATORS ONLY).
10 FILAMENT FEEDBACK CURRENT TEST POINT. THIS IS SCALED 1 VDC = 1 AMP OF FILAMENT CURRENT.
11 PWM OUTPUT. THE WAVEFORM WILL BE AS PER FIGURE 1 FOR LOW AND HIGH FILAMENT CURRENT DEMAND.
0V
FIGURE 1
+12 V
HIGH FILAMENT
DEMAND
0V
DRAWN DATE
G. SANWALD 12 MAY 2000 FILAMENT DRIVE
CHECKED & MA CONTROL
S. BLAKE 12 MAY 2000
DES.\MFG.\AUTH.
L. FOSKIN 15 MAY 2000 MD-0760 REV G
SHEET 4 OF 4
Use and disclosure is subject to the restrictions on the title page of this CPI document.
REFER TO PAGE 2 FOR LOGIC LEVELS,
NOTES, ETC, REFERENCED BY
HEXAGONAL SYMBOL:
+12V TUBE 1
J3-9 SHIFT
R1
J1-1
* See note
+12V K2
CONTINUED
ON PAGE 2 J3-3 MAIN
R121
J1-20 RN4E
K4 COMM
R138 J6-10 J5-10
2 +12V
Q18
D7
R29 J4-9 J4-9 J3-8 J2-8
1
Q3
R30
K1 TUBE 2
J3-7 SHIFT
STATOR FAULT TO GENERATOR
READY DETECTOR CIRCUIT ON K3
CONTROL BOARD, SEE MD-0761
TP1
J3-5 MAIN
J3-1 COMM
PREP COMMAND J6-8 J5-8
3
FROM MD-0761, COMMON FROM J1-4. REFER
PAGE 2 F3
TO LOW SPEED STARTER
BOARD ON MD-0788, PAGE 1
JUMPER POSITION:
INDICO 100 GENERATORS
JUMPER “1.5S” FOR 1.5 SEC 120 / 240 VAC FROM J1-1. REFER Q2
F1
BOOST, NO JUMPERS FOR TO LOW SPEED STARTER
2.5 SEC BOOST. REFER TO BOARD ON MD-0788, PAGE 1
4 TP3 +12V
CH. 2 OF SERVICE MANUAL.
DO NOT USE JUMPER ZERO
POSITION “.15S”
R36
CROSS
R5
TP3 CIRCUIT
JW1 U2
BOOST AND J4-11 J4-11 J3-7 J2-7
.15S RUN LOGIC
CIRCUIT
1.5S (U1, U10, U18
Q2, Q12, ETC.) 52 / 73 / 94 VAC FROM J1-3. Q1
F2
REFER TO LOW SPEED STARTER
5 BOARD ON MD-0788, PAGE 1
TP4 +12V
ZERO
TUBE 1 / TUBE 2 MISMATCH &
R35
CROSS
R1
THERMOSTAT OPEN SIGNAL TP2 U1 CIRCUIT
FROM MD-0787
J4-12 J4-12 J3-6 J2-6
12 VDC / SOFT START
FAULT SIGNAL +12V
FROM MD-0788,
PAGE 3
+12V
8 D1
7 K1 +12V
D18
J4-6 J4-6 J3-10 J2-10
R45
RN7A
ROTOR
DS20 DS21
GRN RED
TO 2.1 V
9 OPTO-COUPLER
CURRENT
U24 “ON” = NO FAULT
SINK
J10-1 J1-1
BUFFER
5 1
U5
FROM
PAGE 1
4 2 J10-20 J1-20
DATA BUS
D0..D7
NOTE
REMARKS
REFERENCE
1 “HIGH” (APPROXIMATELY 6-11 VDC) = NO STATOR FAULT, “LOW” (<APPROXIMATELY 2 VDC) = STATOR FAULT (LOW OR NO STATOR CURRENT).
2 “LOW” (APPROXIMATELY 0 VDC) = NO STATOR FAULT, “HIGH” (APPROXIMATELY 12 VDC) = STATOR FAULT (LOW OR NO STATOR CURRENT).
3 “HIGH” (APPROXIMATELY 10 VDC) = PREP REQUESTED, “LOW” (APPROXIMATELY 1 VDC) = PREP NOT REQUESTED.
4 “LOW” (APPROXIMATELY 0 VDC) = BOOST REQUESTED, “HIGH” (APPROXIMATELY 12 VDC) = BOOST NOT REQUESTED (BOOST REQUESTED FOR APPROXIMATELY 1.5 SEC AFTER PREP INITIATED).
5 “LOW” (APPROXIMATELY 0 VDC) = RUN REQUESTED, “HIGH” (APPROXIMATELY 12 VDC) = RUN NOT REQUESTED (RUN REQUESTED AFTER BOOST COMPLETE, AND FOR DURATION THAT PREP IS PRESSED).
6 “HIGH” (APPROXIMATELY 12 VDC) = LOW SPEED STARTER ENABLED, “LOW” (APPROXIMATELY 0 VDC) = STARTER DISABLED (SEE # 7).
THIS POINT MUST BE “HIGH” (AS PER # 6) TO ENABLE THE LOW SPEED STARTER. THIS REQUIRES THE ENABLE COMMAND TO BE PRESENT (”HIGH”), AND THE TUBE 1 /TUBE 2 MISMATCH &THERMOSTAT
7 OPEN SIGNAL TO BE “HIGH”. IF THE 12 VDC / SOFT START FAULT SIGNAL IS LOW (INDICATING A FAULT), J1-4 WILL NOT BE PULLED LOW DUE TO THE DIODE SHOWN CONNECTED TO THIS PIN ON PAGE 1.
“LOW” (APPROXIMATELY 0 VDC) ENERGIZES K1 ON THE LOW SPEED STARTER BOARD, ENABLING THE STARTER. “HIGH” (APPROXIMATELY 12 VDC) DE-ENERGIZES K1 ON THE LOW SPEED STARTER BOARD.
8 AS PER # 6 AND 7, NO ENABLE COMMAND, OR PRESENCE OF A TUBE 1 / TUBE 2 MISMATCH & THERMOSTAT OPEN FAULT, OR A 12 VDC / SOFT START FAULT WILL INHIBIT LOW SPEED STARTER OPERATION.
9 DS20 LIT INDICATES NORMAL STATOR CURRENTS. DS 21 LIT INDICATES STATOR FAULT, OR LOW SPEED STARTER IS IN STANDBY MODE.
DRAWN DATE
G. SANWALD 10 MAR 2000 LOW SPEED
CHECKED________ ________ STARTER
DES.\MFG.\AUTH.
HTW 10 MAR 2000 MD-0764 REV G
SHEET 2 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.
CS1, U10, U11
SW1 * SW2 *
INVERTER
+5V +5V FAULT
DETECTOR
560 / 650 VDC (+)
RN7G
DS1
INVERTER
FAULT
R24
DS8 DS7
5
HS LS U17, U18
U19, U22, U24
1 TO 2.1 V IGBT IGBT
CURRENT DRIVER SWITCH SWITCH
SINK U19, U16 R40 (Q2) (Q4)
U27 CIRCUIT AND
J10-2 J1-2 2 J4-6 J1-6 FAULT
DATA BUFFER AND 1 5 CURRENT
LATCH DRIVER LATCH
J10-21 J1-21 J4-8 J1-8 U12
(U1-U10, IGBT IGBT
2 4 T1-T4, ETC). SWITCH SWITCH
(Q1) (Q3)
+12V HIGH SPEED
SELECT K4
PREP COMMAND 6
FROM MD-0761
R96
+12V 560 / 650 VDC (-)
D47 DUAL SPEED
R41 STARTER CPU,
K1 TUBE 1
Q7 BUFFERS, TB2-3 SHIFT
J4-2 J1-2 1 5 K1-A
DRIVERS K5
R94 J4-4 J1-4 U13
K2
2 4 D47 K2-A
3
Q5
PREP
R31
CONTACTOR +12V INITIATED TB2-2 MAIN
K3 K6 +12V
CLOSED K5
SIGNAL FROM R42 R32
K6 C22
MD-0788, PAGE 3 TB2-1 COMM
J4-14 J1-14 1 5
FROM MD-0788, **
SHIFT
PAGE 3 CAPACITOR E7 E6
ROTOR
ARRANGEMENT
DS20 DS21 733317-12, 13 C2 C3 C4
+12V 735925-12, 13 K7
E14
GRN RED TB3-2 MAIN
TO 2.1 V
8 OPTO-COUPLER
R1
J4-10 J1-10 K3
4 2 RN4E E5 E8 735925-15, 16, 17
J10-20 J1-20
**
K3 C1
R138 E5 E8
Q18 C1
E7 E6
K7 C3 C4
E7 E6 E14
C2 C3 C2 C5
STATOR FAULT TO K7
E14 SHIFT
GENERATOR READY
DETECTOR CIRCUIT CAPACITOR
DATA BUS ON CONTROL BOARD, ARRANGEMENT
D0..D7 SEE MD-0761 733317-01, 02
735925-01, 02
DUAL SPD DUAL SPD DUAL SPD DUAL SPD DUAL SPD DUAL SPD DUAL SPD
STARTER ASSY STARTER ASSY STARTER ASSY STARTER ASSY STARTER ASSY STARTER ASSY STARTER ASSY
733317-01 733317-02 733317-12 733317-13 733317-15 733317-16 733317-17
735925-01 735925-02 735925-12 735925-13 735925-15 735925-16 735925-17
CAPACITOR VALUE VALUE VALUE VALUE VALUE VALUE VALUE
C1 25 uF 40 uF 30 uF 25 uF 12.5 uF 25 uF 25 uF
C2 N/A N/A 30 uF 25 uF 6 uF 12.5 uF 15 uF
C3 12.5 uF 40 uF 15 uF 12.5 uF 6 uF 12.5 uF 10 uF
C4 12.5 uF 40 uF 15 uF 12.5 uF 6 uF 12.5 uF 10 uF
C5 N/A N/A N/A N/A 6 uF 12.5 uF 15 uF
C6 N/A N/A N/A N/A 12.5 uF N/A N/A
NOTE
REMARKS
REFERENCE
1 DS8 LIT INDICATES HIGH SPEED SELECTED, DS7 LIT INDICATES LOW SPEED SELECTED.
2 “HIGH” (APPROXIMATELY 5 VDC) = HIGH SPEED SELECTED, “LOW” (APPROXIMATELY 0 VDC) = LOW SPEED SELECTED.
“LOW” (APPROXIMATELY 7 VDC) = CONTACTOR CLOSED AND PREP REQUESTED. THIS INITIATES THE BOOST CYCLE. “HIGH” (APPROXIMATELY 12 VDC) = BOOST NOT REQUESTED (PREP COMMAND NOT
3 RECEIVED, OR CONTACTOR IS NOT CLOSED).
4 “LOW” (APPROXIMATELY 0 VDC) = TUBE 2 SELECTED, “HIGH” (APPROXIMATELY 12 VDC) = TUBE 2 DESELECTED. THIS CONDITION DEFAULTS TO TUBE 1.
DS1 LIT INDICATES AN INVERTER CURRENT FAULT. POSSIBLE CAUSES INCLUDE INCORRECT DIP SWITCH SETTINGS FOR THE TUBE IN USE (SEE ** ON PAGE 1), INCORRECT STATOR IMPEDANCE, OR
5
DEFECTIVE STATOR CABLE.
6 K4 OPEN CIRCUITS THE STATOR COMMON LEAD AT ALL TIMES THAT THE DUAL SPEED STARTER IS IN STANDBY MODE.
7 “LOW” (APPROXIMATELY 0 VDC) = NO STATOR FAULT, “HIGH” (APPROXIMATELY 12 VDC) = STATOR FAULT (LOW OR NO STATOR CURRENT).
8 DS20 LIT INDICATES NORMAL STATOR CURRENTS. DS21 LIT INDICATES STATOR FAULT, OR DUAL SPEED STARTER IS IN STANDBY MODE.
DRAWN DATE
G. SANWALD 30 MAR 2000 DUAL SPEED
CHECKED STARTER
STEVE BLAKE 30 MAR 2000
DES.\MFG.\AUTH.
L.FOSKIN 30 MAR 2000 MD-0765 REV E
SHEET 2 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.
NOTE
REMARKS
REFERENCE
D36 LIT INDICATES RAD OR PULSED FLUORO
REFER TO 1 MODE. D36 NOT LIT INDICATES CONTINUOUS
K1
MD-0759
PAGE 2 FLUORO MODE.
+12V
“LOW” (APPROXIMATELY 0 VDC) = K1 ON
FLUORO CONTACTOR DRIVE RESONANT BOARD ENERGIZED IN RAD / PULSED
R44
+12V
CIRCUITS 2 FLUORO MODE. “HIGH” (APPROXIMATELY 12 VDC)
D36 APPLICABLE TO R&F = K1 ON RESONANT BOARD DE-ENERGIZED IN
J2-1 J2-1 CONTINUOUS FLUORO MODE.
RAD GENERATORS ONLY
1 MODE “LOW” (APPROXIMATELY 0 VDC) = K1 ON POWER
J2-2 J2-2 K1
FROM J1-5 (AUXILIARY R79 MODE SELECT BOARD ENERGIZED IN FLUORO OR
BOARD), SEE MD-0788, Q5
PAGE 3 J2-3 2 LOW POWER RAD MODE (< 20 kW APPROX). “HIGH”
3
R47
RAD-ONLY UNITS
(APPROXIMATELY 12 VDC) = K1 ON POWER MODE
ARE FITTED WITH SELECT BOARD DE-ENERGIZED IN HIGH POWER
A JUMPER FROM RAD MODE (> 20kW APPROX).
J2-2 TO J2-3
RESONANT BOARD
AUXILIARY BOARD (R&F GENERATORS ONLY)
+12V
R239
TO INVERTER
+12V BOARD No. 3
K2
THE POWER-MODE SELECT
CIRCUIT IS USED ON 80 AND 100 KW
D106
K2 GENERATORS ONLY
D104
3
D105
FROM J8-3 (CONTROL R240
BOARD) SEE MD-0788, Q17 REFER TO
PAGE 3 MD-0759,
R241
PAGE 2
CONTROL BOARD
DRAWN DATE
G. SANWALD 21 MAR 2000 RAD / FLUORO AND
CHECKED________ ________ POWER MODE SELECT
DES.\MFG.\AUTH.
HTW 21 MAR 2000 MD-0786 REV E
SHEET 1 OF 1
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V +5V
J18-1 R126
RN5
RN5
J18-2
THERMAL SWITCH INPUT U51 U25
FOR INDICO 100 SP UNITS J18-3
(FUTURE USE) J12-5 J6-5 RN14D D4
R124
J18-4 BUFFER BUFFER J12-4 J6-4 RN14E D3
R125
+24V +24V
R123
R122
1 5 1 5
U52 U53
2 4 2 4
+12V
R39
ON OFF JUMPER POSITION:
1 2 3 R&F GENERATORS (WITH THERMAL SWITCH) +12V
JW4 NO JUMPER FITTED
RAD GENERATORS (NO THERMAL SWITCH) D42
THERMAL
R41
JUMPER JW4 PINS 2-3 (OFF) CUTOFF
4 OPEN
J2-4 R40
Q10
R43
J2-3
+12V
D26
THERMAL SWITCH ON
INVERTER HEATSINK
TUBE 1 / TUBE 2 MISMATCH &
R6
(ALL R&F UNITS) 5
THERMOSTAT OPEN SIGNAL TO
+12V MD-0764 AND MD-0761, PAGE 2
TUBE 1 / TUBE 2
TELLBACK LOGIC R7
CIRCUIT Q8
1 5
(U9, U10, R84) +5V +5V
R8
U7
RN11H
RN7H
2 4
FOR TUBE 1 / TUBE 2 INVERTER BOARD
SOLENOID DRIVE
CIRCUITS SEE TUBE 1 / TUBE 2 SELECT DS5 DS6
MD-0788, PAGE 1 1 5
SIGNAL FROM MD-0788,
U8 PAGE 3 TUBE TUBE
TUBE 1 / TUBE 2 SELECT 2 1
2 4 COMMAND FROM MD-0788,
TUBE 1 / TUBE 2 PAGE 1 U35
RELAY CONTACTS 3
(SHOWN IN TUBE D39 +12V DECODER/
J5-1 J11-1 J4-20 J4-20
1 POSITION) DEMULTIPLEXER
R28 J1-2 J8-2 J2-5 J3-5 1 5
TUBE 2
J5-2 J11-2 J4-19 J4-19 R38 SELECTED
U3
J1-1 J8-1 J2-13 J3-13
1 2 4
2
OPTO COUPLER
“ON” = TUBE 2 SELECTED
POWER INPUT
H.T. TANK BOARD AUXILIARY BOARD CONTROL BOARD GENERATOR CPU BOARD
REFER TO MD-0763 (ROOM INTERFACE) FOR INTERLOCKS ACCESSED VIA THE ROOM INTERFACE BOARD
DRAWN DATE
REFER TO PAGE 2 FOR TUBE THERMAL SWITCH CONNECTIONS AT THE STATOR TERMINAL BLOCK G. SANWALD 18 MAY 2000
INTERLOCKS &
CHECKED TUBE 1 / TUBE 2
S. BLAKE 18 MAY 2000 TELLBACK
DES.\MFG.\AUTH.
L. FOSKIN 18 MAY 2000 MD-0787 REV G
SHEET 1 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.
TUBE 1
STATOR
TERMINAL
BLOCK
J5-1 TUBE 1 THERMOSTAT TO T1
ON MD-0763, PAGE 1
THERMAL
NOTE SWITCH
REMARKS J5-2
REFERENCE
1 “LOW” (APPROXIMATELY 0 VDC) = TUBE 2 SELECTED, “HIGH” (APPROXIMATELY 10 VDC) = TUBE 1 SELECTED.
TUBE 2
2 “LOW” (APPROXIMATELY 0 VDC) = TUBE 2 SELECTED, “HIGH” (APPROXIMATELY 12 VDC) = TUBE 1 SELECTED. STATOR
TERMINAL
DS6 LIT INDICATES TUBE 1 SELECTED. DS5 LIT INDICATES TUBE 2 SELECTED. NEITHER LED LIT INDICATES A MISMATCH BETWEEN THE BLOCK
3
TUBE THAT HAS BEEN REQUESTED, AND THE TUBE THAT HAS ACTUALLY BEEN SELECTED (SEE # 5). J5-3
TUBE 2 THERMOSTAT TO T2
“LOW” (APPROXIMATELY 0 VDC) = INVERTER THERMAL SWITCH CLOSED (OR JUMPERED VIA JW4), “HIGH” (APPROXIMATELY 12 VDC) = THERMAL ON MD-0763, PAGE 1
4 INVERTER THERMAL SWITCH OPEN, OR JW4 JUMPER OMITTED ON RAD GENERATORS. SWITCH J5-4
THE TUBE 1 / TUBE 2 TELLBACK LOGIC CIRCUIT ENSURES THAT THE TUBE ACTUALLY SELECTED MATCHES THE TUBE THAT WAS
5 REQUESTED. FOR EXAMPLE, IF TUBE 2 WAS REQUESTED BY THE CONSOLE BUT TUBE 1 WAS ACTUALLY SELECTED BY THE H.T. TANK, GENERATOR INTERFACE BOARD
THE LOGIC CIRCUIT WILL INDICATE A FAULT CONDITION.
DRAWN DATE
G. SANWALD 18 MAY 2000
INTERLOCKS &
CHECKED TUBE 1 / TUBE 2
S. BLAKE 18 MAY 2000 TELLBACK
DES.\MFG.\AUTH.
L. FOSKIN 18 MAY 2000 MD-0787 REV G
SHEET 2 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.
REFER TO PAGE 10 FOR LOGIC LEVELS,
+24V +12V
NOTES, ETC, REFERENCED BY
HEXAGONAL SYMBOL: GAIN CONTROL SIGNAL
J10-13
(NOT USED AT THIS TIME)
FROM MD-0758 J10-19
J10-16
J10-11
-24V -12V
U25, U23 U33
D0 RN14H J6-1 J12-1 8 11
4 CH 4 SELECT J10-2
R88
+5V
R87
1
U28
R99
TP10
8 9
CPU R100 J7-19 J11-19
10
Q6
U45C
R86
6
PTSTOP J10-1
Q5
2
R85
TP9 TP12
R44
R42
TP11
2
J11-4 PTRAMP J10-15
U37
- 9
A/D 8
10 J7-4 TP12
CONVERTER +
3
U23C J11-1 PTREF J10-10
RN5B
+12V
R117
J10-17
3 TP4 U46
R89
4 5 +12V
R116
R30
2 1
U18 Q7
9 - 8 J7-1
D/A 10 +
CONVERTER -12V
U14C J14-6 J14-7 J14-14 J14-3 J14-1 J14-2 J14-4 J14-12 J14-13 J14-15 J14-8 J14-9 J14-10 J14-11
GENERATOR INTERFACE BOARD
DATA BUS
DO..D7
THIS INTERFACE NO
LONGER USED DRAWN DATE
G. SANWALD 02 JUN 2000
CHECKED AEC
__________ __________
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0757 REV J
SHEET 1 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+500V
TP10 LEFT +/-300V
J1-2
+/-300 V AEC CH 1
+12V +12V +12V +12V +12V
12 J11-1
JW8 H.V. J1-1
+12V 1 +/-300/+500 V
RN6C
RN6D
RN6B
RN6A
RN6E
TP22 2 J1-3
+/-300V +45V +45 V
TP24 * H.V. 3 J11-4
START J1-8
DS5 DS1 DS2 DS3 DS4 RIGHT RESET/START
J11-3
MIDDLE J1-10
RN4A JW7 M FIELD SEL
J10-2 J5-2 D6 J11-2
CHAMBER 4 SELECT CH 4 1 L/R J1-9
TP9 2 R FIELD SEL
U3C 3 J11-6
J10-3 J5-3 RN3D CONVERTER R/L J1-11
D5 L FIELD SEL
CHAMBER 3 SELECT CH 3 +12V +24V CIRCUIT J11-5
R66
12 VDC TO 45 VDC TP11 J1-12
U3B R89 CHAMBER O/P
J10-4 J5-4 D12 RN3C AND +/-300 / +500 VDC 13 J11-9
CHAMBER 2 SELECT CH 2 J1-7
+45V CH 1 GROUND
J5-5
U3F
RN3A * INCLUDES U7 AND T1
J10-5 D4
CHAMBER 1 SELECT CH 1 S1D R90
D16
U3D
J10-6 J5-6 D11 RN3B Q1
SET
R79
START STRT
VALUE 11 LEFT +/-300V
J2-2
+/-300 V AEC CH 2
U3E U3A * START J12-1
JW6 H.V. J2-1
1 +/-300/+500 V
2 J2-3
+12V +24V +12V +24V +12V +24V +45V +45 V
3 J12-4
START J2-8
RIGHT RESET/START
J12-3
MIDDLE J2-10
JW5 M FIELD SEL
J5-7
* * * 1 J12-2
L/R
J10-7 J2-9
RIGHT FIELD SELECT 2 R FIELD SEL
D30 D40 D65 3 J12-6
J10-8 J5-8 R/L J2-11
MIDDLE FIELD SELECT Q2 Q3 Q4 L FIELD SEL
J12-5
J10-9 J5-9 TP12 J2-12
LEFT FIELD SELECT * * * R67 CHAMBER O/P
RIGHT MIDDLE LEFT 13 J12-9
J2-7
CH 2 GROUND
FROM
PAGE 1 S1C R68
LEFT +/-300V
J3-2
+/-300 V AEC CH 3
TP18 J13-1
TP17 2 TP20 8 JW4 H.V. J3-1
J10-19 J5-19 CH 1 1 +/-300/+500 V
+24V J3-3
2 +45V +45 V
TP23 - STRT R1 S2A 3 J13-4
START J3-8
-
CH 2 RESET/START
J10-13 J5-13 TP5 TP6 TP7
+
S4 RIGHT
+12V + J13-3
U4A MIDDLE J3-10
J10-17 J5-17 U4B R2 S2B JW3 M FIELD SEL
R32 J13-2
C11 CH 3 1 L/R J3-9
* 2 R FIELD SEL
TP4 3 J13-6
C4 S2C R/L J3-11
R3 L FIELD SEL
J10-11 J5-11 CH 4 J13-5
-12V CH 1 R53 TP13 J3-12
TP21 -
13 R57 CHAMBER O/P
S2D J13-9
J10-16 J5-16 S3A
+ R4 J3-7
-24V CH 3 GROUND
U2B
R11 CH 2 S1B R58
TP3 3 TP19 9
TP2 10
S3B
J10-15 J5-15 R54 LEFT +/-300V
J4-2
+/-300 V AEC CH 4
PT RAMP R12 J14-1
RN4C CH 3 JW2 H.V. J4-1
J10-10 J5-10 +/-300/+500 V
PT REF 1
2 J4-3
J10-1 J5-1 S3C +45V +45 V
PT STOP 3 J14-4
START J4-8
R13 CH 4
-
RIGHT RESET/START
+12V
- J14-3
D27 MIDDLE J4-10
R56
+
+ JW1 M FIELD SEL
S3D U1A 1 J14-2
U2A L/R J4-9
RN4D
S1A R36
GENERATOR INTERFACE BOARD AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734614 DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 02 JUN 2000
CHECKED AEC
__________ __________
THE -24V OUTPUTS ON J1 TO J4 AND THE +/- 12V OUTPUTS ON J1 TO J4 DESIGNATES A FACTORY CONFIGURED LOGIC OR SIGNAL LEVEL. AEC
AND J11 TO J14 ARE NOT SHOWN ON THIS DIAGRAM. THESE ARE BOARDS ARE CONFIGURED AT THE TIME OF ORDER TO BE COMPATIBLE DES.\MFG.\AUTH.
*
DETAILED ON THE CONNECTOR PIN OUT TABLES IN CHAPTER 3D. WITH THE SPECIFIED AEC CHAMBER(S). FOR EXAMPLE, THE START
L. FOSKIN 02 JUN 2000 MD-0757 REV J
SIGNAL TO THE CHAMBER MAY BE FACTORY CONFIGURED TO BE ACTIVE
LOW (0 V), ACTIVE HIGH +12 V, OR ACTIVE HIGH +24 V. SHEET 2 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
AEC CH 1 AEC CH 3
LEFT 1 LEFT 1
SELECT SELECT
2 2
JW1 JW5
RIGHT 3 R5 RN1 RN1 RIGHT 3 R6 RN2 RN2
3 6 7 2 J1-2 3 6 7 2 J3-2
SELECT ANODE (L) SELECT ANODE (L)
2 J1-5 2 J3-5
R69 -
CATH (L) R70 - CATH (L)
1 RN1 RN1 1 RN2 RN2
3 4 5 8 1 J1-1 3 4 5 8 1 J3-1
ANODE (M) ANODE (M)
+ +
U4A U5A
U2A J1-6 U3A J3-6
CATH (M) CATH (M)
R10
R50
J1-3 J3-3
ANODE (R) ANODE (R)
J1-4 J3-4
CATH (R) CATH (R)
MIDDLE MIDDLE
SELECT J1 (shell) SELECT J3 (shell)
R13 RN7 RN7 GROUND R14 RN8 RN8 GROUND
3 6 7 2 3 6 7 2
R9 - 6 R11 - 6
7 RN7 RN7 7 RN8 RN8
+ 5 4 5 8 1 + 5 4 5 8 1
U4B U5B
U2B U3B
R7
R8
RIGHT 1 J11-5 RIGHT 1 J13-5
ANODE (L) ANODE (L)
SELECT J11-6 SELECT J13-6
2 CATH (L) 2 CATH (L)
JW2 J11-3 JW6 J13-3
3 ANODE (M) 3 ANODE (M)
LEFT R27 RN9 RN9 J11-4 LEFT R28 RN10 RN10 J13-4
3 6 7 2 CATH (M) 3 6 7 2 CATH (M)
SELECT SELECT
2 J11-1 2 J13-1
R22 - ANODE (R) R23 - ANODE (R)
1 RN9 RN9 1 RN10 RN10
3 4 5 8 1 J11-2 3 4 5 8 1 J13-2
U4C
+
CATH (R) U5C
+
CATH (R)
U8A J11-7 U9A J13-7
R16
R17
CH 1 CH 3
SELECT U4D SELECT U5D
CH 1 CH 3
OUT OUT
(NEXT PG) (NEXT PG)
AEC CH 2 AEC CH 4
LEFT 1 LEFT 1
SELECT SELECT
2 2
JW3 JW7
RIGHT 3 R43 RN11 RN11 RIGHT 3 R44 RN12 RN12
3 6 7 2 J2-2 3 6 7 2 J4-2
SELECT ANODE (L) SELECT ANODE (L)
6 J2-5 6 J4-5
R40 - CATH (L) R41 - CATH (L)
7 RN11 RN11 7 RN12 RN12
5 4 5 8 1 J2-1 5 4 5 8 1 J4-1
ANODE (M) ANODE (M)
+ +
U14A U15A
U8B J2-6 U9B J4-6
CATH (M) CATH (M)
R33
R34
J2-3 J4-3
ANODE (R) ANODE (R)
J2-4 J4-4
CATH (R) CATH (R)
MIDDLE MIDDLE
SELECT J2 (shell) SELECT J4 (shell)
R51 RN13 RN13 GROUND R52 RN14 RN14 GROUND
3 6 7 2 3 6 7 2
R47 - 2 R49 - 2
1 RN13 RN13 1 RN14 RN14
+ 3 4 5 8 1 + 3 4 5 8 1
U14B U15B
U16A U17A
R45
R46
RIGHT 1 J12-5 RIGHT 1 J14-5
ANODE (L) ANODE (L)
SELECT J12-6 SELECT J14-6
2 CATH (L) 2 CATH (L)
JW4 J12-3 JW8 J14-3
3 ANODE (M) 3 ANODE (M)
LEFT R57 RN15 RN15 J12-4 LEFT R58 RN16 RN16 J14-4
3 6 7 2 CATH (M) 3 6 7 2 CATH (M)
SELECT SELECT
6 J12-1 6 J14-1
R55 - ANODE (R) R56 - ANODE (R)
7 RN15 RN15 7 RN16 RN16
5 4 5 8 1 J12-2 5 4 5 8 1 J14-2
U14C
+
CATH (R) U15C
+
CATH (R)
U16B J12-7 U17B J14-7
R54
R53
CH 2 CH 4
SELECT U14D SELECT U15D
CH 2 CH 4
OUT OUT
(NEXT PG) (NEXT PG)
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737992. THIS DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
PAGE SHOWS THE INPUT CIRCUITS; THE SIGNAL PROCESSING THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CIRCUITS ARE CONTINUED ON THE NEXT PAGE. LOGIC LEVEL (0V = OFF, 5V = ON). G. SANWALD 02 JUN 2000
CHECKED AEC
__________ __________
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0757 REV J
SHEET 3 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V +5V +5V +5V
8 7 6 5
RN3
RN3
RN3
RN3
1 2 3 4 U6
DS4 DS3 DS2 DS1
R67 CH 1 OUT
J10-2 J5-2 2 18
CHAMBER 4 SELECT CH 4 SELECT (FROM PREVIOUS
PAGE)
J10-3 J5-3 R66 3 17
CHAMBER 3 SELECT CH 3 SELECT
+5V
R15
R36
TP1 15 R18
R59 R1
2 TP3 CH 2 6- R32
TP4 7
3 SELECT 5+
R31
C31
R26 U12B
J10-15 J5-15
R37
PT RAMP R60 R2
- 2
J10-10 J5-10 1 CH 3 CH 4 OUT
PT REF 3 SELECT (FROM PREVIOUS
+
+5V SELECT
R20
SAMPLE
R4 & HOLD
6 D37
R12
R24
TP5
D38 R30
- 3
7
+ 2
U10
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737992. THIS DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
PAGE SHOWS THE SIGNAL PROCESSING CIRCUITS; THE INPUT THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CIRCUITS ARE SHOWN ON THE PREVIOUS PAGE. LOGIC LEVEL (0V = OFF, 5V = ON). G. SANWALD 02 JUN 2000
CHECKED AEC
__________ __________
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS.
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0757 REV J
SHEET 4 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
LEFT AEC CH 1
+5V +5V +5V +5V SELECT
JW8 NO CONNECTION N/C
+5V 1
J1-2
R51
R49
R50
R52
2 LEFT/RIGHT
3 J1-6
U6 RIGHT RIGHT/LEFT
R39
DS1 DS2 DS3 DS4 SELECT MIDDLE J1-3
R61 +12V JW7 MIDDLE
J10-2 J5-2 2 18 SELECT
CHAMBER 4 SELECT +12V
CH 4 SELECT START/ 1 J1-4
START RESET/START
2
R62 R40 D12 3 TP1 J1-8
J10-3 J5-3 3 17 Q5 +12V
CHAMBER 3 SELECT CH 3 SELECT 13
R1 J1-5
START CHAMBER O/P
J10-4 J5-4 R63 4 16
CHAMBER 2 SELECT CH 2 SELECT R38 CH 1 J1-7
Q4 SELECT -12V
J10-5 J5-5 R64 5 15 J1-9
CHAMBER 1 SELECT GROUND
CH 1 SELECT U1D R2
INVERTING -12V
BUFFER
LEFT AEC CH 2
SELECT
J10-6 J5-6 D20 6 14 JW6 NO CONNECTION N/C
START
R66 1
J10-7 J5-7 7 13 J2-2
RIGHT FIELD SELECT 2 LEFT/RIGHT
R67 3 J2-6
J10-8 J5-8 8 12 RIGHT/LEFT
MIDDLE FIELD SELECT RIGHT
J10-9 J5-9 R68 9 11 SELECT MIDDLE J2-3
LEFT FIELD SELECT JW5 MIDDLE
SELECT
+12V
1 J2-4
START RESET/START
2
+12V +12V +12V 3 TP2 J2-8
13 +12V
R3 J2-5
CHAMBER O/P
+12V +5V D11 D10 D9
CH 2 J2-7
R37
R36
R35
U3 LEFT MIDDLE RIGHT SELECT -12V
SELECT SELECT SELECT J2-9
+5 V GROUND
FROM U1C R4 -12V
REGULATOR Q3 Q2 Q1
PAGE 1
J10-13 J5-13
LEFT AEC CH 3
SELECT
TP11 TP12 JW4 NO CONNECTION N/C
1
J10-17 J5-17 J3-2
2 LEFT/RIGHT
TP7 8 CH 1 SELECT 3 J3-6
RIGHT RIGHT/LEFT
J10-11 J5-11 SELECT MIDDLE J3-3
-12V - R11 JW3 MIDDLE
CH 2 SELECT SELECT
START/ +12V
+
1 J3-4
START RESET/START
U4A 2
R12 3 TP3 J3-8
CH 3 SELECT 13 +12V
* R5 J3-5
CHAMBER O/P
R13 CH 3
CH 4 SELECT J3-7
SELECT -12V
- J3-9
R14 GROUND
TP9 2 TP8 + U1B R6 -12V
3 U8B
R31
+ MIDDLE J4-3
JW1 MIDDLE
R69
R34
+
SELECT
U7A +12V
U8A 1 J4-4
START/ START RESET/START
6 2
D25 3 TP4 J4-8
R33 +12V
TP10 13
R7 J4-5
CHAMBER O/P
D27 3
7
-
SAMPLE CH 4 J4-7
+ 2 & HOLD SELECT -12V
U9 J4-9
GROUND
U1A R8 -12V
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737998 DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 02 JUN 2000
CHECKED AEC
__________ __________
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0757 REV J
SHEET 5 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+12V +12V +45V TP4
+500V
AEC CH 1
J1-3 J5-3 +12V J1-1
U1E U1F +300V +500V +500 V
J1-19 J1-19 J1-2
R22 R47 +300V +300 V
R31
J1-15 J1-15 +12V J1-3
+45V +45 V
J1-17 J1-17 J1-4
R27
+12V +12 V
J1-1 J5-1 J1-5
-12V -12 V
16 J1-6
R15
+12V J1-4 J5-4
R32
-24V -24 V
+12V +12V +12V +12V J1-7
-12V J1-2 J5-2 -12V TP3 GND
6-
7 J1-8
R23
-24V -24V R28 5+ FEEDBACK RESET/START
D45 D46 D47 START 1
R16
R18
R20
R21
J1-9
U1B RIGHT 1 RIGHT
CONVERTER CIRCUIT J1-10
U1D 12 VDC TO 45 VDC, MIDDLE 1 MIDDLE
CH 4 300 VDC, 500 VDC, J1-11
J10-2 J5-2 D44 AND -1000 VDC LEFT 1 LEFT
CHAMBER 4 SELECT D43 J1-12
U1C SIGNAL 1 CHAMBER O/P
CH 3 INCLUDES U3, Q1-Q4,
U2C
U2D
U2A
J10-3 J5-3 D37 TO D1-D6, D12-D21,
CHAMBER 3 SELECT D42
U1B SHT 8 AND T1 AEC CH 2
CH 2
J10-4 J5-4 D38 5.1V REFERENCE J2-1
CHAMBER 2 SELECT D41 +500V +500 V
U1A J2-2
CH 1 +300V +300 V
R19
R10
R24
J10-5 J5-5 D39 J2-3
CHAMBER 1 SELECT D40 +45V +45 V
J2-4
+12V +12 V
+12V J2-5
-1000V -12V -12 V
J2-6
-24V -24 V
J2-7
R14
START 1~ J2-1 J6-1 GND
START 1
D36 NEXT PG. J2-8
J2-3 J6-3 START 2 RESET/START
J10-6 J5-6 TO START RIGHT 1_ RIGHT 1 J2-9
START RIGHT 2 RIGHT
SHT 8 FROM J2-5 J6-5
MIDDLE 1_ MIDDLE 1 J2-10
SHT 7 J2-7 J6-7 MIDDLE 2 MIDDLE
+12V +24V LEFT 1_ J2-11
LEFT 1
LEFT 2 LEFT
J2-9 J6-9 J2-12
SIGNAL 1_ TO SHT 8 SIGNAL 1 SIGNAL 2 CHAMBER O/P
R29*
R90*
START 2~ J2-11 J6-11
START 2
NEXT PG. J2-13 J6-13
RIGHT 2_ RIGHT 2 AEC CH 3
R42 FROM J2-15 J6-15
FROM MIDDLE 2_ MIDDLE 2 J3-1
PAGE 1 D69* SHT 7 +500V +500 V
R43 J2-17 J6-17 J3-2
LEFT 2_ LEFT 2 +300V +300 V
Q4 J3-3
J2-19 J6-19
SIGNAL 2_ TO SHT 8 SIGNAL 2 +45V +45 V
D34 TO AEC INPUT J3-4
START 3~ J2-2 J6-2 +12 V
J10-15 J5-15 START 3 CONNECTORS J1 -J4 +12V
PT RAMP NEXT PG. J3-5
JW29 J2-4 J6-4 -12V -12 V
J10-10 J5-10 FROM RIGHT 3_ RIGHT 3 J3-6
PT REF D33 FROM J2-6 J6-6 -24V -24 V
SHT 8 JW30 MIDDLE 3_ MIDDLE 3 J3-7
J10-1 J5-1 SHT 7 GND
PT STOP J2-8 J6-8
LEFT 3_ LEFT 3 J3-8
D22 START 3 RESET/START
J2-10 J6-10 J3-9
SIGNAL 3_ TO SHT 8 SIGNAL 3 RIGHT 3 RIGHT
JW31 START 4~ J2-12 J6-12 J3-10
J10-19 J5-19 START 4 MIDDLE 3 MIDDLE
+24V D24 NEXT PG. J2-14 J6-14 J3-11
JW32 RIGHT 4_ RIGHT 4 LEFT 3 LEFT
J3-12
TP1 FROM J2-16 J6-16 SIGNAL 3 CHAMBER O/P
MIDDLE 4_ MIDDLE 4
J10-13 J5-13 TP2 D26 SHT 7 J2-18 J6-18
+12V LEFT 4_ LEFT 4
J10-17 J5-17 JW33 J2-20 J6-20 AEC CH 4
SIGNAL 4_ TO SHT 8 SIGNAL 4
D28 J4-1
JW34 +500V +500 V
TP5 J4-2
+300V +300 V
J10-11 J5-11 J4-3
-12V D30 +45V +45 V
J4-4
+12V +12 V
J10-16 J5-16 JW35 J4-5
-24V D32 -12V -12 V
JW36 J4-6
-24V -24 V
J4-7
TP5 GND
J4-8
START 4 RESET/START
-1000V J4-9
RIGHT 4 RIGHT
J4-10
MIDDLE 4 MIDDLE
J4-11
LEFT 4 LEFT
J4-12
SIGNAL 4 CHAMBER O/P
GENERATOR INTERFACE BOARD AEC BOARD J7-1 J7-2 J7-3 J7-4 AEC INTERFACE BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734654, WHICH DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
CONSISTS OF AEC INTERFACE BOARD 728399 AND AEC BOARD SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 02 JUN 2000
734630. THE AEC BOARD CIRCUITS ARE CONTINUED ON PAGES CHECKED AEC
__________ __________
7 AND 8.
* NOT FITTED ON ALL MODELS. REFER TO SUP734654 IN THE FRONT OF DES.\MFG.\AUTH.
THIS MANUAL FOR DETAILS
L. FOSKIN 02 JUN 2000 MD-0757 REV J
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS.
SHEET 6 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
J10-7 J5-7
RIGHT FIELD SELECT
FROM J10-8 J5-8
MIDDLE FIELD SELECT
PAGE 1
J10-9 J5-9
LEFT FIELD SELECT +12V +24V +12V +24V +12V +24V
R29*
R29*
R29*
R90*
R90*
R90*
R28 R26 R27
R9 R8 R5
Q2 Q1 Q3
D31 D9 D17
D20 D2 D10
D27 D6 D15
R12 R6 R10
2- 6- 2- 6-
JW47 R88, R67 1 S/S OUT 1 JW52 R74, R46 7 S/S OUT 2 JW57 R73, R80 1 S/S OUT 3 JW62 R87, R54 7 S/S OUT 4
START 1~ 3+ SHT 8 START 2~ 5+ SHT 8 START 3~ 3+ SHT 8 START 4~ 5+ SHT 8
SHT 6 U6A SHT 6 U6B SHT 6 U14A SHT 6 U14B
R38
R44
R68
R59
GENERATOR INTERFACE BOARD AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734654, WHICH DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
CONSISTS OF AEC INTERFACE BOARD 728399 AND AEC BOARD SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 02 JUN 2000
734630. THE AEC BOARD CIRCUITS ARE CONTINUED ON PAGES CHECKED AEC
__________ __________
6 AND 8.
* NOT FITTED ON ALL MODELS. REFER TO SUP734654 IN THE FRONT OF DES.\MFG.\AUTH.
THIS MANUAL FOR DETAILS
L. FOSKIN 02 JUN 2000 MD-0757 REV J
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS.
SHEET 7 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
START
FROM SHT 6 R50E R52 JW43
R50A
R36 U4C
R50F
R50B - 6
- 6 7
JW2 C4 7 5 JW44 R86
+ 5
+
SIGNAL 1_
R1 R50D START R50G JW45 FROM SHT 6
U7B
R41
U5B FROM SHT 6
R37
JW3 R45
- 2 JW46 S/S OUT 1
R50C
1
R50H
CH 1 3 FROM SHT 7
D51
+
R91
C48
START
R118 FROM SHT 6 R51A R75 JW48
R51E
R114 R58 U4D
R51B
R116 2 R51F - 6
6 1
-
- 6 7
7
-
3 JW39 C12 7 5 JW49 R85
+
5
+
SIGNAL 2_
5 +
R51H FROM SHT 6
+
R2 START U11B R51C JW50
R39
U18A
U10B FROM SHT 6
R31
U18B JW40 R49
- 2 JW51 S/S OUT 2
R51G
1
R51D
CH 2 3 FROM SHT 7
D56
+
R92
START
FROM SHT 6 R70A R71 JW53
R70E
R76 U12C
R70B
R70F - 6
+12V 2 - 6 7
JW37 C14 7 5 JW54 R84
5
+
SIGNAL 3_
3 TP4 R3
+
R70H START FROM SHT 6
U8B R70C JW55
R56
U9B
R25
FROM SHT 6
R30
TP3 JW38 R72
2
- JW56 S/S OUT 3
R70G
1
R70D
R53 CH 3 3 FROM SHT 7
D59
+
PT RAMP FROM SHT 6 U12A
R17 U8A
TO R98 R33 2
PT REF 1
-
C19
SHT 6 + 3
PT STOP C33 U3C
R97 U9A R55 +12V
R93
R106
D49 START
R24
FROM SHT 6 R82A R81 JW58
R82E
R19 R77 U12D
3
7
-
R82B
2 R82F - 6
+
- 6 7
JW41 C15 7 5 JW59 R83
SIGNAL 4_
R22
+
U2 + 5
D50 R4 R82H START R82C JW60 FROM SHT 6
U15B
R63
U13B FROM SHT 6
R79
JW42 R61
- 2 JW61 S/S OUT 4
R82G
1
R82D
CH 4 3 FROM SHT 7
D65
+
AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734654, WHICH DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CONSISTS OF AEC INTERFACE BOARD 728399 AND AEC BOARD LOGIC LEVEL (0V = OFF, 12V = ON). G. SANWALD 02 JUN 2000
734630. THE AEC BOARD CIRCUITS ARE CONTINUED ON PAGES CHECKED AEC
__________ __________
8 AND 9.
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0757 REV J
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS.
SHEET 8 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V LEFT +12V
+5V +5V AEC CH 1
+12V JW8
1 J1-8
+12 V
R39
2
R49
R50
D29 3 J1-2
LEFT/RIGHT
U6 STRT RIGHT J1-6
DS1 DS2 INVERTED RIGHT/LEFT
R40 JW7
J10-2 J5-2 R61 2 18 R71 Q5 J1-4
CHAMBER 4 SELECT Q7 1 START RESET/START
+12V +12V 2 J1-3
R62 3 MIDDLE MIDDLE
J10-3 J5-3 3 17
CHAMBER 3 SELECT J1-11
D28 D12 13 TP1 PORTRAIT PORTRAIT
J10-4 J5-4 R63 4 16 J1-13
CHAMBER 2 SELECT CH 2 INVERTED INVERTED
PORTRAIT START CH 1
R2 R1 J1-5
R64 R70 R38 CHAMBER O/P
J10-5 J5-5 5 15 Q6 Q4 U1D
CHAMBER 1 SELECT CH 1 J1-7
INVERTING -12 V
BUFFER J1-9
GROUND
-12V
J10-6 J5-6 D20 6 14
START
J10-7 J5-7 R66 7 13 LEFT +12V
RIGHT FIELD SELECT AEC CH 2
J10-8 J5-8 R67 8 12 JW6
MIDDLE FIELD SELECT 1 J2-8
R68 +12 V
J10-9 J5-9 9 11 2
LEFT FIELD SELECT 3 J2-2
LEFT/RIGHT
+12V +12V +12V
RIGHT J2-6
RIGHT/LEFT
JW5
D11 D10 D9 J2-4
1 START RESET/START
R37
R36
R35
J10-19 J5-19 2 J2-3
+24V LEFT MIDDLE RIGHT 3 MIDDLE MIDDLE
J2-11
J10-13 J5-13 Q3 Q2 Q1 13 TP2 PORTRAIT PORTRAIT
+12V TP11 TP12 J2-13
FROM INVERTED INVERTED
J10-17 J5-17 CH 2
PAGE 1 R4 R3 J2-5
CHAMBER O/P
U1C J2-7
J10-11 J5-11 -12 V
-12V
J2-9
GROUND
J10-16 J5-16 -12V
-24V 8 TP7
STRT
R11 S2B
TP8 2 CH 1
TP9 3
U2A
J10-15 J5-15 R30 R12
PT RAMP CH 2
J10-10 J5-10 R32 -
PT REF U2B
+ R4
U8B
TP6 9
+5V TP5 10
R69
-
-
J10-1 J5-1 +
PT STOP +
U4A
U4B -
D27
-
+12V +
+
U7A
D25 R33 U8A STRT
R34
R31
- 3
7
+ 2
SAMPLE
U9 & HOLD
TP10 6
GENERATOR INTERFACE BOARD AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 739389 DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 02 JUN 2000
CHECKED AEC
__________ __________
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0757 REV J
SHEET 9 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
NOTE
REMARKS
REFERENCE
1 “HIGH” (APPROXIMATELY 5 VDC) = NO PTSTOP (PHOTOTIMER STOP) SIGNAL RECEIVED FROM AEC BOARD. “LOW” (APPOXIMATELY 0 VDC) = PTSTOP SIGNAL RECEIVED FROM AEC BOARD.
2 AEC RAMP. THIS IS A SIGNAL RAMPING FROM 0 TOWARD +10 VDC. THE ACTUAL MAGNITUDE WILL DEPEND ON THE AEC TECHNIQUE.
3 AEC REFERENCE VOLTAGE, 0 TO +10 VDC, DEPENDING ON AEC TECHNIQUE. THE LENGTH OF THE AEC EXPOSURE IS PROPORTIONAL TO THE AEC REFERENCE VOLTAGE.
4 “HIGH” (> 10 VDC) = AEC CHANNEL DESELECTED, “LOW” (APPROXIMATELY 0 VDC) = AEC CHANNEL SELECTED.
5 “HIGH” (> 10 VDC) = L, M, R, FIELD DESELECTED, “LOW” (APPROXIMATELY 0 VDC) = L, M, R, FIELD SELECTED.
6 “HIGH” (> 10 VDC) = NO AEC STOP REQUEST (INSUFFICIENT RAMP TO TERMINATE AEC EXPOSURE), “LOW” (APPROXIMATELY 0 VDC) = AEC STOP REQUESTED (AEC EXPOSURE TERMINATED).
7 “HIGH” (> 10 VDC) = AEC START NOT REQUESTED, “LOW” (APPROXIMATELY 0 VDC) = AEC START REQUESTED.
8 THE VOLTAGE AND MAGNITUDE OF THE RAMP AT THIS POINT SHOULD BE APPROXIMATELY THE SAME AS THE PT RAMP OUTPUT, NOTE REFERENCE 2 .
9 THIS WILL BE A NEGATIVE DC VOLTAGE OR RAMP, DEPENDING ON AEC CHAMBER OUTPUT. THE MAGNITUDE OF THE DC VOLTAGE OR RAMP IS DEPENDENT ON THE AEC TECHNIQUE IN USE.
10 THIS WILL BE A POSITIVE DC VOLTAGE OR RAMP, DEPENDING ON AEC CHAMBER OUTPUT. THE MAGNITUDE OF THE DC VOLTAGE OR RAMP IS DEPENDENT ON THE AEC TECHNIQUE IN USE.
11 R79 ADJUSTS THE +45V, +300V, AND +500V OUTPUTS FROM THE DC TO DC CONVERTER CIRCUIT. REFER TO CHAPTER 3D FOR DETAILS.
12 THE VOLTAGE AT TP22 SHOULD BE APPROXIMATELY AS SHOWN IN FIGURE 1 (BELOW). THE MAXIMUM DUTY CYCLE WILL BE APPROXIMATELY 45%, DEPENDING ON THE LOAD ON THE HV SUPPLIES.
13 THE VOLTAGE AT THIS TEST POINT IS THE OUTPUT OF THE AEC CHAMBER. REFER TO THE AEC CHAMBER MANUFACTURERS DOCUMENTATION FOR DETAILS.
14 THIS WILL BE A POSITIVE DC VOLTAGE. THE MAGNITUDE OF THE DC VOLTAGE IS DEPENDENT ON THE AEC TECHNIQUE IN USE.
15 THIS IS THE START SIGNAL. “HIGH” (5 VDC) = START = ANALOG SWITCHES CLOSED, “LOW” (0 VDC) = START = ANALOG SWITCHES OPEN.
16 THIS WILL BE A VOLTAGE BETWEEN 0 AND 5.1 V, DEPENDING ON THE SETTING OF THE ACTIVE POTENTIOMETER R10, R19, OR R24..
200 kHz
12 VDC
0 VDC
FIGURE 1
DRAWN DATE
G. SANWALD 02 JUN 2000
CHECKED AEC
__________ __________
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0757 REV J
SHEET 10 OF 10
Use and disclosure is subject to the restrictions on the title page of this CPI document.
“DIGITAL IMAGING” ABS
FROM MD-0767, PAGE 1
1
JW12 * R62 TP13 TP15
R65 R27 JW23
JW21 *
1
JW26 *
JW4 * C19
R58
R54
1 2
R120 R63 2 R42 R52 U37
2 - 1 3
D13
3
JW11 * 3 R121 R64
+ R45 6 R41 13 - R56 SAMPLE AND HOLD
- 7 9 14 A/D
U17A - J11-3 J7-3 CIRCUIT (U47,
5 +
8 12 + CONVERTER
4 10 R95, C102, ETC.)
JW27 * +
R44
U17B U23D
U17C
RN5A
R51
R31
+12V
R61
J7-4
JW24 JW25
J7-10 R118 TP8
PMT / PHOTO DIODE / (IN) (OUT)
PROPORTIONAL DC J7-5 C22 1
VIDEO INPUT &
AEC OUTPUT J7-7 TP9
-12V
CONTROL SIGNALS
R50
J7-12 FROM DATA BUS DIGITAL
ADDRESS REGISTERS POTENTIOMETER
(U24, U25)
1 U49 TP14
DATA BUS
J8 D0..D7
COMPOSITE VIDEO 2
JW19 *
INPUT 3 R49
C21 R47
13 - D11 U34
14
R28
R46
DRAWN DATE
G. SANWALD 16 MAY 2000
ABS
CHECKED
(AUTOMATIC BRIGHTNESS
KVR 16 MAY 2000 STABILIZATION)
DES.\MFG.\AUTH.
L. FOSKIN 16 MAY 2000 MD-0758 REV E
SHEET 1 OF 1
Use and disclosure is subject to the restrictions on the title page of this CPI document.
J1-1 J2-1
J1-2 J2-2
J1-3 J2-3
J1-4 J2-4
+5V +5V
J1-5 J2-5
J1-6 J2-6
DS15 DS19 J1-7 J2-7
LS1 J1-8 J2-8 LED
TXD RXD
J1-9 J2-9 DISPLAYS
(7 SEGMENT
R43
R46
GENERATOR CPU BOARD REMOTE FLUORO CONTROL BOARD REMOTE FLUORO DISPLAY BOARD KEYBOARD ASSEMBLY
LIMITED TROUBLESHOOTING CAN BE PERFORMED ON THE REMOTE FLUORO CONTROL ASSEMBLY IN THE FIELD. THE DC RAILS CAN BE CHECKED (REFER TO MD-0788),
AND THE TXD AND RXD LEDs ON THE GENERATOR CPU BOARD MAY BE OBSERVED (THESE WILL FLASH ON AND OFF TO INDICATE DATA FLOW). MEANINGFUL MEASUREMENTS
CANNOT BE MADE ON COMMUNICATIONS, DATA, AND CONTROL LINES.
DRAWN DATE
G. SANWALD 02 JUN 2000 REMOTE FLUORO
CHECKED _________ _________ CONTROL
DES.\MFG.\AUTH.
L. FOSKIN 02 JUN 2000 MD-0766 REV D
SHEET 1 OF 1
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+24V +15V +5V
J13-11
J13-13
J13-17
J13-15
-15V
6 4
5 DS40
SYNC 3
U45B
3 1 R97 J7-15 J11-15 2
2 JW22
5 1 1
U45A
U28 3 U51
JUMPER POSITION:
2 4 2 INTERNAL (LINE SYNC)
CPU JW3 LINE SYNC FROM JUMPER PINS 1-2
1 MD-0788, PAGE 4 EXTERNAL (DIGITAL IMAGING SYNC)
JUMPER PINS 2-3
JUMPER POSITION:
INVERTED SYNC J13-9
JUMPER PINS 1-2
NON-INVERTED SYNC J13-21
JUMPER PINS 2-3
DATA, ADDRESS, J13-23
AND CONTROL BUS
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
DES.\MFG.\AUTH.
L. FOSKIN 17 MAY 2000 MD-0767 REV M
SHEET 1 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V +15V +24V
J1-11
J1-13 J3-7
J1-17
J3-1
J1-15
J3-3
TP1 TP2
-15V U7
+24V
R2 J2-20
J1-20
MUX R3 J2-21
R11
+24V J3-9
J1-14
1 5
R1
U16
3 +24V +24V +24V +24V +24V +24V +24V
2 4
5 1 J3-10
2
U3B JW1 U10 F1 J2-1
R10
R12
R13
R14
R15
R16
4 6 1
J1-19 5 4 2 +24V
DS4 DS6 DS7 DS8 DS9 DS10
FROM
R17
PAGE 1 EXON PFL HCF PREP GEN TOMO
J1-1 U4 U6 J3-5
READY
J1-2 J2-7
1 5
J1-3
J1-4 J2-3 U14
R6
R7
J2-9
BUFFER 5 1 DS1
J1-9 U13
OFL
J1-21 4 2 +24V
+24V
J1-23
R5
U9 SW1
R8
J2-23
5 1 DS2
BUFFER U12
STOP J2-2
4 2 EXP. +24V
+24V J2-10
R4
J2-12
R9
5 1 DS3
U11
O.EXP
4 2
J2-11
R9
D3 U17
12 U10D 11 J2-19
J1-19 MONOSTABLE
13 TIMER J2-18
D4 J2-20
U14 U16
J2-14
J1-1
J2-12
J1-2
J2-10
J1-3
J2-8
J1-4 DATA
DRIVER J2-6
J1-5 LATCH
J2-4
J1-6 ADDRESS DECODER +24V +24VR
J2-2
J1-7 CIRCUITS
(U1, U2, U9, U10C)
J1-8
R15
J1-10
U13 U15 R13 J3-34
J1-12 Q2 J2-23
J1-16 J3-32
J1-18 J3-30
D1 J3-28
DATA DRIVER J3-26
LATCH
J3-36
FROM
PAGE 1
+24V +24VR
+24VR +24VR +24VR
U12
R14
R12
J1-9 Q3
BUFFER 5 1 R1 5 1 R2 5 1 R3 J2-16
J3-47
J1-21 J2-22
U3 U4 U5
J1-23 D2
4 2 4 2 4 2 J3-41
J3-39
U11 SW1
J3-37
J3-38
BUFFER J3-40
J3-42
J3-44
5 1 R4 5 1 R5 5 1 R6 J3-46
U6 U7 U8
4 2 4 2 4 2 J2-15
+24VR
J3-45
J3-43
R16
J2-24
J1-22 J3-48
J1-20 J2-21
R9
D3 U17
12 U10D 11 J2-19
J1-19 13
MONOSTABLE GENERATOR INTERFACE BOARD.
TIMER J2-18
D4 J2-20
U14 U16
J2-14
J1-1
J2-12
J1-2
J2-10
J1-3 J4-1 J5-3
J2-8
J1-4 DATA *
DRIVER J2-6 J4-2 J5-7
LATCH
J1-5
J2-4 *
J1-6 ADDRESS DECODER +24V +24VR J4-4 J5-2
J1-7 CIRCUITS
J2-2 *
(U1, U2, U9, U10C) J4-5 J5-8
J1-8 *
R15
J1-10 J4-7 PREP SW ** J5-5
J1-12 U13 U15 R13 J3-34 J2-23
FROM J4
Q2
J3-32 GENERATOR J4-8 X-RAY SW **
J1-16
J1-18 J3-30 INTERFACE J4-10 “ON” SW ***
D1 J3-28 BOARD
DATA DRIVER J3-26
J4-11 “OFF” SW ***
LATCH
J3-36 J4-12 COMMON***
J4-3
+24V +24VR J4-9
**
+24VR +24VR +24VR
U12
R14
R12
J1-9 Q3
BUFFER 5 1 R1 5 1 R2 5 1 R3 J2-16
J3-47
J1-21 J2-22
U3 U4 U5
J1-23 D2
4 2 4 2 4 2 J3-41
FROM J3-39
PAGE 1 U11 SW1
J3-37
J3-38
BUFFER J3-40
J3-42
J3-44
5 1 R4 5 1 R5 5 1 R6 J3-46 +15V
U6 U7 U8
4 2 4 2 4 2 J2-15 J6-1
+24VR
J3-45 J6-2
J3-43
J6-3
R16
J2-24
J7-2 J6-9
J6-10
J7-3
J6-13
J7-1 TO MINI-CONSOLE X-RAY
EXPOSURE INDICATOR. J6-5
J7-4
(SHEET 5) J6-14
J7-5
U18 U19
J7-7
DATA
DRIVER
LATCH
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 735921. DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL CHECKED INTERFACE
KVR 17 MAY 2000
FOR DETAILS REGARDING THE CONNECTIONS TO J2, J3, J5.
DES.\MFG.\AUTH.
L. FOSKIN 17 MAY 2000 MD-0767 REV M
SHEET 4 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
J1-1
J1-4
J1-6
J1-3
J1-5
J1-7
FROM J6 J1-8
(SHEET 4)
J1-9
J1-10
ON
OFF
J1-13
J1-11 J2-1
J2-2
J1-12
HAND
PREP J2-3 SWITCH
(OPTIONAL)
X-RAY
J1-14 J2-4
J3-2
RAD FLUORO
EXP EXP
LS1 LS2
FROM J7
(SHEET 4) J3-1
J3-5
J3-7
J3-4
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
THE OPTIONAL “X-RAY MINI CONSOLE” AND OPTIONAL “MINI CONSOLE X-RAY EXPOSURE INDICATOR” CHECKED INTERFACE
ARE TYPICALLY USED WITH DIGITAL IMAGING SYSTEMS THAT HAVE INTEGRATED GENERATOR KVR 17 MAY 2000
DES.\MFG.\AUTH.
CONSOLE CONTROL FUNCTIONS. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 5 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+24V
F1 J2-14
+5V +15V +24V +5V(A)
J1-11 U12
J1-13 +5 V J2-21
REGULATOR
J1-17
+15V J2-8
J1-1
1 5
J1-2
GENERATOR U7 +15V J2-22
J1-3
U4 U6
READY
J1-4 2 4 1 5
DS4
J1-5 EXPOSURE IN U10
R2 PROCESS (EIP)
J1-6 ADDRESS DECODER 2 4
J1-7 CIRCUITS DATA DS3
FROM (U1, U2, U3A, U5A) DRIVER
LATCH R1 J2-11
PAGE 1 J1-8
J1-10 +24V J2-13
J1-12
J1-16
R9
J1-18
X-RAY
DS2 J2-15
R8
J1-14
J2-4
R6
5 1
J3-1
U16
J2-5
R7
4 2
J3-4
U8 5 1 J2-6
U14 J3-3
J1-9
4 2 J2-16
J1-21 J3-10
BUFFER
J1-23 5 1 J2-18
U15 J3-11
+5V(A) 4 2 J2-17
U9 SW1
5 1
J2-19
EXPOSE
U11
+24V RDY
BUFFER 4 2 J3-12
DS5
5 1
R3
U13 J2-9
4 2 DS1 J2-12
R4 R5 PREP
F1 J2-13
J1-17 J2-5
J4-3
J2-6
J4-2
+15V J2-20
J4-5
1 5 +15V J2-24
J1-1 U10
1 5 +15V J2-22
J1-2 U6 2 4
DS3 U7
J1-3 U4 1 5 +15V J2-21
R1 2 4
J1-4 DS4 U13
1 5 +15V J2-23
J1-5 R2 2 4
J1-6 DATA DS7 U14
ADDRESS DECODER DRIVER 1 5
J1-7 CIRCUITS LATCH R7 2 4
FROM (U1, U2, U3A, U5A) DS8 U15
PAGE 1 J1-8
R8 2 4
J1-10 DS9 J2-1
J1-12 J3-2
R9
J1-16 J2-2
12
J1-18 9 11 DS3 EXPOSURE IN PROCESS (EIP) J3-1
8 13
10
U3D DS4 GENERATOR PREPPED J2-3
U3C
DS7 RAD HANGMODE J3-4
J1-19
DS8 BUCKY START J2-4
J3-5
DS9 X-RAY ON
J2-11
J3-6
U8 J2-15
J3-8
J1-9
J2-16
J1-21
BUFFER J3-7
J1-23
J2-17
J3-12
J2-18
U9 SW1
J3-11
+24V
J2-19
BUFFER 5 1
J3-10
U11
+24V
4 2 DS5 J2-10
5 1 R3 R4 BUCKY IN MOTION
U12
4 2 DS6 J2-25
R5 R6 SPARE INPUT
R77
SELECT TABLE STEPPING J3-24
J2-24
R78 * DS3 SELECT STEP DIRECTION J3-6
Q1 J2-25
DRIVER DS46 DRIVER * DS5 TOMO TIME SELECT 0 J3-25
R72
TOMO TIME SELECT 1 * DS7 J3-7
D3 TOMO TIME SELECT 2 * DS10 J3-26
* DS12
J3-34
J3-35
J3-36
J2
J3-37
-1
+15V
1
0
3
-1
-3
-3
-2
-1
-3
U
U
J2
J3
J3
J2
J2
J3
1
1
D1
R63 DS2 DS9 DS44 DS42 DS15
J1-20
5 1 5 1 5 1 5 1 5 1
D2 U4 TABLE X-RAY U6 TABLE FLUORO U15 READY ACQUIRE U13 READY ACQUIRE U8 TABLE PREP +24V
REQUEST REQUEST FLUORO RAD/CINE/HCF REQUEST
4 2 4 2 4 2 4 2 4 2 R30 K1
-15V
J1-14
J1-9 5 1 5 1 5 1 5 1
J5-1
J1-21 U5 U7 U16 U14 24V FROM
ROOM INTERFACE J5-3
J1-23 4 2 R17 4 2 R25 4 2 R69 4 2 R68 J3-18
J3-19
SHEET 8 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V +15V +24V
J1-11
+5V
J1-13
DS1 +15V
JW103
J1-17 J7-2
XRAY ON X-RAY ON TO PAGE 10
J7-3 +15V
R10
U10 J6-1
6 J2-20 (-) J7-1
U3C J6-2
U7 U3B 9 8 4
4 J7-4
12 U3D 11 6 10 DRIVER 7 J2-19 (+) J6-5
J1-19 MONOSTABLE 5 J7-5
13 TIMER J6-14
J7-7
U17 U18
J6-3
J1-1
J6-4
J1-2
J6-6
J1-3
J6-7
J1-4 DATA
DRIVER J6-8
J1-5 LATCH
J1-6 ADDRESS DECODER
J1-7 CIRCUITS JW101 J4-10
(U1, U2, U3A, U5)
J1-8 X-RAY RQST TO PAGE 10 J6-9
J1-10
J4-11
J1-12 U13
U4 6 J2-17 (+) J6-10
J1-16
4
J1-18 DRIVER 7 J2-18 (-) J4-7
DATA J6-11
U11
LATCH 6 J2-13 (+)
4 J4-8
FROM DRIVER 7 J2-14 (-) J6-12
PAGE 1
R8
R6
J4-12
U12
U6 6 J2-15 (+) J6-13
XRAY DS4 DS2 PREP
4
DRIVER 7 J2-16 (-) J4-3
DATA U14 J4-9
LATCH 6 J2-21 (+)
4
J1-9 DRIVER 7 J2-22 (-)
J1-21
R7
R9
J1-23 U8
GENRDY DS3 DS5 *
J2-1 (+)
U15 J4-1
BUFFER 6 J5-3
1
R4
DRIVER 7 J4-2
J2-2 (-) J5-7
R5
J4-5
BUFFER
DS6 * XRAYEN J5-8
+5V
R12
J2-25 (+) J5-5
5 1
R11
U16
4 2 J2-26 (-)
Q1 JW102
X-RAY EN FROM PAGE 10
* THE INPUTS / OUTPUTS MARKED “*” ARE SPARE, AND HAVE NOT BEEN ASSIGNED DIGITAL I/O BOARD
SHEET 9 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+24V_EXT +24V_EXT +24V_EXT
+24V_EXT
R112
R110
R111
+5V
R102
DS101 DS102 DS103
R101
1 5
U103
2 4 +24V_EXT +24V_EXT
J101-5
U101 +5V
R107
1 2 EXP_ACQ J101-2
X-RAY RQST
R105
EXP_END J101-6 TO DIGITAL
FROM SYSTEM
PAGE 9 4 U104
EXP_REQ J101-8
3 DATA 5 2 MONOSTABLE 3 R106
X-RAY ON LATCH TIMER
Q101 J101-1
U102
+5V +5V
R114
R115
U105
TO R113 6 4
PAGE 9 X-RAY EN DRIVER +24V_EXT
5 1
U106 J102-1 FROM
J102-3 DIGITAL
4 2 SYSTEM
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 737950. THIS SHOWS
THE CONNECTIONS TO J101 AND J102. THE REMAINING CIRCUITS ARE SHOWN ON THE
PREVIOUS PAGE.
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
FOR DETAILS REGARDING THE CONNECTIONS J101 AND J102.
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
DES.\MFG.\AUTH.
L. FOSKIN 17 MAY 2000 MD-0767 REV M
SHEET 10 OF 19
+5V +15V +24V +24V
U9
J6-16
J8-11
F1 J6-17
U7
J8-13 J6-1
J6-2
J8-17
J6-3
J8-15
J6-4
DRIVER J6-20
J6-21
-15V
J6-22
J8-1 J6-23
J8-2
J8-3 U8
J8-4 R14 J6-5
J8-5 R16 J6-6
CPLD R18 J6-7
J8-6
J8-7 DRIVER R15 J6-24
J8-8 R17 J6-25
J8-10 R19 J6-26
J8-12
J8-16
U10
J8-18 R20 J6-8
R22 J6-9
R24 J6-10
R21 J6-27
DRIVER
J8-9 R23 J6-28
R25 J6-29
J8-21
R26 J6-31
J8-23 J6-32
FROM
PAGE 1 J6-12
J6-30
U20
J6-33
+3.3V J6-14
R54 -
2
A/D 1 R46 J6-15
CONVERTER +
3
R35
J6-18
R53
U23A
+3.3V J6-19
DS3
R30 +3.3V
5 1 +24V +24V
R27 J9-1
U19
DS2 24V FROM
5
R43
1 4 2 J9-3 ROOM INTERFACE
J8-14 R36
U14 1 5 DS1
5 1 Q3
2 4 U12
U15 5 1 +24V
R42
2 4 U11
4 2 R31 U11 R44
U13
4 2 U11 U11 DRIVER
DRIVER R28
K1
DRIVER DRIVER
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738947. THIS SHOWS THE CONNECTIONS
TO J6 AND J9; THE REMAINING CIRCUITS ARE SHOWN ON THE NEXT PAGE. DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J6, J9. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 11 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+3.3V +2.5V
U16 +24V
J8-11 3.3V
REGULATOR J2-1
+24V +24V R6 J2-2
U22 J2-3
J4A-1 J4E-1
R8 VOLTAGE R5 J2-4
REGULATOR J4A-2 J4E-2
U2 J2-5
J4A-3 J4E-3
+10V R4 J2-6
J4A-4 J4E-4
U9 U6 J4A-5 U4 J4E-5
+24V
J4A-6 J4E-6
R48
DRIVER
U21 J4A-7 J4E-7 J3-1
J8-13 R49 VOLTAGE J4A-8 J4E-8 R9 J3-2
REGULATOR DRIVER DRIVER J3-3
R47
+24V +24V
J3-4
J4B-1 J4F-1 J3-5
J4B-2 J4F-2 R7 J3-6
R10
J4D-2 J4H-2
Q2 Q1 J4D-3 J4H-3
J4D-4 J4H-4 +24V +24V +24V +24V
R13
R11
J4D-5 J4H-5
R37
R39
U11 J4D-6 J4H-6
J4D-7 J4H-7
DRIVER Q4 Q5
J4D-8 J4H-8
J7-6
R38
R40
J7-4
J7-1
D2 U11
J7-3
U18B U17 R41 DRIVER J7-5
4 6 J7-2
MONOSTABLE D1
J8-19 5 TIMER
D3 D4
J8-20 TO J8-22
(SHT 11)
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738947. THIS SHOWS THE CONNECTIONS TO J1 TO J4, J7, J10, J11, AND
THE VOLTAGE REGULATOR CIRCUITS; THE REMAINING CIRCUITS ARE SHOWN ON THE PREVIOUS PAGE. DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J1-J4, J7, AND J10. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 12 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V +24V
U10 +24V
+24V(A)
+15V
J8-11
J3-11
R17
J8-13 J3-12
F1 J3-9
J8-17 DS
U14 15 J3-10
J8-15 J6-20
J3-13
J6-17
J6-21
-15V
J6-18
DRIVER +24V J6-19 J4-7
J8-1 PREP SW
+24V J6-22 J4-8
J8-2 X-RAY SW
R26
1 4 J6-16 J4-10
J8-3 PWR ON
1 4 U18 +5V J6-14 J4-11
J8-4 +5V PWR OFF
2 3 J6-7 J4-12
J8-5 U26 PWR COMM
RN7D
CPLD DS29 J6-2 J4-1
RN7C
J8-6 2 3 RXD
R18
J6-23 J4-2
J8-7 CTS
R33 J4-4
J8-8 +5V DS21
1 4 TP1 TXD
J4-5
J8-10 U16 RTS
4 1 J4-3
4 1 DS16
RN6D
J8-12 2 3
U31 J4-9
J8-16 U29
3 2
J8-18
R11
3 2
+24V
J8-19 J1-3
+5V 4 1 J1-7
4 1
TP3 J1-2
U21
U32
RN6B
4 1 J1-8
J8-9 3 2
U30 3 2 J1-5
J8-21
3 2
FROM
J8-23
PAGE 1 +24V
4 1
R32 DS28 J7-16
1 4 U23
U20 3 2 J7-24
2 3 DS19 J7-23
R24
J8-14
R34
4 1 TP4
U22
J7-14
3 2
R23 J7-21
DS18 J7-2
R21
U24
J7-7
J8-22
J7-20
MUX
+24V(A)
R31
R30
J9-1
24V FROM
J8-20 J9-3 ROOM INTERFACE
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738114. THE CIRCUITS FOR THIS BOARD ARE SPLIT BETWEEN SHEETS 13, 14, AND 15.
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J6, AND J7. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 13 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
U10
+15V +15V
J3-1 J2-2
J3-2 J2-3
U2
J3-3 J2-1
J3-4 J2-5
J8-1
J3-6 J2-7
J8-2 DRIVER
J3-7 J2-4
J8-3
J3-8
J8-4
J8-5 J3-5
CPLD J3-14
J8-6 +5V
FROM
PAGE 1 J8-7
+5V +5V
RN3B
J8-8
J8-10 J6-1
J8-12 +24V J6-3
J8-16 J6-4
J8-18 4 1 J6-5
J8-19 +5V U3 J6-6
RN5C
3 2 DS2
R2
RN3D
+24V J6-24
+24V
4 1
RN3C
U11 J7-1
4 1
+24V J7-3
U5 3 2 DS10
+5V R10 J7-4
3 2 DS4 J7-5
R4 4 1
RN2B
+5V U4
+24V +5V
3 2 DS3
R3
RN2A
RN5D
4 1 +5V
+24V
+5V U7 +24V
RN6C
3 2 DS6
R6 4 1
RN2D
+24V 4 1
+5V U6
+24V +5V U12
3 2 DS5
4 1 R5 3 2 DS9
RN2C
R9 J7-6
RN6A
4 1 +5V U25
3 2 DS20 +24V
U9 +24V
RN3A R25
3 2 DS8
R8 4 1
+24V 4 1
U8
U17
3 2 DS7
4 1 R7 3 2 DS17
R22 J7-22
U1
3 2 DS1
R1
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738114. THE CIRCUITS FOR THIS BOARD ARE SPLIT BETWEEN SHEETS 13, 14, AND 15.
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J6, AND J7. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 14 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
U10
J8-1
J8-2
J8-3
U19
J8-4 J6-12
J8-5 J7-12
CPLD
J8-6 J6-11
FROM
PAGE 1 J8-7 J7-11
J8-8 DRIVER J6-10
J8-10 J7-10
J8-12 J6-9
J8-16 J7-9
J8-18
J8-19
DS11 DS12 DS13 DS14 DS22 DS23 DS24 DS25
R12
R13
R14
R15
R16
R19
R20
R27
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738114. THE CIRCUITS FOR THIS BOARD ARE SPLIT BETWEEN SHEETS 13, 14, AND 15.
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J6, AND J7. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 15 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+5V +24V
U10 +24V
+24V(A)
+15V
J8-11
J3-11
R17
J8-13 J3-12
F1 J3-9
J8-17 DS
U14 15 J3-10
J8-15 J10-17
J3-13
J12-10
J10-2
-15V
J12-2
DRIVER +24V J11-6 J4-7
J8-1 PREP SW
+24V J10-16 J4-8
J8-2 X-RAY SW
R26
1 4 J12-5 J4-10
J8-3 PWR ON
1 4 U18 +5V J11-9 J4-11
J8-4 +5V PWR OFF
2 3 J10-11 J4-12
J8-5 U26 PWR COMM
RN7D
CPLD DS29 J10-10 J4-1
RN7C
J8-6 2 3 RXD
R18
J11-8 J4-2
J8-7 CTS
R33 J4-4
J8-8 +5V DS21
1 4 TP1 TXD
J4-5
J8-10 U16 RTS
4 1 J4-3
4 1 DS16
RN6D
J8-12 2 3
U31 J4-9
J8-16 U29
3 2
J8-18
R11
3 2
+24V
J8-19 J1-3
+5V 4 1 J1-7
4 1
TP3 J1-2
U21
U32
RN6B
4 1 J1-8
J8-9 3 2
U30 3 2 J1-5
J8-21
3 2
FROM
J8-23
PAGE 1 +24V
4 1
R32 DS28 J12-8
1 4 U23
U20 3 2 J12-11
2 3 DS19 J12-12
R24
J8-14
R34
4 1 TP4
U22
J11-10
3 2
R23 J12-7
DS18 J12-3
R21
U24
J8-22
MUX
U27
D1 D3
R29 DS27
DRIVER D2 D4
R28 DS26 SW1
+24V(A)
R31
R30
J9-1
24V FROM
J8-20 J9-3 ROOM INTERFACE
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 902724. THE CIRCUITS FOR THIS BOARD ARE SPLIT BETWEEN SHEETS 16, 17, AND 18.
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J10, J11, J12, J13 AND J14. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 16 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
U10
+15V +15V
J3-1 J2-2
J3-2 J2-3
U2
J3-3 J2-1
J3-4 J2-5
J8-1
J3-6 J2-7
J8-2 DRIVER
J3-7 J2-4
J8-3
J3-8
J8-4
J8-5 J3-5
CPLD J3-14
J8-6 +5V
FROM
PAGE 1 J8-7
+5V +5V
RN3B
J8-8
J8-10 J10-9
J8-12 +24V J10-18
J8-16 J10-19
J8-18 4 1 J10-7
J8-19 +5V U3 J11-4
RN5C
3 2 DS2
R2
RN3D
+24V J12-13
+24V
4 1
RN3C
U11 J10-20
4 1
+24V J10-21
U5 3 2 DS10
+5V R10 J10-22
3 2 DS4 J10-23
R4 4 1
RN2B
+5V U4
+24V +5V
3 2 DS3
R3
RN2A
RN5D
4 1 +5V
+24V
+5V U7 +24V
RN6C
3 2 DS6
R6 4 1
RN2D
+24V 4 1
+5V U6
+24V +5V U12
3 2 DS5
4 1 R5 3 2 DS9
RN2C
R9 J10-8
RN6A
4 1 +5V U25
3 2 DS20 +24V
U9 +24V 1
RN3A R25
3 2 DS8
R8 4 1 2
+24V 4 1 JW2
U8 3
U17
3 2 DS7
4 1 R7 3 2 DS17
R22 J12-14
U1
3 2 DS1
R1
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 902724. THE CIRCUITS FOR THIS BOARD ARE SPLIT BETWEEN SHEETS 16, 17, AND 18.
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J10, J11, J12, J13 AND J14. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 17 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
J13-1
U10
J13-2
J10-12
J10-13
J10-24
J10-25
J8-1
J8-2
J8-3
U19
J8-4 J11-5
J8-5 J11-1
CPLD
J8-6 J11-3
FROM
PAGE 1 J8-7 J11-2
J8-8 DRIVER J11-7
J8-10 J12-6
J8-12 J12-4
J8-16 J10-1
J8-18
J8-19
DS11 DS12 DS13 DS14 DS22 DS23 DS24 DS25
R12
R13
R14
R15
R16
R19
R20
R27
J10-3
J10-4
J10-5
J10-6
J10-14
J10-15
J14-1
J14-2
J14-3
J14-4
J14-5
J14-6
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 902724. THE CIRCUITS FOR THIS BOARD ARE SPLIT BETWEEN SHEETS 16, 17, AND 18.
DRAWN DATE
G. SANWALD 16 MAY 2000 DIGITAL
CHECKED INTERFACE
KVR 17 MAY 2000
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
DES.\MFG.\AUTH.
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J10, J11, J12, J13 AND J14. MD-0767 REV M
L. FOSKIN 17 MAY 2000
SHEET 18 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
TP1
R2 J2-16 DOSE
FEEDBACK
+5V +5V
R21
R18
R19
R20
R1
R3
R4
Q1
R22
DS1 DS2 DS3 DS4 DS5 DS6
U4 U6
+5V +24V J2-12
X-ON
J2-7
+15V TRIGGER 0
J1-11 J2-8
TRIGGER 1
J1-13 J2-9
DATA TRIGGER 2
DRIVER J2-10
J1-17 LATCH TRIGGER 3
J2-11
J1-20 TRIGGER CLOCK
J1-19 J2-14
REMOTE ON
J1-1
J1-2 DS7 +15V +15V +24V +24V
J1-3
R23
R25
J1-4
R34
R36
FROM
PAGE 1 +5V +5V
J1-5
Q2
J1-6
R16
R15
R35
R5
J1-7 DS8
J1-8
R28
R24
J1-22
J1-15 Q4 J2-4
U8 READY
J1-9
+24V +24V
R29
J1-21
BUFFER
J1-23 -15V
R31
R26
Q5
SW1
DS9 Q3
U9
R27
BUFFER
R30
J2-1 TRIGGER
R32
ACKNOWLEDGE
J2-2
Q6
J2-13
R33
J2-15
SHEET 19 OF 19
Use and disclosure is subject to the restrictions on the title page of this CPI document.
+15V
Q6
+15V
Q5
+5V
J2-1
SWITCHED +15V
Q4 J2-6
TEST +15V
R2
Q3 R31 J2-7
TEST +15V
+5V +5V DS1 J2-2
+5V + DOSE
U1 DAP
J2-3
+5V +5V - DOSE CHAMBER
R5
J2-4 #1
DS32 DS29 OPTO
DAP J2-5
RELAY
R7
R8
R71
R69
CHANNEL 1
DS3 U5 J2-8
U31 U38 U2 GROUND
RN12C J2-2 J1-2 RS-422 J2-9
GROUND
RS-232 RS-232 DRIVER
RN12A J2-3 J1-3
TRANSMITTER / TRANSMITTER / MICRO-
UART
RECEIVER RECEIVER CONTROLLER +5V
RN12B J2-7 J1-7
R9
J2-5 J1-5 +5V
R10
Q1
5 6 1
R11
JW1
3 2 1 U8 D6
DATA BUS
D0..D7 D2 4 3
+15V
Q8
+15V
Q7
R26
R5
J3-4 #2
2 OPTO
DAP J3-5
R13
R14
3 RELAY
CHANNEL 2
4 DS2 U6 J3-8
GROUND
5 RS-422 J3-9
+5 AND +15 VOLT GROUND
J4-2 R45 DRIVER
REGULATORS
(U7, U4, L1, D4
TB7 J4-1 D5, ETC) +5V
R15
1 +5V
TP1 R16
2 Q2
5 6 1
3 R17
JW2
4 3 2 1 U9 D7
5
D3 4 3
DRAWN DATE
G. SANWALD 16 JULY 2001
CHECKED DAP
M. LODER 21 AUG 2001
DES.\MFG.\AUTH.
L. FOSKIN 28 AUG 2001 MD-0828 REV D
SHEET 1 OF 1
Use and disclosure is subject to the restrictions on the title page of this CPI document.
* +5V +5V
CONSOLE
CABLE FOR RS-232: U1, U2, AND R16 ARE NOT FITTED.
FOR RS-422: U12, RN3C, RN3D, RN3A, AND RN3B DS3 DS1
ARE NOT FITTED.
RXD TXD
R18
R15
U12 U20
*
J5-1 J4-1 J11-7 J7-7 RXD (RS-232) 14 RN3C 3 2 15
*
J4-2 J11-18 J7-18 CTS (RS-232) 13 RN3D 4 4 13
* RN3A
16 1 3 14
* RN3B
15 2 5 12
J5-4 J4-4 J11-6 J7-6 TXD (RS-232)
RS-232
J5-5 J4-5 J11-17 J7-17 RTS (RS-232) SERIAL PORT FOR REMOTE DUART
FLUORO CONTROL. REFER
* U2 TO MD-0766
+5V J5-3 J4-3
J11-11 J7-11 TXD- (RS-422) 7
RS-422 4
+5V +5V J11-10 J7-10 TXD+ (RS-422) C40
6 O/P
R47
Y2
DS41 DS42
DS45
TXD RXD C35
* U1
U18 1 Hz J11-13 J7-13 RXD- (RS-422) 7
R20
R19
RS-422 1
U1 J11-12 J7-12 RXD+ (RS-422) I/P
6
11 14 R2
* R16
J16-1
J11-9 J7-9
FROM +5V +5V
RAD-ONLY J16-2
12 13 R8 CONSOLE
DS44 DS43
(PAGE 2) J16-3
9 8 R10 U31
FPGA RXD TXD
R93
R98
J1 U42
RS-232
5 RN12E 12 3 14
3
6 RN12F 11 5 12
7
J6-1
7 RN12G 10 2 15
2
J6-2
8 RN12H 9 4 13
8
ALTERNATE +5V +5V
5 RS-232
R72
CONSOLE
+5V +5V CONNECTIONS DS32 DS29 DUART
J6-3
DS44 DS43 RXD TXD
J6-4 -12V
R71
R69
TXD RXD J2 U38
RS-232
(LAPTOP) 1 RN12A 16 3 14
R17
3
R8
J2
U5 2 RN12B 15 5 12
R5 7
11 14
3 TXD 3 RN12C 14 2 15
R4 2
10 7
7 RTS 4 RN12D 13 4 13
R3 8
12 13
2 RXD
5 RS-232
DATA BUS R9
9 8
D0..D7 8 CTS
RS-232 5
THIS SHEET SHOWS THE CONSOLE BOARD FOR DATA BUS
INDICO 100 GENERATORS WITH THE 31 X 42 CM OPTIONAL COMMUNICATIONS PORTS ARE SHOWN ON PAGE 2
D0..D7
CONSOLE. REFER TO PAGE 2 FOR INDICO 100 GENERATOR INTERFACE
GENERATORS WITH THE 23 X 56 CM CONSOLE BOARD GENERATOR CPU BOARD
AND THE RAD-ONLY CONSOLE.
CONSOLE BOARD (INDICO 100)
DRAWN DATE
G. SANWALD 13 DEC 2001 SERIAL
CHECKED COMMUNICATIONS
J. BARNES 9 JAN 2002
DES.\MFG.\AUTH.
L. FOSKIN 9 JAN 2002 MD-0829 REV G
SHEET 1 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.
COMMUNICATIONS PORTS SHOWN BELOW ARE OPTIONAL
+5V
*
FOR RS-232: U5, U9, JP2, AND R6 ARE NOT FITTED. DS16
FOR RS-422: U6, RN4A, RN4C, RN4D AND R7 ARE +5V +5V +5V +5V TP5
NOT FITTED. 1 Hz
* U9 DS47 DS45 DS46 DS48
6 J5-1
R65
RXD TXD RXD TXD
4 RS-422 U28
RN16C
RN16D
RN16A
RN16B
O/P 7 J5-2
J16 U50
3 RN18B 4 3 14
3
* U5 TO GENERATOR
+5V
INTERFACE 5 RN18C 6 5 12
J5-4 7
6 BOARD (PG 1)
D4 1 RS-422 7 RN18D 8 2 15
TXD I/P J5-5 2 CPU
7
1 RN18A 2 4 13
RN2A
+5V 8
+5V *JP2 J5-3
R6
D3 8 RN17D 7 7 10
* 3 5
D6 Q4 RXD
TP1
2 5 RN17C 6 6 11
RN2B
1 Hz 1
J15 RS-232
R94
JP2 CLOSED FOR RS-422,
R5
* U6 7 -12V
*RN4A
11 14 2 1 2
DATA BUS
8 D0..D7
*
12 13 6 RN4C 5 5
*RN4D
9 8 8 7
CPU GENERATOR CPU BOARD
RS-232
R7
* +3.3V
+5V +5V
-12V
DS2 DS3
R11
U21
TXD RXD
R19
R20
+5V DS1
U4
1 Hz
D2 DATA
BUFFER TP10 TP11
TXD 3.3V-5V U8
+5V RS-232
R23 J8-1 J16-1
RN2D
(LAPTOP) U14
D1 U20 J2 DATA R24 J8-2 J16-2
TO GENERATOR
RXD FPGA BUFFER INTERFACE
11 14 6 RN1C 5 5V-3.3V
Q1 3 TXD BOARD (PG 1)
RN2C
R22
R21
D0..D7 U11 7 RTS
RS-232 5 U4
R27 RS-232
DATA 2 RXD (LAPTOP)
THIS AREA SHOWS THE CONSOLE CPU BOARD BUFFER R28
3.3V-5V 8 CTS
FOR INDICO 100 GENERATORS WITH THE 23 X 56 CM
CONSOLE.
5
U14
DATA
BUFFER
DATA BUS 5V-3.3V
CONSOLE BOARD (INDICO 100) D0..D7
DRAWN DATE
RS-232
G. SANWALD 13 DEC 2001 SERIAL
THIS AREA SHOWS THE CONSOLE CPU BOARD FOR
INDICO 100 GENERATORS WITH RAD-ONLY CONSOLE.
CHECKED COMMUNICATIONS
J. BARNES 9 JAN 2002
DES.\MFG.\AUTH.
L. FOSKIN 9 JAN 2002 MD-0829 REV G
CONSOLE BOARD (INDICO 100)
SHEET 2 OF 2
Use and disclosure is subject to the restrictions on the title page of this CPI document.