COMPUTER ENGINEERING

MAROHOM, Sittie Shahanie L. ENGR. J.C Z. Apduhan

COE181/CPARCH1L

EXPERIMENT NO.3 CARRY LOOKAHEAD ADDERS

OBJECTIVES:
1. To understand the operation of carry lookahead adder.
2. To analyze the operation of a carry lookahead adder and generate the output.
3. To design the equivalent circuit using the combination of full adders.

MATERIALS:
power supply
breadboard
Connecting wires
3 pcs. 7432 OR gate IC
3 pcs 7408 AND gate IC
2 pcs 7404 NOT gate IC
7 pcs LEDs DISCUSSION:

To reduce the computation time, there are faster ways to add two binary numbers by using
carry lookahead adders. They work by creating two signals P and G known to be Carry
Propagator and Carry Generator. The carry propagator is propagated to the next level
whereas the carry generator is used to generate the output carry, regardless of input carry.
The block diagram of a 4-bit Carry Lookahead Adder is shown here below

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The number of gate levels for the carry propagation can be found from the circuit of
full adder. The signal from input carry Cm to output carry Cout requires an AND gate and an
OR gate, which constitutes two gate levels. So if there are four full adders in the parallel
adder, the output carry C5 would have 2 X 4 8 gate levels from Cl to C5. For an n-bit parallel
adder, there are 2n gate levels to propagate through.

RESULTS:
The corresponding boolean expressions are given here to construct a carry lookahead
adder. In the carry-lookahead circuit we ned to generate the two signals carry propagator(P)
and carry generator(G),

The output sum and carry can be expressed as

Sumi = Pi O Ci

Ci+l = Gi + ( Pi CD
Having these we could design the circuit. We can now write the Boolean function for
the carry output of each stage and substitute for each Ci its value from the previous equations:

Cl = Go + po • Co

C3 = G2 + P2 C2 —— G2 P2 • Gl + • PI • Go + • PI • PO Co

= G3 + P3 C3

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A. Using your designed circuit.

l. Derive the truth table of carry lookahead adder implementation:

INPUT OUTPUT

C P P P G G1 GC C C
0 0 1 2 0 2 1 2 3
0 0 0 0 0 0 0 0 0 0

1 0 0 1 0 0 1 0 0 1

0 0 1 0 0 1 0 0 1 0

1 0 1 1 0 1 0 1 1

0 1 0 0 1 0 0 1 0 0

1 1 0 1 1 0 1 1 0 1

0 1 1 0 1 1 0 1 1 0

1 1 1 1 1 1 1 1 1 1

Computations:

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C1 = Cin*P0 + G0 = G2 +P2 G1+ P2 G1 G0 + P2 P1

C1=P0 P0Cin
C3=G2
C2 = G1 +P1C1
= G1 +P1G0 + P1P0Cin C2=G1 C4 = G3+ P3C3
C4 = G3 + P3G2 + P3P2 G1+ P3P2 G1
C3 = G2 +P2C2 G0 + P3P2 P1 P0Cin

2. Design, construct and test a combination of full adder circuit implementation of carry
lookahead adder. Draw your logic diagram inside the box.

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Logic Diagram:

Test design :

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Figure 1: Logic Diagram using full adder.

Questions:
1. How would you describe the implementation of carry lookahead adder using full adder
circuits?

The implementation of carry-lookahead adder using full adder circuits have

equal propagation delay times by the sum outputs of S2 to S4.

OBSERVATION:

CONCLUSION:

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