Tb

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity tb is

generic(

n: integer:=5 -- n bits

);

port (

clk,rst: in std_logic;

BT: out std_logic

);

end TB;

architecture algoritmo of TB is

signal qp,qn: std_logic_vector (n-1 downto 0);

signal c: std_logic;

begin

algoritmo:process (qp,c)

begin

if (c='0') then

qn<=qp+1;

else

qn<= (others =>'0');

end if;
 end process;

com9:process (qp)

begin

if (qp=25) then

c<= '1';

BT<='1';

else

c<= '0';

BT<='0';

end if;

end process;

secuencial:process (rst,clk)

begin

if(rst='0') then

qp<= (others => '0');

elsif (clk'event and clk ='1') then

qp<= qn;

end if;

end process;

end algoritmo;

maquina de estados

library IEEE;
use IEEE.std_logic_1164.all;

entity fsm_contador is

port(

CLK,RST: in std_logic;

BT,X: in std_logic;

CTD: out std_logic_vector (2 downto 0)

);

end fsm_contador;

architecture algoritmo of fsm_contador is

signal Qp: std_logic_vector (2 downto 0);

signal Qn: std_logic_vector (2 downto 0);

begin

combinacional: process (BT,X,Qp)

begin

case Qp is

when "000"=>

if(X='1' and BT='1') then

Qn<="001";

elsif(X='0' and BT='1') then

Qn<="111";

else

Qn<=Qp;

end if;

CTD<="000";

when "001"=>

if(X='1' and BT='1') then

 Qn<="010";

elsif(X='0' and BT='1') then

Qn<="000";

else

Qn<=Qp;

end if;

CTD<="001";

when "010"=>

if(X='1' and BT='1') then

Qn<="011";

elsif(X='0' and BT='1') then

Qn<="001";

else

Qn<=Qp;

end if;

CTD<="010";

when "011"=>

if(X='1' and BT='1') then

Qn<="100";

elsif(X='0' and BT='1') then

Qn<="010";

else

Qn<=Qp;

end if;

CTD<="011";

when "100"=>
if(X='1' and BT='1') then

Qn<="101";

elsif(X='0' and BT='1') then

Qn<="011";

else

Qn<=Qp;

end if;

CTD<="100";

when "101"=>

if(X='1' and BT='1') then

Qn<="110";

elsif(X='0' and BT='1') then

Qn<="100";

else

Qn<=Qp;

end if;

CTD<="101";

when "110"=>

if(X='1' and BT='1') then

Qn<="111";

elsif(X='0' and BT='1') then

Qn<="101";

else

Qn<=Qp;

end if;

CTD<="110";
 when others=>

if(X='1' and BT='1') then

Qn<="000";

elsif(X='0' and BT='1') then

Qn<="110";

else

Qn<=Qp;

end if;

CTD<="111";

end case;

end process combinacional;

secuencial:process (RST,CLK)

begin

if(RST='0') then

Qp<="000";

elsif (CLK'event and CLK='1')

then

Qp<=Qn;

end if;

end process;

end algoritmo;

top

library IEEE;

use IEEE.std_logic_1164.all;

entity top_contador is

port (

CLK,RST: in std_logic;
 X: in std_logic;

CTD: out std_logic_vector (2 downto 0)

);

end top_contador;

architecture topcontador of top_contador is

signal SBT: std_logic;

signal SY: std_logic_vector (2 downto 0);

component fsm_contador is

port(

CLK,RST: in std_logic;

BT,X: in std_logic;

CTD: out std_logic_vector (2 downto 0)

);

end component;

component tb is

port (

clk,rst: in std_logic;

BT: out std_logic

);

end component;

begin

bloque1_fsmcontador: fsm_contador port map(CLK,RST,SBT,X,SY);

bloque2_tb: tb port map(CLK,RST,SBT);

CTD<=SY;

end topcontador;