A Transmission Gate Flip-Flop Based on Dual-
Threshold CMOS Techniques
Linfeng Li and Jianping Hu
Faculty of Information Science and Technology
Ningbo University
Ningbo City, China
Abstract—In present CMOS circuits, the power dissipation
caused by leakage current cannot be neglected anymore. An
effective way to reduce the leakage power is dual-threshold
techniques. Low-threshold transistors are assigned to critical
paths of the circuits to enhance the performance, while high-
threshold transistors are assigned to non-critical paths to reduce
the leakage current. This paper proposes a new transmission
gate flip-flop based on dual-threshold CMOS technique to
reduce its leakage power. Simulation results show that the
proposed transmission gate dual-threshold flip-flop saves 20-
30% power and 40-50% leakage power compared with the
single-threshold transmission gate one and gate-length biasing
one, respectively. The proposed flip-flop is an excellent
candidate for low-power VLSI designs in deep sub-micro ICs.
I. INTRODUCTION
With the growing uses of portable and wireless electronic
systems, reduction in power consumption has become more
and more important in today’s VLSI circuits [1-3]. In CMOS
digital circuits, power dissipation consists of dynamic and
static components. Since dynamic power is proportional to the
square of supply voltage VDD, lowering supply voltage is the
most effective way to reduce power consumptions as long as
dynamic power is dominant. With the lowering of supply
voltage, transistor threshold voltage should also be scaled in
order to satisfy the performance requirements. Unfortunately,
such scaling can lead to a dramatic increase in leakage current,
which become an important concern in low voltage and high
performance circuits.
For sequential circuits, there are several technologies to
reduce their leakage power. MTCMOS, leakage feed back,
gate-length biasing, and DTCMOS have been applied in flip-
flops [4-9]. MTCMOS technology provides low leakage and
high performance operation by utilizing high speed and low
VT transistors for logic cells and low leakage and high VT
devices as sleep transistors [4-6]. However, sleep transistors
cause additional dynamic power and logic cells to slow down
during the active mode. The leakage feed back technology is
applied to overcome the problem of holding state during
standby mode by maintaining an active path to one rail [9].
978-1-4244-4480-9/09/$25.00 ©2009 IEEE
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Though it can effectively reduce leakage current, the feed
back balloon cause large additional dynamic power and area
to lead to a penalty of performance. The gate-length biasing
flip-flop is based on the principle that an 8nm increase in gate
length yields 30% decrease in leakage with a 5% increase in
delay for a minimum size inverter [7]. However, considering
the balance of the leakage power and the delay, the reduction
magnitude of the leakage power is limited.
In this paper, a new flip-flop based on dual-threshold
technologies is proposed for delay-constrained circuits. For a
logic circuit, a high threshold voltage can be assigned to some
transistors on non-critical paths to reduce its leakage current,
while the performance is maintained due to the low-threshold
transistors. The proposed flip-flop achieves considerable low
leakage power without additional dynamic power and silicon
area caused by sleep transistors.
II. PREVIOUS WORKS
A single-threshold transmission gate flip-flop (ST-TG FF)
is shown in Fig. 1. ST-TG FF is extensively used in sequential
systems, thus it is taken as a benchmark circuit for comparing
the performances of the flip-flops in this paper. Because
leakage current increases exponentially, several leakage
reduction techniques for flip-flops have proposed in recent
years. A leakage feedback flip-flop (LFB FF) [9] shown in
Fig. 2 applies the principles of the leakage feedback gate to a
traditional master-slaver flip-flop. The inherent design of the
flip-flop allows this implementation to avoid adding any
capacitive load to the nodes on the critical path.
clk clkb
M
D T1 I1 T3 I3 Q
clkb
clkb T2 clk clk T4
I2I I4
Figure 1. Single-threshold transmission gate flip-flop (ST-TG FF).
539
 VDD VDD I0 I1 I3 I5
clk clkb
clk sleep P1 clkb sleepb P2 M
M D T1 T3 Q
D T1 I1 T2 I2 Q
L4
clkb sleepb N1 I3 clk sleep N2

clkb T2 clk clk T4 clkb

Figure 2. Dynamic leakage feedback flip-flop (LFB FF). L3

The critical path through the LFB FF consists solely of

low-threshold devices. The high-threshold inverters that
feedback to hold state during the active mode also provides
the feedback for the conditional sleep gating in standby mode.
It has no extra loading from the feedback mechanism beyond
the load inherent to the latches. During sleep mode, the
transistors P1 and N1 are off, and the transistors P2 and N2 are
on. Therefore, the master stage stores the data value and
propagates it through the low-threshold inverter (I2) in the
slave stage to the output. The sleep devices attached to the
sleep signal all turn off. The other sleep devices (minimum
sized) conditionally turn off to maintain the correct values at
the internal and external storage nodes. Simulations have
shown that the LFB FF is very favorable in terms of speed and
power compared to the other MTCMOS flip-flops [9].
A gate-length biasing flip-flop is shown in Fig. 3, which is
implemented with inverters and tri-state inverters. If we
employ gate-length biasing only to those transistors that are
turned off when both D-input and Q-output are low as shown
in Fig. 3, the leakage for those two flip-flop states can be
made very different. The increase of rising delay is larger than
that of falling delay since the transistors whose gate length is
increased are sensitized for rising signal. The rising and falling
setup time is increased by 34% and 24%, respectively [7].
VDD VDD
VDD
clk E F clkb G area and the length of diffusion area of a MOS device,
D Q
clkb clk
VDD VDD
clkb
clk
Figure 3. Gate-length biasing flip-flop (GLB FF).
III. DUAL THRESHOLDS FLIP-FLOP
The proposed dual threshold flip-flop is shown in Fig. 4.
Its structure is the same as a single-threshold transmission gate
flip-flop (ST-TG FF), but a higher threshold voltage is
assigned to the transistors in the blocks of Fig. 1 to reduce its
leakage current, which is used to hold the state.
L1
L2
I2 I4
Leakage paths reduced
High-threshold transistors
Leakage paths
Figure 4. Dual-threshold transmission gate flip-flop (DT-TG FF).
DT-TG FF consists of two paths, namely non-critical and
critical. The circuits that hold the state use high-threshold
transistors to reduce its leakage current. The performance is
maintained due to the low-threshold transistors in the critical
path.
A. Power dissipations
The switching power of an inverter PSW can been
described as
Psw = fVDD 2 (CparW + C wire ) (1)
Where the drain and gate capacitive parasitic are
C par = 3(C D LD + Cox L) (2)
VDD
Where CD and LD defines the diffusion capacitance per unit
respectively. COX and L define the oxide capacitance per unit
area and the drawn gate length, respectively, and Cwire is the
wire capacitance.
VDD
Compared with the leakage feedback flip-flop (LFB FF),
the DT-TG FF doesn’t demand additional MOS devices. The
performance penalty of a sleep transistor depends on its size
clk
H and the amount of current that goes through it. In LFB FF and
clkb the other flip-flops using sleep transistors, the high-threshold
transistors have wider transistors to maintain the performance.
According to (1) and (2), this will affect the total power
L-biasing device consumption. Though the leakage feedback flip-flop can
reduce larger leakage power than the ST-TG FF, the DT-TG
FF avoids the penalty of the additional dynamic power caused
by the sleep transistors with large size.
The leakages paths can be analyzed in Fig. 4. When the
master latch works, T1 is on while T2 is off. When the slave
master latch works, T3 is on while T4 is off. T2 and I2 are
used to hold the state of node M, T4 and I4 are used to hold
the state of node Q. The leakage of the two paths (L1 and L2)

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 is reduced due to the inverters (I2 and I4) with high-threshold
transistors. The other sneak leakage paths are depended on the
working states. When Q = 1, the leakage of the path (L3) is
reduced due to the transmission gate (T4) and the NMOS
transistor of inverter (I4) assigned with high threshold. When
Q = 0, the leakage of the path (L4) is reduced is reduced due
to the transmission gate (T4) and the PMOS transistor of
inverter (I4) assigned with high threshold. The total leakage
power is reduced greatly. Moreover, no any additional
dynamic power is caused, because no more transistors are
added in the flip-flop.
B. Delay constraint
There are three important timing parameters associated
with a flip-flop. The set-up time tsu is the time that the data
inputs (D) must be valid before the clock transition. The hold
time thold is the time the data input must remain valid after the
clock edge. Assuming that the setup and hold times are met,
the data at the input D is copied to the output Q after a worst-
case propagation delay (with reference to the clock edge)
denoted by tc-q.
Once we know the timing information for the flip-flops
and the combinational logic blocks, we can derive the system-
level timing constraints. In the synchronous sequential
circuits, switching events take place concurrently in response
to a clock stimulus. The results of operation await the next
clock transitions before progressing to the next stage. In other
words, the next cycle cannot begin unless all current
computations have completed and the system has come to rest.
The clock period T, at which the sequential circuit operates,
must thus accommodate the longest delay of any stage in the
network. Assume that the worst-case propagation delay of the
logic circuit equals tplogic, while its minimum delay (also called
the contamination delay) is tcd. The minimum clock period T
that is required for proper operation of the sequential circuits
is given by
T ≥ tc − q + t plogic + tsu
The hold time of the flip-flop imposes an extra constraint
for proper operation,
tcd , flip − flop + tcd , log ic ≥ thold
Where tcd, flip-flop is the minimum propagation delay (or
contamination delay) of the flip-flop. This constraint ensures
that the input data of the sequential elements is held long
enough after the clock edge and is not modified too soon by
the new wave of data coming in.
According to the Alpha power delay model [10], the
propagation delay, tp, of a CMOS inverter can be
approximated as
C LVDD
tp = K
W
μCox (VDD − VT )α
L Figure 5. The transient curves of flip-flop.
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Where COX and L define the oxide capacitance per unit area
and the drawn gate length, respectively. In long channel
devices the velocity saturation parameter, a, is equal to 2.
However, in cutting-edge processes a approaches 1. It is clear
that the large device size of high-threshold transistors for
satisfying the delay requirement will cause their switching
power, which may dominate the leakage power.
The leakage feedback flip-flop is implemented by inserting
sleep transistors. Small sleep devices further reduce the
leakage current in standby mode but slow down transitions in
active mode, because of the voltage drop across the sleep
transistors.
Gate-Length biasing involves a small increase in the gate
lengths of devices. In a 130-nm industrial process, it is
reported that an 8nm increase in gate length yields 30%
decrease in leakage with 5% increase in delay for a minimum
size inverter. However, the magnitude of reducing leakage
power is limited, because the gate-length biasing transistors
used in critical path directly deteriorate its performances.
In the proposed dual-threshold flip-flop, the critical paths
are assigned with low VT, which assures the same level delay
as the conventional master-slave flip-flop.
IV. SIMULATION RESULTS
In this section, the leakage power consumption of the
proposed dual-threshold transmission gate flip-flop is
compared with the other typical ones (ST-TG FF, GLB FF,
and LFB FF) in the 130nm CMOS process. ST-TG FF is taken
as a benchmark circuit for comparing their performances in
this paper. For the four flip-flops, the simulation is carried out
by HSPICE using the BSIM4 predictive models [11]. Their
delay, leakage power, and total power have been compared.
The same input and clock shown in Fig. 5 are given to these
circuits to assure the fairness of the comparison.
Their delays are listed in Tab. 1. Compared with ST-TG
(3) FF (single-threshold transmission gate flip flop), both GLB FF
(gate-length biasing flip-flop) and LFB FF (leakage feedback
flip-flop) have large delay penalty while the DT-TG FF (the
proposed dual-threshold transmission gate flip-flop) has the
same delay as the benchmark circuit due to the critical path
assigned with low VT. Moreover, there aren’t any more
(4) transistors (sleep transistors or feed back transistors) inserted
in DT-TG FF.
1.2
D
0
Voltage (V)V
1.2
clk
0
1.2
Q
0
(5) 0 0.1 0.2 0.3
Time (us)
541
 TABLE I. DELAY COMPARISONS OF FLIP-FLOPS TABLE II. POWER COMPARISONS OF FLIP-FLOPS
Dynamic Static Power Total Power
Flip-flops tsu (ns) thold (ns) tc-p (ns) T (ns) Flip-flops
Power (uw) (uw) (uw)

ST-TG FF 0.029 0 0.029 0.058 ST-TG FF 0.425 0.7 1.125

GLB FF 0.059 0 0.052 0.111 GLB FF 0.475 0.5 0.975

LFB FF 0.083 0 0.075 0.158 LFB FF 0.55 0.2 0.75

DT-TG FF 0.029 0 0.029 0.058 DT-TG FF 0.425 0.3 0.725

The simulation results for energy consumptions are V. CONCLUSIONS

illustrated in Fig. 6. Since the ST-TG FF doesn’t adopt any
technology of reducing leakage current, the total power is the
largest one, which is contributed to the increasing leakage
power in sequential circuits. The DT-TG FF has the lowest
power among those flip-flops. The high-threshold transistors
adopted in the state holding circuits reduce its leakage power.
Moreover, its simple structure with the least count of
transistors doesn’t cause the additional dynamic power.
Though LFB FF can reduce leakage current of all existing
sneak leakage paths very effectively, the sleep transistors can
bring up additional dynamic power, because the size of the
sleep transistors must be enlarged to meet the delay constraints,
and the gate capacitance of the sleep transistors becomes large,
which leads to additional dynamic power.
The power dissipations are compared in the Tab. 2.
Compared with ST-TG FF, DT-TG FF can save the 50%
leakage power and the 30% total power at the same size
transistors level, and DT-TG FF keeps the same dynamic
power as the ST-TG FF. Compared with ST-TG FF, LFB FF
can save the 70% leakage power and the 23% total power with
the serious penalty of additional dynamic power. GLB FF can
save 30% leakage power and the 20% total power compared
with ST-TG FF. with the increasing frequency, the dynamic
power will increase quickly, and thus LFB FF can be used in
low operation frequencies. The DT-TG FF is an excellent
candidate for low-energy VLSI designs in deep sub-micro
integrated circuits.
ST-TG DFF
2
GBL DFF
DLF DFF
Energy dissipations (pJ)
Based on that the characteristic of the high VT transistors
has low leakage current, the dual-threshold transmission gate
flip-flop is proposed. Compared with the previously published
technologies, the proposed flip-flop reduces the leakage power
considerably, and maintains the performance as the
conventional master-slave flip-flop. By HSPICE simulations,
the propose flip-flop can work well. It achieves considerable
energy savings over the other similar implementations. This
design idea could provide a significance reference that would
guide the design of the other circuits for reducing leakage
power in deep sub-micron ICs.
ACKNOWLEDGMENT
Project is supported by National Natural Science
Foundation of China (No. 60773071).
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