International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)
Design of a Low Power Dynamic Comparator in
180nm CMOS Technology
Anupriya Mishra
University School of Information, Communication &
Technology
Guru Gobind Singh Indraprastha University, Delhi, India
anupriyaece.2013@gmail.com
Abstract—This paper aimed towards compact and low power
dynamic CMOS comparator in 180nm technology with supply
voltage of 1.8V. Comparator is proposed in this paper using
circuit level techniques LECTOR, GALEOR, ONOFIC, LCNT &
LCMT in which two leakage transistors are added between pull
up and pull down network of logic circuit in different styles and
are used to design circuit with no critical path. Approach of
leakage transistor is to conceive a state with more than one
transistor OFF in a trail from supply voltage to ground. It is
significantly less leaky than a state with only one transistor OFF
in trail of from supply to ground. Proposed comparator circuit
performance analysis is done in respect of power dissipation and
delay. Total power dissipation in conventional circuit is
67.027pW with delay 79.940ps. In LECTOR and GALEOR
power consumption is in range of 50-60pW. In ONOFIC and
LCNT power dissipated in the range of 40-45pW. In LCMT
power reduces to 92% as compared to conventional comparator.
Moreover, power delay product (PDP) results also have been
compared for comparator circuit. Power consumption of
comparator is also compared with earlier reported circuits and
proposed circuit’s shows better performances.
Keywords─Comparator; leakage transistor; low power; multi-
threshold; stacking; VLSI
I. INTRODUCTION
In recent year’s proliferative demand of portable devices led to
colossal power consumption which impoverished the battery
service life. As the technology scales down, power
management becomes primary issue. The power is emerging
as the most censorious issue in system on chip design. The
aim of low power style is to extend the battery service life.
The prime power dissipation source of CMOS circuits are
static, short-circuit and dynamic power. The total power
dissipated by a circuit is given by [1-3]
Ptotal= Pswitching + Pshort + Pleakage
Pswitching= αCLVDD2f , Pshort=ζαVDDIshort
Pleakage=VDDIleakage
Where CL is the switching node capacitance, f is the frequency
of switching, VDD is the supply voltage, α is the switching
activity and ζ is the voltage settling time. Short circuit power
is due to the direct path between the supply and ground. Static
power is due to the leakage current [3]. Dynamic power is due
to the charging and discharging of output node capacitance.
ISBN: 978-1-5386-4119-4/18/$31.00 ©2018 IEEE
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Manoj Kumar
University School of Information, Communication &
Technology
Guru Gobind Singh Indraprastha University, Delhi, India
manojtaleja@yahoo.com
As indicated by condition the dynamic power dissipation can
be relieved by lessening clock frequency, switching activity,
and load capacitance or by scaling down supplied voltage i.e.
VDD. Reducing clock frequency is the most straightforward
activity; however it impacts the compatibility of chip. Power
dissipation can likewise be decreased by downsizing the
voltage VDD, however this could be done by device
technology. Area, power dissipation and propagation delay are
the primary parameters for designing a VLSI circuit. As the
technology scale down in nanometer level so the power
supply, threshold and device size reduces which brings about
expanding sub-threshold current exponentially. As leakage
current is significant factor for increasing power dissipation.
According to the International Technology Roadmap for
Semiconductor (ITRS), whole power consumption is
exorbitantly consecrated by the leakage power (as per
International Technology Roadmap for Semiconductor 2009).
It is expected that leakage power can increase up to 32 times
per device, so it is important to reduce power dissipation [3-5].
Power optimization can be achieved at multifarious abstract
level that are system, algorithm, architecture, logic, circuit and
device level. This paper centers on circuit level power
optimization technique [6]. Comparator is vital part utilized as
a part of analog-to-digital converters (ADCs). It is the second
most broadly utilized device in electronic circuit after Opamp.
Apart from ADCs, it is utilized as a part of peak detector, Zero
crossing detectors, BLDC operating motors and switching
power regulators [7-8]. Comparator is the device used to
compare two analog voltages or currents and switches its
output to indicate which is greater. In Fig. 1 if Vp is at higher
potential than Vn then the output of comparator is logic 1. If
Vp is at lower potential than Vn , output gives a logic 0 [8-10].
Vdd
Vp +
Vo
Vn -
gn d
Fig. 1 Circuit of a Comparator
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 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)

In this paper, a new dynamic comparator is proposed using

LECTOR, GALEOR, ONOFIC, LCNT and LCMT
techniques. Performance of dynamic comparator is analyzed
in terms of power consumption and delay.
The rest of the paper is composed as follows: Section II
portrays the conventional dynamic comparator working and
proposed comparator circuits. In Section III outcomes for the
proposed comparators has been acquired. Finally, Section IV
concludes this paper.
II. SYSTEM DESCRIPTION
Conventional dynamic comparator circuit is shown in fig. 2.
The circuit is a regenerative comparator found vast application
in ADCs. As they can make a expeditious certitude due to the
steady positive feedback in the regenerative latch. Where
M8/M3 and M9/M4 are two inverter of the latch and though
M7, M10, M5, M6 work as switches, M1 and M2 are the input
transistors that unbalanced the latch inverter.
A dynamic comparator work in two phases that is reset
(CLK=0) and evaluation (CLK=VDD) [7].
Vdd
condition. In evaluation phase when CLK= VDD, transistors
M7 and M10 are off. Output nodes that are pre-charged to
VDD, it starts to release by different rates depending upon
inputs given in comparator. Let VIN > VREF, then V2 discharge
faster than V1, hence when V2 falls down to VDD-│VTHP│
before V1, transistor M9 will turn on initiating the latch
regeneration caused by back-to-back inverters(M8, M3, M9,
M4). Thus V1 pulls to VDD and V2 to ground [3]. Fig. 3
shows an output and input waveform for conventional
comparator.
First proposed circuit of dynamic comparator is shown in fig
4. Leakage Control Transistor (LECTOR) technique
essentially incotporates two leakage transistor which are
interpolated between PUN and PDN. The leakage transistor
gate restarined by another leakage transistor source. At the
point when in excess of one transistor is OFF in a path from
supply voltage to ground is considerably less leaky than one
transistor OFF amid a way. Technique is tend to applied in
dynamic compartaor [10]. Input and output waveform shown
in Fig. 5.
Vdd

CLK CLK
M7 M9
CLK
CLK M8 M10
V2 V1
V2 V1

CLK
M5
M6
CLK

CLK

M4 CLK

M3

Vref

Vref
M1 Vin
Vin M2
Gnd

gnd Fig. 4 Comparator using LECTOR Technique

Fig. 2 Conventional dynamic Comparator

Fig. 3 Input and output waveform of conventional comparator Fig. 5 Input and output waveform of comparator using LECTOR technique

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 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)
In second proposed circuit of dynamic comparator GALEOR
technique is used shown in fig. 6. Gate Leakage Transistor
(GALEOR) technique in which two gated leakage transistor is
inserted in the path of supply voltage and ground. The gates of
these additional transistors are controlled by drain voltage
[11]. Throughout active mode leakage transistor own normal
operation. During standby mode it produces stacking effect.
Input and output waveform of proposed circuit shown in fig.
7.
Vdd
CLK
CLK
V2 V1
CLK
CLK
Vref
Vin
Gnd
Fig. 6 Comparator using GALEOR technique
Fig. 7 Input and output waveform of comparator using GALEOR technique
In third proposed circuit of comparator ONOFIC technique is
used shown in fig. 8. On-Off logic circuit (ONOFIC) is a
single threshold level approach for leakage power reduction.
In this technique two transitor are placed between pull-up
network and pull-down network. In this technique source of
PMOS transistor is connected to supply voltage and drain
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connected to gate of NMOS transistor. PUN is connected to
source of NMOS and PDN connected to drain of NMOS.
These transitor offer sensible conducting path when both
transistor are ON they work in linear region. Once these
transitor are OFF they work in cut-off region [5][12]. Fig. 9
shown input and output waveform of propsed comparator.
Vdd
CLK
CLK
V2 V1
Vdd
Vdd
CLK
CLK
Vref
Vin
Gnd
Fig. 8 Comparator using ONOFIC Technique
Fig. 9 Input and output waveform of comparator using ONOFIC technique
In fourth proposed circuit of comparator shown in Fig. 10
LCNT technique is applied. Leakage Control NMOS transistor
(LCNT) is a circuit level technique used for attenuated leakage
current in CMOS logic gate. During this technique two NMOS
transistor are inserted between pull-up network and pull-down
network. Gate of each NMOS connected to output node of
comparator. Once these leak transistors are ON they supply a
 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)
decent conducting path with minimum delay and once these
are off they provide stacking impact. It minimizes the leakage
current [5] [12]. Input and output waveform of proposed
circuit of comparator is shown on fig. 11.
Vdd
CLK
V2
LCT
LCT
LCT
LCT
CLK
CLK
Vref
Vinn
Gnd
Fig. 10 Comparator using LCNT technique
Fig. 11 Input and output waveform of comparator using LCNT technique
Fifth proposed comparator circuit is shown in fig. 12. This
technique is leakage control multi-threshold technique. This is
the inclusion of LCNT technique and Multi-threshold CMOS
technique (MTCMOS). MTCMOS is the priory proposed
technique in which PMOS is added between logic and power
supply and NMOS transistor between logic and ground. It
creates a pragmatic supply rail or virtual ground. Added
transistor may have high, low and medium threshold voltage
as per desideratum. The low threshold transistor used to
reduce delay in circuit while high threshold reduces the power
dissipation in shortest path [9]. High threshold transistors are
added to reduce power dissipation by having two modes active
and sleep for efficient power management. The threshold
voltage is selected based on supply voltage. MTCMOS can
only reduce the standby leakage power and area is penalty in
this technique [13-14].
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Vdd
S
CLK
CLK
CLK V2 V1
V1
CLK
CLK
Vref
Vin
Sbar
Gnd
Fig. 12 Comparator using LCMT technique
Fig. 13 Input and output waveform of Comparator using LCMT technique
III RESULTS AND DISCUSSIONS
In this section analysis of total power dissipation is mentioned
for proposed circuits with conventional using mentor graphics
in 180nm CMOS technology with provide voltage variation
from [1.0-1.8] V. Power dissipation is reduced by applying
circuit level techniques in logic circuit of comparator. Table I
demonstrates the aggregate power dissipation results for
LECTOR, GALEOR, ONOFIC, LCNT and LCMT
techniques. The proposed design (LCMT) of comparator
dissipates less power as compared to other circuit techniques.
Table II outlines delay in comparator of different techniques.
In circuit level techniques extra transistors are inserted
between PDN and PUN it raises the propagation delay.
LECTOR, GALEOR and ONOFIC techniques are good for
leakage reduction but these techniques are not proficient of
reducing propagation delay. In LCMT as two NMOS LCTs
are inserted so it gives a more desirable result with better
speed of operation and high threshold transistor also helps in
reducing standby leakage power. Also in LCNT two NMOS
transistor are inserted, it conjointly has smart speed of
operation with less power dissipation
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 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)

Table I: Power Consumption Comparisons of Proposed Circuits

Supply voltage Conventional LECTOR GALEOR ONOFIC LCNT LCMT
(V) (pW) (pW) (pW) (pW) (pW) (pW)
1.0 20.538 14.132 19.252 12.237 13.895 3.402
1.1 24.563 16.679 22.377 14.502 16.304 3.957
1.2 29.128 19.538 26.003 16.953 18.902 4.040
1.3 34.283 22.621 29.887 19.602 21.691 4.085
1.4 40.122 25.930 34.029 22.446 24.675 4.112
1.5 46.751 29.487 38.405 25.489 27.836 4.233
1.6 52.283 33.256 42.838 28.761 31.030 4.412
1.7 59.710 37.658 44.558 32.662 34.565 4.647
1.8 67.027 54.290 58.363 43.005 43.426 4.997

Table II: Delay comparisons of Proposed Circuits

Supply voltage Conventional LECTOR GALEOR ONOFIC LCNT LCMT
(V) (ns) (ns) (ns) (ns) (ns) (ns)
1.0 79.949 50.094 50.418 50.186 40.054 45.539
1.1 79.949 50.080 50.375 50.146 40.044 45.430
1.2 79.948 50.069 50.344 50.126 40.035 45.362
1.3 79.946 50.062 50.263 50.113 40.031 45.325
1.4 79.943 50.057 50.222 50.098 30.025 45.267
1.5 79.942 50.052 50.167 50.088 30.024 45.223
1.6 79.942 50.047 50.132 50.082 30.023 45.185
1.7 79.941 50.044 50.083 50.076 30.023 45.166
1.8 79.940 50.039 50.045 50.071 30.023 45.132

Table III: PDP comparisons of proposed circuit

Supply voltage Conventional LECTOR GALEOR ONOFIC LCNT LCMT
(V) (J×10-24) (J×10-24) (J×10-24) (J×10-24) (J×10-24) (J×10-24)
1.0 1.641 0.707 0.970 0.614 0.556 0.154
1.1 1.963 0.835 1.119 0.727 0.642 0.179
1.2 2.328 0.978 1.301 0.849 0.756 0.183
1.3 2.740 1.132 1.501 0.982 0.800 0.185
1.4 3.207 1.297 1.709 1.124 0.840 0.186
1.5 3.737 1.475 1.926 1.276 0.841 0.191
1.6 4.179 1.664 2.147 1.440 0.931 0.199
1.7 4.773 1.884 2.231 1.635 1.037 0.209
1.8 5.358 2.716 2.944 2.153 1.304 0.225

100
80
C o n v e n tio n a l C o n v e n tio n a l
P o w e r d is s ip a t io n ( p W )

LECTOR 80 LECTOR
60
G ALEOR
D e la y (n s )

G ALEOR
60
40 O N O F IC O N O F IC
LCNT 40 LCNT
20 LCMT
LCMT
20

0
0
0 .8 1 .0 1 .2 1 .4 1 .6 1 .8 2 .0
0 .8 1 .0 1 .2 1 .4 1 .6 1 .8 2 .0
S u p p ly v o lta g e (V )
S u p p ly v o lta g e (V )

Fig. 14 Power consumptions comparison for comparator with supply voltage Fig. 15 Delay comparison for comparator with supply voltage
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 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)

threshold CMOS technique," International

6 Conference on Information,
C o n v e n tio n a l
Communication, Instrumentation and
LECTOR Control (ICICIC), Indore, 2017, pp. 1-4.
P D P (J × 1 0 -2 4 )

4 G ALEOR [3] A. D. Shinde and M. Sharma, "Low power, area

2
0 Implementation of a Low-Power , High-Speed
0 .8 1 .0 1 .2 1 .4 1 .6
S u p p ly v o lta g e (V )
Fig. 16 PDP comparison for comparator with supply voltage
Fig. 14 shows total power dissipation at varying supply
voltage from (1.0-1.8) V. As power is directly proportional to
supply voltage, with increase in supply voltage power also
increases. Power consumption has been reduced from
67.02pW to 43pW in LCNT and in LCMT technique it is
reduced to 4.9pW. In terms of power and delay LCMT give
good result. Proposed comparator give better outcome as
compared to other applied technique. Table III illustrates the
power efficiency of proposed comparator circuits. PDP
ascends by increment in power consumption and propagation
delay in circuit. LCMT give best performance in terms of PDP
as its gives less PDP compared to other shown in Fig. 16.
IV CONCLUSION
In presented work a dynamic CMOS comparator using
different circuit level techniques in 180nm CMOS technology
is designed. Performance has been analyzed in terms of power
dissipation, delay and power-delay product. Proposed LCMT
provides a less power dissipation with minimum delay. High
threshold transistor is used as sleep transistor for reducing
power dissipation. From simulation result it can be verified
that there is an average saving of 92% for power dissipation
with 43% decrease in delay in LCMT in comparison with
conventional circuit. In LCNT there is 35% of power
reduction over a conventional circuit. In order to compare the
proposed comparator with earlier designed double-tail
dynamic comparator simulated in 180nm technology
dissipates 329µW power at 1.2V supply voltage and gives a
propagation delay of 69ps. Power saving can be accomplished
by imbedding leakage transistors in logic circuit.
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