Digital Electronics

Memory and Storage

(Part 2)

Lecture No. 16
1

ROM types

Data written by
the user, and can
be changed with
some difficulty.

Data written by the Data written by

manufacturer, and the user, and can
can never be never be changed.
changed.

2
 Larger / Wider ROM

Made up from sets of chips

Consider a 32K × 8 ROM
❑ No data in
❑ No R/W

Example 1: Construct a 128K x 32 Memory

using 128K x 8 ROM ICs

4
Example 2: Construct a 64K x 16 Memory using
32K x 8 ROM ICs

PROM

• PROMs are programmable ROM, in which a

fused link is burned (open) during the
programming process. Once the PROM is
programmed, it cannot be reversed.
• An array of semiconductor devices
– Diodes
– Transistors
– Field effect transistors
Burn out fuses to disable unwanted diodes or transistors

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 PROM
❑ MOS PROM array with fusible links. (All drains are commonly
connected to VDD.)

16×5 PROM Organization

1-Bit Storage Cell

8
 PROM Memories
❑ PROM Organization
1024 x 4 PROM

CS
Chip Select Line (active low) PROG
A9
Prog. Enable Line (active low) A8
A7 O3
10 Address Lines A6 O2
A5 O1
4 Data Lines - outputs are A4 O0
A3
commonly 3-state buffered and
A2
are enabled by CS
A1
A0

UV EPROMs and EEPROMs

•

VPP
A0
A1 O0
A2 O1
A3 O2
A4 O3
A5 O4
A6 O5
A7 O6
A8 O7
A9
A10
CE/PGM

OE

10
 ROM Consideration
❑ A ROM has a fixed AND plane and a programmable OR
plane
❑ Size of AND plane is 2n where n = number of input pins
• Has an AND gate for every possible minterm so that all
input combinations access a different AND gate
❑ OR plane dictates function mapped by the ROM

11

ROM Internal Structure

n Inputs
Lines

..
n × 2n . Memory Array
. decoder . n
. 2 words x m bits

...

m Outputs Lines

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 ROM Structure
❑ Each minterm of each function can be specified

A
3 Inputs B ROM
Lines 8 words
C x 5 bits

F0 F1 F2 F3 F4

5 Outputs Lines
13

Construction of ROM
• Each output of the decoder represents a memory address.
• Each OR gate must be considered as having 32 inputs.
• A 2n x m ROM will have an internal n x 2n decoder and m OR
gates with 2n inputs.

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 ROM Initialization
• 4×4 ROM
– 22×4 bit ROM has 4 addresses that are decoded
– Each address represents 1 word
– Each word has 4 bits

2-to-4 decoder

a0

a1

d3 d2 d1 d0 15

Example 1
• Implementation of three functions, F2 F1 F0 with an 8 × 3 ROM.
• Crosses (x) indicate connections between decoder outputs and OR
gates. Otherwise there is no connection.

A0
A1
A2

F2 = Σm(1,2,3,4) F1 = Σm(0,1,5) F0 = Σm(1,3,5) 16

 Example 2
• The Figure shows an alternative presentation
of the same 8 x 3 ROM, using “abbreviated”
OR gates to make the diagram neater.

A0
F0 = Σm(0,1,3) A1
F1 = Σm(0,2,5) A2
F2 =
Σm(1,4,5,6)

F2 F1 F0
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Why is this a “memory”?

❑ This combinational circuit can be considered a read-only memory.
– It stores eight words of data, each consisting of three bits.
– The decoder inputs form an address, which refers to one of the
eight available words.
– So every input combination corresponds to an address, which is
“read” to produce a 3-bit data output.

A0
A1
A2

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F F F
 ROM Table
• ROMs are actually combinational
devices, not sequential ones!
– ROM as a combinational circuit
takes an address as input, and
produces some data as the output.
• A ROM table is basically just a
truth table.
– The table shows what data are
stored at each ROM address.
– You can generate that data
combinationally, using the address
as the input.

19

PROM as a Sequential Circuit

❑ Need to construct FSM with:
15 states 1024 x 8 PROM
6 inputs PROG
4 outputs CS
A9
A8
We need at least 4 FFs to INPUTS A7 O7
store the 15 states A6 O6 OUTPUTS
A5 O5
A4 O4
No. of combinational logic A3 O3
inputs (i.e. PROM address A2 O2
A1 O1
signals) is 6 + 4 = 10; A0 O0
therefore the PROM must
have a minimum of 210 or
Q0 D0
1024 locations Q1 D1
Each location has to store the Q2 D2
next state and output values; Q3 D3

therefore we need at least CLOCK

4 + 4 = 8 bits / location 20
PROM size : 1024 x 8
 Example 3
•

x A
0 3
1 3
2 6
3 18

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Example 3
✔Step 2: Implementation

0 x x

2 to 4 1 x x
decoder
2 x x

3 x x

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 Example 4
❑ Implement the following
function using a ROM.
F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ +
A’B’C

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Example 4: Implementation
m0=AʼBʼCʼ

m1=AʼBʼC

m2=AʼBCʼ
A
m3=AʼBC
3 to 8
B
decoder m4=ABʼCʼ

m5=ABʼC
C
m6=ABCʼ

m7=ABC

Each column is a new function

F G H
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 Homework
•

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