10/19/2018

FREQUENCY DIVISION
• J-K FFs ,in toggle mode as shown, can provider
frequency divider system

FREQUENCY DIVISION
• J-K FFs ,in toggle mode as shown, can provider
frequency divider system

-How does the frequency of Q compares to the

frequency of the CLK
- How can the CLK frequency be divided further

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FREQUENCY DIVISION
• By connecting more flip-flops as shown, CLK
frequency can divided further

FREQUENCY DIVISION
• By connecting more flip-flops as shown, CLK
frequency can divided further

80Hz

- What would be the frequency of QB if the frequency of CLK was 80Hz

-connecting flip-flops as discussed, achieves ÷2n frequency division

-Implement a circuit which will achieve a ÷ by 16 frequency division

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COUNTERS
• Flip-flops can also be used for counting operations
(counter).
• The # and the way in which flip-flops are connected
determines the # of states (modulus) & counting
sequence.
• Two broad categories of counters : Asynchronous
and synchronous.
• In asynchronous: FF are clocked consecutively
• In synchronous : FF are clocked simultaneously

Asynchronous Counters
 Asynchronous or ripple : output of one flip-flop drives
the CLK of the next FF.
 The clock signal is applied only to the 1st FF, (input FF)
 Examine2-bit asynchronous counter shown

Determine output waveform

and modulus of the counter

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Asynchronous Counters
 Asynchronous or ripple : output of one flip-flop drives
the CLK of the next FF.
 The clock input is applied only to the 1st FF, (input FF)
 2-bit asynchronous counter with 4 clock pulses

state sequence 0

Modulus is 2n = # of states

Asynchronous Counters
3-bit asynchronous counter

Counter goes through

8 states
It recycles after
counting 7

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Asynchronous Counters
Propagation delay: Accumulation of some time taken by FFs
to relay clock effect to their successive FFs.
Input clk pulse ripples
through counter (taking
time)to reach last FF
NB propagation delays(TPLH
& TPHL ) in waveforms
- They are disadvantages of
ripple counter
- total delay T < clock T
Calc tot delay if
propagation delay is 50ns
What should be max freq
of CLK

Asynchronous Counters
Propagation delay: Accumulation of some time taken by FFs
to relay clock effect to their successive FFs
Input clk pulse ripples
through counter (taking
time)to reach last FF
NB propagation delays(TPLH
& TPHL ) in waveforms
- They are disadvantages of
ripple counter
- total delay T < clock T

 delay = 50ns x 3 FF =
max freq of CLK = 1/(3x50n)=

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Decade Asynchronous Counters (MOD 10)

Counters can have # of states < max 2n
 Decade counter have 4 FF but truncated to count 10 states
0000

1001 -> max

1010 -> decode

Decade Asynchronous Counters (MOD 10)

Counters can have # of states < max 2n
 Decade counter have 4 FF but truncated to count 10 states

•NB glitch on Q1&

decoder output as
1010 is decoded.

•Glitch ~ rapid change

of state
- causing Voltage spike

 Draw the circuit of

MOD 7 Ripple counter
and its timing diagram.

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IC Asynchronous Counter (74LS93)

Counters are available in IC form i.e. 74LS93
-It can be configured as a frequency divider
-Or configured in different modulus counting

The 74LS93 logic symbol

The 74LS93 logic diagram
The 74LS93 logic diagram

Show how 74LS93 can be configured as MOD 6 counter

IC Asynchronous Counter (74LS93)

Show how 74LS93 can be configured as MOD 6 counter
Solution : The counter must decode 0 1 1 0 i.e. NAND Q1 with Q2
Q3 Q2 Q1 Q0

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Synchronous Counter
 FF are clocked at the same time by a common clock
In asynchronous output of preceding FF are used to clock next
FF
In synchronous counter output of preceding FF (+modification
sometimes) are used as inputs (J & K) of next FF
 2-bit synchronous counter analysis

Q0 – toggles at each
clock pulse

Q1 – changes after every high pulse of-Initially

Q0 all FF output is reset
i.e Q1 toggles FF1 - FF0 inputs (J&K)= 1 -> clk1 -> FF0 output
– Thus any high of Q0 can be used to =1(toggle)
toggle FF1 - FF1 inputs (J&K)= 0 -> clk1 -> FF1 output =0
(N.C)

Synchronous Counter
 FF are clocked at the same time by a common clock
In asynchronous output of preceding FF are used to clock next
FF
In synchronous counter output of preceding FF (+modification
sometimes) are used as inputs (J & K) of next FF
 2-bit synchronous counter analysis

The resulting circuit

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Synchronous Counter
3 -bit synchronous counter analysis

- Q0 and Q1 analysis is similar to 2bit

- FF2 is toggled by Q0 and Q1

Synchronous Counter
3 -bit synchronous counter analysis

- Q0 and Q1 analysis is similar to 2bit

- Q2 is toggled by Q0 and Q1

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Design of Synchronous Counter

1st step: Specify sequence and draw state diagram

2nd Step: Derive next state table from state diagram

3rd Step: Develop a transition table (list possible inputs for

output transition)

Design of Synchronous Counter

1st step: Specify sequence and draw state diagram

2nd Step: Derive next state table from state diagram

3rd Step: Develop a transition table (list possible inputs for

output transition)

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Design of Synchronous Counter

4th
step: Transfer J and K states from transition table to K-
map

Design of Synchronous Counter

4th step: Transfer J and K states from transition table to K-
map

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Design of Synchronous Counter

Last group map and draw the circuit

Circuit diagram

Design a counter with the following

sequence 1->3->5->1

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UP/down Design of Synchronous Counter

Sequence specification and state diagram

Derive next state table from state diagram

UP/down Design of Synchronous Counter

Transfer J and K states from transition table to K-map

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UP/down Design of Synchronous Counter

Transfer J and K states from transition table to K-map

CIRCUIT

J 0  Q2Q1Y  Q2 Q1Y  Q2 Q1Y  Q2Q1Y

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CIRCUIT

J 0  Q2Q1Y  Q2 Q1Y  Q2 Q1Y  Q2Q1Y

K 0  Q 2 Q1Y  Q 2Q1Y  Q2 Q1Y  Q2Q1Y

CIRCUIT

J 0  Q2Q1Y  Q2 Q1Y  Q2 Q1Y  Q2Q1Y

K 0  Q 2 Q1Y  Q 2Q1Y  Q2 Q1Y  Q2Q1Y

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CIRCUIT

J 0  Q2Q1Y  Q2 Q1Y  Q2 Q1Y  Q2Q1Y

K 0  Q 2 Q1Y  Q 2Q1Y  Q2 Q1Y  Q2Q1Y

Complete the circuit

CIRCUIT

J 0  Q2Q1Y  Q2 Q1Y  Q2 Q1Y  Q2Q1Y

K 0  Q 2 Q1Y  Q 2Q1Y  Q2 Q1Y  Q2Q1Y

Complete the circuit

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UP/down Design of Synchronous Counter

Sequence specification and state diagram
Y=1
Y=0

Derive next state table from state diagram

Present state Next state Next state
UP(Y=1) DOWN(Y=0)
Q2 Q1 Q0 Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 1 0 1 1 1
0 1 0 1 0 1 0 0 1
1 0 1 1 1 1 0 1 0
1 1 1 0 0 1 1 0 1

Complete the process and draw the circuit

UP/down IC Synchronous Counter

Up/Down Counters are available in IC form i.e. 74HC190
74HC190 is a synchronous Up/Down decade counter:

-D/U : Determines direction (up or down) of the count

- LOAD : Presets the counter to desired (BCD) digits
- MAX/MIN : Indicate that terminal count is reached (0000 & 1001)
- CTEN : Allows/Inhibit counter to count up or down (It freezes or
unfreeze) counter
- RCO : Activate the next cascaded counter when the preceding counter
has reached terminal count

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UP/down IC Synchronous Counter

74HC190 operation:

UP/down IC Synchronous Counter

74HC190 operation:

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