Spring 2023: SOC EE5004 1/20

SOC Packaging and Signal Integrity

LABORATORY MANUAL
Spring 2023

LAB 2
Title: Impedance Matching Using Lumped Components

Dr. Hassan Saif

Engr. Hamza Atiq
Shahid Mehmood 22I-9942

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LAB ENGINEER SIGNATURE & DATE

MARKS AWARDED: /10

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NATIONAL UNIVERSITY OF COMPUTER AND EMERGING SCIENCES (NUCES),
ISLAMABAD
Version
Prepared by: Engr. Hamza Atiq 1.0
:
Updated By: 6 Apr 2021 Date: 07 Feb,2023
Last Edition: Date:
Verified by: Dr Hassan Saif
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Lab Tasks

Figure 1. Schematic
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Figure 2. Smith Chart Matching Utility Setup

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Figure 3. Generated Lumped Matching Network

Figure 4. Optimized Schematic

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Figure 5. Final Schematic

Figure 6. Optimization Results

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Figure 7. Input Layout

Figure 8. output Layout

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Figure 9.Co Simulation Optimization Results

Remarks:
Source to load impedances are matched for given L-Matched network. Z2P equation is used to
model transistors.
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Task1

Figure 10. Microstrip Input Schematic

Figure 11. Schematic

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Figure 12. Results

Figure 13. Momentum Layout

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Figure 14. Matching layout Results

Figure 15. Microstrip Schematic using Co-Simulation components

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Figure 16. Co-Simulation S- Parameter Results

Source to load impedances are matched for given network.

Task2

Figure 17. Schematic

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Figure 18. Smith Chart Matching Utility Setup

Figure 19. Generated Lumped Matching Network

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Figure 20. Generated Lumped Matching Network

Figure 21. Results

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Figure 22. Generated Lumped Matching Network

Figure23. Optimized Schematic

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Figure 24. Schematic

Figure 25. Optimization Results

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Figure 26. Input Layout

Figure 27. output Layout

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Figure 28.Co Simulation Results 1

Figure 29.Co Simulation Results 2

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Figure 30. Final Schematic

Figure 31. Co-Simulation Optimization Results

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Conclusion:
Source to load impedances is matched. The layout is generated, and EM
simulation is done for the input & output match network. S-Parameter,
optimized, and layout/Co-Simulation results are verified. S(1,1) and
S(2,2) parameters are as per our requirement of less than -20dB.