LAB 4

Bootstrap Circuits (Level

Translators/Shifters) Design and
Simulation
Name: Mudassir Ali
Roll No.: 21i-2425
Section: IC Design
Date: March 16,2022
Subject: Mixed Signal IC Design
Submitted to: Google Classroom
 Lab Tasks

1. Voltage Level Shifter

Figure 1: Schematic for the Voltage level shifter

Figure 2: Testbench for the voltage level shifter

 Figure 3: Output waveforms of the voltage level shifter

The above waveforms shows that a 0-1 V signal was applied at the input o the voltage level shifter and at the output
we got a waveform of 2-3 V. The input wave from are shown in dotted lines while the output waveforms are shown
in solid lines.

2. Voltage Level Translator:

Figure 4: Schematic for the Voltage level translator

 Figure 5: Testbench for the voltage level translator

Figure 6: Output waveforms of the voltage level translator

The above results shows that a 0-1V clock is applied at the input of the Voltage level translator and we have got an
output of 0-3 V. The output shown in black in the above waveforms while ethe input waveforms are shown in colors.
3. Non-overlapping Clock Generator:

Figure 7: Schematic of the non-overlapping waveform

Figure 8: Testbench for the non-overlapping clock

 Figure 9: Output waveform for the non-overlapping clock generator

The above waveforms are self-explanatory. The input clock is shown in dotted lines while the resultant non
overlapping clocks are shown in solid lines.
 Assignments:
1. Design a Voltage level Shifter using NMOS transistors and 1pF internal capacitor that can derive the
following loads:
a. 1 pF
b. 3 pF
c. 5 pF
d. 10 pF
a. 1pF

Figure 10:Schematic for the VLS (1pF load)

Figure 11: Testbench for the VLS (1pF load)

 Figure 12: Results of the VLS

The internal caps are kept at 1pF and the PMOS are replaced with NMOS in the schematic. The resultant waveform
shows that when a 0-1 Volt signal is applied at the input a 2-3 volt signal is achived.

b. 3 pF

Figure 13: Schematic for VLS (3 pF load)

 Figure 14: Testbench for the VLS (3pF load)

Figure 15: VLS Results (3pF) load)

To drive a load of 3 pF, the internal capacitance of 1 pF was not enough. That is why the internal caps are increased
up to 10 pF which can be seen in the schematic.
c. 5 pF

Figure 16: Schematic for VLS (5pF load)

Figure 17: Testbench for VLS (5pF load)

 Figure 18: results (5 pF load).

To drive a load of 3 pF, the internal capacitance of 1 pF was not enough. That is why the internal caps are increased
up to 20 pF which can be seen in the schematic.

d. 10 pF

Figure 19: Schematic VLS (10 pF load)

 Figure 20: Testbench for VLS (10 pF load)

Figure 21: Results of VLS (10pF load)

To drive a load of 3 pF, the internal capacitance of 1 pF was not enough. That is why the internal caps are increased
up to 30 pF which can be seen in the schematic.
2. Design a Non-overlapping clock that has a period of 40ns and 0-0 overlapping
time of 5ns.

Figure 22: Schematic for the non-overlapping clock (40 ns period)

Figure 23: Testbench for the non-overlapping clock (40 ns period)

 Figure 24: results of 40 ns period non-overlapping clock

From the schematic it can be seen that that the NOR gates used are 2 time weaker than the normal nor gate. The
weaker gates are used such that we increase the 0-0 overlapping time up to 5 ns as desired in the problem. From the
above results it is evident that a non-overlapping clock of 40 ns is achieved having almost 5 ns 0-0 overlapping time.
3. Design a Voltage level Translator that translates an input signal from 0-3 V to 0-1 V.

Figure 25: Schematic for voltage translator

Figure 26: Testbench of the voltage translator

 Figure 27: Results of the voltage shifter

The desired voltage translator can be designed in 2 ways by manipulating the voltage level translator designed in the
lab task # 2. The 1st method is to cascade a buffer having VDD of 1V. The 2nd method is changing the reference voltage
to 1V as performed here which can be seen from the testbench shown in figure 26. The results are shown in figure 27.
The output waveform is shown in solid blue which has voltage level of 0-1 V. While the input clocks are shown in
dotted line having voltage levels of 0-3 V.
4. Simulate and discuss the function of the circuit shown below, where A is the input and Y is the
output.

Figure 28: Schematic of the task 4

Figure 29: Testbench of the Task 4

 Figure 30: Output waveform of the Task 4.

When the circuit given in task 4 was simulated, it was found out that it is a very good voltage translator. It has
many advantages over the normal voltage translator as it doesn’t use any capacitor which is very big plus
point of this translator. It’s voltage translating capabilities are much better as can be seen from the output
waveforms that we get a very smooth output as compared to the common translator. The disadvantage is
that it is a bit complex to design and use more transistor as compared to common translator design.

Conclusion: In this lab we designed multiple types of voltage level shifter and translators. A non-overlapping clock
generator was also simulated and then redesigned in the assignment task for a given time period and 0-0 overlapping
period. In the assignment part, Voltage level shifter for multiple loads were also designed. A voltage Translator from
0-3V ti 0-1 V was also designed. In the last part of assignment, a new sophisticated kind voltage translator was analyzed
and discussed.