LAB 6

Switch Capacitor Circuits Layout Design

and Post Layout Simulations
Name: Mudassir Ali
Roll No.: 21i-2425
Section: IC Design
Date: March 25,2022
Subject: Mixed Signal IC Design
Submitted to: Google Classroom
 Assignments

1. Layout the Non-Overlapping clock and do the DRC, LVS, PEX and post-layout
simulation to verify the results. (Compare the schematic and post-layout simulation
results)

Figure 1: Schematic of the non-overlapping clock

Figure 2: Test bench for the non-overlapping clock

Figure 3: Layout of the non-overlapping clock
Figure 4: DRC simulation results of the non-overlapping clock

Figure 5: LVS simulation result of the non-overlapping clock

 Figure 6: PEX simulation results of the no-overlapping clock

Figure 7: Comparison of pre and post layout results of the non-overlapping clock

The 1st 2 waveforms in the above figure shows the results of non-overlapping clock. The pre-layout
simulation results are shown in dotted lines while the post layout simulations are shown in solid line.
It can be observed from the waveforms that the results are almost same except a slight delay in post
layout simulations.
2. Layout the Inverting Delay-free Insensitive Switch Capacitor Integrator and do the
DRC, LVS, PEX and post-layout simulation as well to verify the results. (Compare
the schematic and post-layout simulation results).

Figure 8: Schematic of the Delay Free SC Integrator

Figure 9: Testbench for the delay free SC Integrator

 Figure 10: Layout of the Delay free SC Integrator

Figure 11: DRC Simulation results of the SC Integrator

The above CSR, Density and PP layer errors can be ignored at this phase.
 Figure 12: LVS simulations of SC Integrator

The above property Errors are due to the use of MIMCaps. These property errors can be ignored and
we can proceed to PEX Simulations.

Figure 13: PEX Simulations results of SC Integrator

 Figure 14: Pre and post layout results of the integrator

The above waveforms shows the post and pre layout output results of the delay free SC Integrator.
The post layout results are shown in dotted lines while the pre-layout results are shown in dotted-
dashed lines. The results are almost same except a slight deviation can be seen both the results.

3. Conclusion: In the lab we made the layouts of the non-overlapping clock and delay free SC
integrator. Both of the circuits were designed in the previous labs. The pre and post layout
simulations of the both circuits were also compared in this lab.