J Comput Electron (2018) 17:138–145
https://doi.org/10.1007/s10825-017-1056-x
Design and analysis of a gate-all-around CNTFET-based SRAM
cell
G. Saiphani Kumar1 · Amandeep Singh1 · Balwinder Raj1
Published online: 22 September 2017
© Springer Science+Business Media, LLC 2017
Abstract This paper proposes a highly stable and low
power 6-T static random access memory (SRAM) cell design
using a gate-all-around carbon nanotube field effect transis-
tor (GAA-CNTFET). The 6-T SRAM cell is designed and
analyzed in HSPICE for different performance metrics viz.
SNM, read SNM, write SNM, delay, and leakage power for
both the top gate CNTFET and the GAA-CNTFET. The
effect of variation of the power supply voltage on the leakage
current is also presented, and it was found that the GAA-
CNTFET accounts for low power dissipation at higher supply
voltage. The 6-T SRAM cell is analyzed for different flat
band conditions of the p-type CNTFET taking flatband of the
n-type as constant, which is called a dual flat band voltage
technique. Through simulations, it is found that by increasing
the flatband voltage of a p-type CNTFET, the SRAM gives
better performance. The dual flatband variation technique is
compared with dual chirality technique, and it is observed
that both techniques give the same results.
Keywords Top gate carbon nanotube field effect transistor ·
Gate-all-around carbon nanotube field effect transistor ·
SRAM · Flatband · Noise margin
B Amandeep Singh
amandeepsingh.ec.13@nitj.ac.in
G. Saiphani Kumar
phani.sai22@gmail.com
Balwinder Raj
rajb@nitj.ac.in
1 Department of Electronics and Communication, National
Institute of Technology, Jalandhar, Punjab 144011, India
123
1 Introduction
With aggressive shrinking of technology at a fast rate,
dimensional scaling of silicon-based devices has entered the
nanometer scale regime [1]. At 32 nm, the problem of leak-
age current become severe, and the device becomes more
sensitive to process parameter variations due to short channel
effects (SCE). Therefore, by scaling the device beyond the
32 nm technology node [2], circuit designers are faced with
several challenges, such as degradation in mobility, threshold
voltage variation, increase in leakage current, and difficulty
in increasing ON current (ION ). In order to overcome these
challenges, several materials and devices have been investi-
gated in recent years, namely nanowire FETs, tunnel FETs,
graphene FETs, and MoS2 FET [3–7]. Carbon nanotubes
(CNTs) have many advantages over these novel materials
for various reasons, e.g. aggressive channel length scaling
due to the absence of mobility degradation [8,9]; variable
bandgap within a single material [10]; ultra-thin body that is
possible due to smaller diameter (1–3 nm) [11]; compatibil-
ity of CNT with high-K materials [12]; and less sensitivity
to process parameter variation [13]. This leads to the novel
device concept of the carbon nanotube field effect transistor
(CNTFET), which shows excellent characteristics for logic
applications [14].
Basically, there are two types of CNTFETs: Schottky
barrier CNTFETs (SB-CNTFETs) and conventional doped
CNTFETs [15]. In SB-CNTFETs, the CNTs are not doped
and hence form Schottky contacts with metals at the source
and drain sides, while with the introduction of doping, would
result in ohmic contacts and is known as a conventional CNT-
FET. However, based on the type of geometry, CNTFETs
can be grouped into two categories: planar and coaxial. In
the planar geometry, the CNTFET can be a top gate (TG-
CNTFET) [16,17], a bottom gate (BG-CNTFET) [18,19], or
J Comput Electron (2018) 17:138–145
a double gate (DG-CNTFET) [20,21]. The coaxial geometry
consists of a gate-all-around CNTFET (GAA-CNTFET), in
which the gate is wrapped around a cylindrical CNT [22–24].
Both the planar and coaxial geometries work based on the
same physics, i.e. a 1-dimensional density of states (DOS)
and ballistic transport [25,26]. However, the coaxial geome-
try is of great interest due to its better electrostatics over the
planar geometry. The coaxial geometry maximizes capacitive
coupling between the gate and the CNT channel resulting in
more induced charge in the channel. Also, a coaxial geome-
try provides better channel control over the leakage current,
making them more suitable for low power applications.
Because of this, there is on-going research for the develop-
ment of TG-CNTFET and GAA-CNTFET based Verilog-A
SPICE models, e.g. the Stanford CNTFET model [27]
for TG-CNTFET devices and the Stanford virtual-source
carbon nanotube field effect transistor model [28] for GAA-
CNTFET devices. Much work is reported for various circuit
applications based on a TG-CNTFETs [29], but there is need
to explore GAA-CNTFET for circuit applications due to var-
ious advantages.
A lot of work has been performed in TG-CNTFET-based
SRAM cell design [30–32] using a top gate CNTFET model
file. Until now, to the best of our knowledge, there is no
SRAM cell design with a GAA-CNTFET reported in the
literature. This paper proposes a GAA-CNTFET based 6-T
SRAM cell design in HSPICE using the Verilog-A Stan-
ford virtual-source carbon nanotube field effect transistor
model [28]. A GAA-CNTFET based SRAM cell is compared
with the TG-CNTFET, and it is found that the GAA-CNTFET
based SRAM provides better noise margins along with low
power dissipation as compared to the TG-CNTFET based
SRAM. Analysis is done to choose the best value of the
pull-ratio to avoid a read upset problem and the cell ratio
to avoid a write upset problem. In addition to a dual chi-
rality scheme [33,34], a dual flatband scheme is proposed,
which consists of different flat band voltages of p-type and n-
type CNTFETs. It has been demonstrated that a dual flatband
scheme gives better results as compared to a dual chirality
scheme. The paper is organised as follows: Sect. 2 explains
the two different geometries along with their characteristics.
Section 3 compares the design of a 6-T SRAM cell with
TG-CNTFET and GAA-CNTFET geometries along with the
effect of pull ratio and cell ratio on bit storage. A dual flat-
band scheme is implemented in Sect. 4, and comparison is
done with the dual chirality scheme. Lastly, conclusions are
drawn in Sect. 5.
2 CNTFET geometries and their characteristics
Figure 1 shows the typical planar TG-CNTFET structure. In
this type, an intrinsic CNT channel is controlled by a top gate
139
Gate Gate
Contact Oxide
Source Drain
Contact Contact
CNTs
SiO2
Substrate
Fig. 1 Cross-sectional view of TG-CNTFET device structure
Gate Gate
Contact Oxide
Source Drain
Contact Contact
SiO2 CNTs
Substrate
Fig. 2 Cross-sectional view of the GAA-CNTFET device structure
insulated with SiO2 , and heavily doped CNTs form ohmic
contacts with the source and drain metal contacts. Here, a
CNT sits on the insulator; therefore, the substrate acts as
a fourth terminal. Figure 2 shows the structure of a GAA-
CNTFET. In this structure, cylindrical CNTs are wrapped by
the cylindrical gate and the source and drain contact with
SiO2 as the insulator. The CNTs are heavily doped at the
source and drain sides, making them conventional CNTFETs.
The GAA-CNTFET is stuck on the substrate, but due to
proper insulation through the SiO2 , the substrate terminal
can be neglected, hence making it a three-terminal device.
Although a GAA-CNTFET shows better electrostatics as
compared to the planar CNTFET, the fabrication of the GAA-
CNTFET is a complex task. However, the fabricated GAA-
CNTFET has been reported and shows good characteristics
[35]. The fabrication steps can be explained using Fig. 3 as
follows. (1) Growing a SiO2 layer on the silicon substrate:
the first process is to grow SiO2 layer on a silicon substrate
by an oxidation process; (2) suspension of the CNTs for the
wrap-up process: the most important step is to suspend the
single wall CNT in order to form the coaxial structure. In this
process, CNTs are functionalized with alternate exposure to
NO2 gas and trimethylaluminum vapour, which makes the
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140 J Comput Electron (2018) 17:138–145

Growing SiO2 Suspension of CNTs Deposition of gate Metal contact at

layer on silicon for wrap up process oxide material gate and
substrate source/drain sides

Fig. 3 Flowchart for GAA-CNTFET device fabrication

9 1.E-05

GAA-CNTFET GAA-CNTFET
7.5 1.E-06
TG-CNTFET
TG-CNTFET 1.E-07
6
1.E-08
IDS (μA)

IDS (A)
4.5
1.E-09
237.5mV
3
1.E-10
125.5mV
1.5 1.E-11

0 1.E-12
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
VDS (V) VGS (V)

Fig. 4 IDS –VDS characteristics of a (16,0) GAA-CNTFET and a Fig. 5 IDS –VGS characteristics of a (16,0) GAA-CNTFET and a
TG-CNTFET at VGS = 0.5 V TG-CNTFET at VDS = 0.5 V

wrap-up process possible [36]; (3) deposition of gate oxide

material: the next step is to deposit gate oxide material (SiO2 )
over the CNT by atomic layer deposition (ALD) followed by
chemical etching of gate oxide other than the gate region;
(4) metal contacts: the last step is to deposit the gate metal
contact on the oxide material and source/drain metal contacts
using ALD. The metal deposited here is aluminium with a
work function 4.1 eV.
Figures 4 and 5 show the IDS –VDS and IDS –VGS character-
istics of the TG-CNTFET and GAA-CNTFET respectively.
These characteristics are plotted in HSPICE using Verilog-
A CNTFET models, i.e. the Stanford CNTFET model [27]
for the TG-CNTFET device and the Stanford virtual-source
carbon nanotube field effect transistor model [28] for the
GAA-CNTFET device. Figures 4 and 5 are plotted by extract-
ing data from the log file after simulating the netlist file, which
includes the CNTFET device model and its parameters in
HSPICE. To plot the IDS –VDS characteristics, dc analysis is
performed by sweeping VDS from 0 to 0.5 V and fixing VGS
at 0.5 V. Similarly, for plotting the IDS –VGS characteristics,
dc analysis is performed by sweeping VGS from 0 to 0.5 V
and fixing VDS at 0.5 V.
It is clear from the comparison in Fig. 4, that the ON cur-
rent (ION ) for the GAA-CNTFET is three times more than
the TG-CNTFET. This is because the capacitive coupling
between the gate and the CNT channel is maximized in the
case of the GAA-CNTFET. However, this capacitive cou-
pling leads to some undesirable effects, namely (a) increased
OFF current (IOFF ), (b) threshold voltage (VTH ) roll off,
and (c) drain-induced barrier lowering (DIBL). These effects
can be clearly seen through transfer characteristics of TG-
CNTFET and GAA-CNTFET as shown in Fig. 5. The IOFF
for a GAA-CNTFET is on the order of 10−10 and 10−12 for
a TG-CNTFET. VTH is calculated by using the constant cur-
rent method with the current value taken as 10−8 A, that is
the minimum current required to turn ON the device. For
the GAA-CNTFET, the value of VTH is found to be 125.5
and 237.5 mV for the TG-CNTFET as from Fig. 5, which
clearly shows the VTH roll off. These undesirable effects can
be improved by increasing the equivalent oxide thickness
using high-k dielectric as the gate oxide.
3 The 6-T SRAM cell design
The 6-T CNTFET SRAM cell structure is shown in Fig. 6.
It consists of two cross-coupled inverters along with two
NCNTFET pass transistors (M5 and M6) that are connected
to bit lines (BL and BLB). The structure is the same as a con-
ventional MOSFET structure with the MOSFET replaced by
a CNTFET. A word-line (WL) is used to activate the access
transistors in order to read and write values at the node LOUT
and ROUT. Scaling of the CNTFETs is necessary to main-
tain proper voltage levels at these nodes, so that the read and
write upset problem are avoided.

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J Comput Electron (2018) 17:138–145 141

300

GAA-CNTFET
250
TG-CNTFET

200

VROUT (mV)
150

100

50

0
0 0.5 1 1.5 2 2.5
Pull-ratio

Fig. 6 CNTFET based 6-T SRAM cell Fig. 7 Pull-ratio versus rise voltage at ROUT

400
3.1 Read operation GAA-CNTFET
350
TG-CNTFET
Read operation can be defined when the logic value stored 300
at node LOUT is read by the BL through pass transistor
250
VLOUT (mV)

M5. During the read operation, M1 and M5 are in operation,

while M2 is not active; therefore, proper scaling of M1, M3,
M5, and M6 is required to define the pull-ratio (M1/M5 and
M3/M6). The requirement is to keep the voltage less than VTH
at the node storing “0” during the read operation. Simulations
are performed for the read operation by storing “1” at LOUT
and “0” at ROUT for different pull-ratios. Figure 7 shows
the voltage rise at node ROUT with different pull-ratios for
TG-CNTFET and GAA-CNTFET. It is clear from Fig. 5 that
VTH for the (16,0) TG-CNTFET is 0.237 V and the GAA-
CNTFET is 0.125 V, corresponding to the different values
of threshold voltages for TGCNTFET and GAA-CNTFET,
the scaling of pull ratio is done. It is clear from Fig. 7 that
a pull-ratio greater than 0.8 would result in a voltage less
than VTH at the ROUT node for the GAA-CNTFET. Unlike
a MOSFET, the CNTFET can be scaled by varying number
of tubes instead of the width of the device. For fair analysis,
the pull-ratio is selected as 1.6 by taking eight tubes for M1
and M3 and five tubes for M5 an M6.
3.2 Write operation
Write operation can be defined when the new logic value is
over written from BL at node LOUT through pass transistor
M5. During the write operation M2 and M5 are in operation,
while M1 is not active; therefore, proper scaling of M2, M5,
M4, and M6 is required to define the cell ratio (M2/M5 and
M2/M6). The requirement is to keep the voltage less than
VTH at the node storing “1”, and “0” is overwritten during
the write operation. Simulations are performed for the write
operation by storing “1” at LOUT and writing “0” as new data
200
150
100
50
0
0 0.2 0.4 0.6 0.8 1
Cell-ratio
Fig. 8 Cell ratio versus write voltage at LOUT
for different cell ratios. Figure 8 shows the write voltage at
node LOUT with different cell ratios for TG-CNTFET and
GAA-CNTFET. It is clear from Fig. 8 that a cell ratio less
than 0.38 would result in voltage less than VTH at the LOUT
node for the GAA-CNTFET. The cell ratio is selected in such
a way that the voltage at LOUT is much less than VTH . For
fair analysis, the cell ratio is selected as 0.2 by taking 1 tube
for M2 and M4.
Simulations are performed for both the TG-CNTFET and
GAA-CNTFET based 6-T SRAM cell in HSPICE, taking
the power supply as 0.5 V. For comparison purposes, VTH
for both types should be the same; therefore, VTH of the TG-
CNTFET is matched with the GAA-CNTFET by varying the
flatband voltage. First, simulations are performed to compare
the noise margins. The simplest method to measure the noise
margins is by plotting a butterfly curve, which results from
the voltage transfer curve (VTC) of the two cross-coupled
inverters. The VTC of one inverter is plotted with the inverse

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142 J Comput Electron (2018) 17:138–145

(a) (b)
0.6 0.6
GAA-CNTFET TG-CNTFET
0.5 0.5

0.4 0.4

VROUT
VROUT
0.3 0.3

0.2 0.2

0.1 0.1

0 0
0 0.2 0.4 0.6 0 0.2 0.4 0.6
VLOUT VLOUT

Fig. 9 Butterfly plot of SNM for a GAA-CNTFET, b TG-CNTFET

(a) 0.6 (b) 0.6

GAA-CNTFET TG-CNTFET
0.5 0.5

0.4 0.4
VROUT

VROUT
0.3 0.3

0.2 0.2

0.1 0.1

0 0
0 0.2 0.4 0.6 0 0.2 0.4 0.6
VLOUT VLOUT

Fig. 10 Butterfly plot of RSNM for a GAA-CNTFET, b TG-CNTFET

(a) 0.6 (b) 0.6

GAA-CNTFET TG-CNTFET
0.5 0.5

0.4 0.4
VROUT

VROUT

0.3 0.3

0.2 0.2

0.1 0.1

0 0
0 0.2 0.4 0.6 0 0.2 0.4 0.6
VLOUT VLOUT

Fig. 11 Butterfly plot of WSNM for a GAA-CNTFET, b TG-CNTFET

VTC of the second inverter to obtain a butterfly curve. Fig-
ure 9 shows the butterfly plot of the GAA-CNTFET and the
TG-CNTFET based on the SRAM cell for the static mode, i.e.
when SRAM cell is storing the data. This is plotted with the
ideal VTC of inverter that is storing data. Similarly Figs. 10
and 11 shows the butterfly plot for the read and write mode,
i.e. during reading and writing of the data on the SRAM
cell. The butterfly plot of RSNM is similar to SNM with lit-
tle change as access transistors are ON for read mode and
from this, the RSNM value decreases from SNM. However,
the butterfly plot for WSNM is totally different as the data
are totally overwritten in this state with new values. This is

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J Comput Electron (2018) 17:138–145 143

Table 1 Comparison of the (16,0) TG-CNTFET and GAA-CNTFET based 6-TSRAM performance parameters at 0.5 V power supply
CNTFET type N- P- SNM RSNM (mV) WSNM (mV) Read Write Leakage
CNTFET CNTFET (mV) delay (ps) delay (ps) power
threshold threshold (nW)
voltage voltage
(mV) (mV)

TG-CNTFET 125.5 −10.5 170 80 200 1.03 2.77 3.86

GAA-CNTFET 125.5 −10.5 187.5 87.5 205 7.88 87.4 3.75

why the WSNM value is highest among all noise margins. 600
584.3 GAA-CNTFET
Noise margins can be calculated by measuring the side of the
500
longest square that can be fitted between the mirrored butter-

Leakage power (nW)

fly curves. The measured values are highlighted in Table 1.
400
It can be concluded from the results that the GAA-CNTFET
based SRAM cell gives better noise margins. The change in 300
noise margins is attributed to threshold voltage and ON cur-
rent. Since the threshold voltage of both devices here is kept 200
the same, the difference is clearly due to high ON current in
the case of the GAA-CNTFET as depicted in Fig. 5. 100
48.31
The next performance parameters are read delay and write 4.05 3.79 3.77 3.75 3.72
delay, which are calculated by measuring the time taken by 0
1 0.9 0.8 0.7 0.6 0.5 0.4
the cell to read and write the data successfully. It is found that
Power supply (V)
the GAA-CNTFET is slower than the TG-CNTFET, which
is due to the large capacitances. The last important parameter Fig. 12 Power supply versus leakage power for the (16,0) GAA-
is the leakage power consumption, and it is calculated during CNTFET
static operation of the cell. It is found that the leakage power
800
consumption is almost the same for the 0.5 V power supply.
749.4 TG-CNTFET
But there is a greater impact of power supply on the power 700
consumption, and due to this, the leakage power is calcu-
600
Leakage power (nW)

lated at different power supplies for both the GAA-CNTFET

and TG-CNTFET, as shown in Figs. 12 and 13, respectively. 500
It is concluded from the results that at higher power sup-
400
ply, the GAA-CNTFET based SRAM cell accounts for much
lower leakage power consumption than TG-CNTFET based 300 257.9
SRAM.
200

100
32.78 4.67 3.87 3.86 3.85
0
4 SRAM cell design by dual chirality and dual flat 1 0.9 0.8 0.7 0.6 0.5 0.4
band Power supply (V)

To achieve a highly stable SRAM cell along with low
power, a multi-threshold voltage based SRAM cell design is
widely gaining attention [37,38]. In the CNTFET, this can be
achieved by using dual chirality, which consists of CNTFETs
with different diameters resulting in multi-threshold volt-
ages. The dual chirality CNTFET based SRAM cell design
provides a low power SRAM cell along with high stability
[33]. The dual chirality scheme is implemented on a GAA-
CNTFET based 6-T SRAM cell. It is already reported that
there is negligible effect of varying the diameter of n-type
CNTs [33], hence simulations are performed for variation of
Fig. 13 Power supply versus leakage power for the (16,0) TG-
CNTFET
the p-type diameter only. Dual chirality is represented by the
triplet index with (p, n, 0), i.e. the first variable represents
the chirality for p-type and the second for n-type. Table 2
highlights the various performance parameters of the GAA-
CNTFET based SRAM using the dual chirality scheme.
Although the dual chirality scheme gives better results,
controlled chirality is the challenge for CNT fabrication [39].
The other method to change the threshold voltage is to change

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144 J Comput Electron (2018) 17:138–145

Table 2 Performance parameters of the (16,0) GAA-CNTFET based 6-T-SRAM with the dual chirality method at 0.5 V power supply
Chirality N- P- SNM (mV) RSNM (mV) WSNM (mV) Read Write Leakage
CNTFET CNTFET delay (ps) delay (ps) power
threshold threshold (nW)
voltage voltage
(mV) (mV)

(11,16,0) 125.5 −303 200 7 105 7.94 63.32 0.008

(13,16,0) 125.5 −210 195 70 235 7.93 64.36 0.0733
(16,16,0) 125.5 −125.5 195 70 212.5 7.86 74.4 0.324
(19,16,0) 125.5 −70 195 90 170 7.88 93.33 0.767
(22,16,0) 125.5 −30 192.5 100 152.5 7.88 105.46 2.28

Table 3 Performance parameters of the (16,0) GAA-CNTFET based 6-T-SRAM with the dual flatband method at 0.5 V power supply
Flat band voltage (V) N- P- SNM RSNM (mV) WSNM (mV) Read Write Leakage
CNTFET CNTFET (mV) delay (ps) delay (ps) power
threshold threshold (nW)
voltage voltage
(mV) (mV)

Vfbn = 0.015
Vfbp = −0.2 125.5 −310.5 200 7 235 7.84 64.6 19.6098
Vfbn = 0.015 125.5 −210.5 198 50 222.5 7.86 68.2 0.263
Vfbp = −0.1
Vfbp = 0.015 125.5 −125.5 195 70 212.5 7.88 74.4 0.324
Vfbp = −0.015
Vfbn = 0.015 125.5 −10.5 187.5 87.5 205 7.88 87.4 3.75
Vfbp = 0.1
Vfbn = 0.015 125.5 89.5 165 82.5 187.5 7.92 91.35 88.22
Vfbp = 0.2

the flatband voltage. Flat band voltage is defined as the work
function difference between the metal and semiconductor
interface in the absence of fixed charge in the insulator.
Hence, the flatband voltage can be changed by using dif-
ferent metals at the gate contact. The threshold voltage is
directly proportional to the flat band voltage. Thus, in order
to increase the threshold voltage, a metal with a greater work
function be used and vice versa. It is already clear from
Table 2 that the dual chirality results in a dual threshold
and gives better results than a single threshold based SRAM.
Table 3 shows the various performance parameters of the
GAA-CNTFET based SRAM using then the dual flatband
scheme. It can be concluded that at the same threshold volt-
ages in both the schemes, the results are comparable.
different performance metrics against a top gate CNT-
FET (TG-CNTFET). It has been demonstrated that the
GAA-CNTFET based SRAM provides better noise mar-
gin along with lower power dissipation as compared to the
TG-CNTFET based SRAM. The potential benefit of the
GAA-CNTFET based SRAM is lower power dissipation,
even at high voltage power supply with the same noise mar-
gins. Analysis is performed for different sizes of SRAM cells
to remove the read and write upset problems. Lastly, the
SRAM cell is analyzed by applying a dual flatband scheme
and a dual chirality scheme, and the results show that dual
flatband gives the same performance as the dual chirality
scheme.

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