Computer Organization and

Architecture

Chapter 3
Top Level View of Computer
Function and Interconnection

Lecture 2
 Course Content in Lectures

• Chapter 1 - Introduction

• Chapter 2 - Computer Evolution and Performance

• Chapter 3 - Computer Function and Interconnection

• Chapter 4 - Computer Arithmetic

• Chapter 5 - Instruction Sets: Characteristics and Functions

• Chapter 6 - Instruction Sets: Addressing Modes and Formats

• Chapter 7 - Processor Structure and Function

2
Program Concept
• Hardwired systems
are inflexible
• General purpose
hardware can do
different tasks, given
correct control
signals
• Instead of re-wiring,
supply a new set of
control signals
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals

• We have a computer!
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
– e.g. jump
• Combination of above
Example
• The processor contains a single data
register, called an accumulator (AC). Both
instructions and data are 16 bits long.
Thus, it is convenient to organize memory
using 16-bit words. The instruction format
provides 4 bits for the opcode, so that
there can be as many as 24 = 16 different
opcodes, and up to 212 = 4096 (4K) words
of memory can be directly addressed.
Example
•
Question

Given a hypothetical machine that has five memory and I/O

instructions:
0001 = Load AC from memory
0010 = Store AC to memory
0011 = Load AC from I/O
0111 = Store AC to I/O
0101 = Add to AC from memory

In these cases, the 12-bit address identifies a particular I/O device.

Show the content of IR for the following:
1. Load AC from I/O device 5. 𝟑𝟎𝟎𝟓 → 𝑰𝑹
2. Add contents of memory location 940. 𝟓𝟗𝟒𝟎 → 𝑰𝑹
3. Store AC to I/O device 6. 𝟕𝟎𝟎𝟔 → 𝑰𝑹
Example of Program Execution

• Example of a program fragment that adds the contents

of the memory word at address 940 to the contents of
the memory word at address 941 and stores the result
in the latter location.
Question

• Expand the previous example to show content of MAR

and MBR?
Instruction Cycle State Diagram
Example
•
Question
• Consider a hypothetical 32-bit microprocessor
having 32-bit instructions composed of two
fields: the first byte contains the opcode and the
remainder the immediate operand or an operand
address.
—What is the maximum directly addressable
memory capacity (in bytes)?
—Discuss the impact on the system speed if the
microprocessor bus has
– a 32-bit local address bus and a 16-bit local data
bus, or
– a 16-bit local address bus and a 16-bit local data
bus.
—How many bits are needed for the program
counter (PC) and the instruction register (32)?
Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
• Classes of Interrupts
—Program
– e.g. overflow, division by zero
—Timer
– Generated by internal processor timer
– Used in multi-tasking
—I/O
– from I/O controller
—Hardware failure
– e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Connecting
• All the units must be connected
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
Computer Modules
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
Input/Output Connection(1)
• Similar to memory from computer’s
viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
—Send data to computer
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Thank You
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