Multistage CMOS Amplifiers: Analytical Case Studies in Frequency Compensation

Multistage CMOS Amplifiers
Analytical Case Studies in Frequency Compensation
Uday Dasgupta
g o1 + scp1 + YC 0 −YC V1 −g m1 Vi
[ −g m2 g o2 + scp2 + YD −YD ] [V2 ] = [ 0 ]
−YC g m3 − YD GL + sCL + YC + YD Vo 0
IMASOL
An IMASOL Publication
Multistage CMOS Amplifiers
Analytical Case Studies in Frequency Compensation
Uday Dasgupta
IMASOL
An IMASOL Publication
Published by IMASOL, June 2022, Singapore
imasol681@gmail.com
Copyright reserved by author
ISBN 978-981-18-4087-6
Revision 1, 1 June 2022
Revision 2, 1 July 2022
National Library Board, Singapore Cataloguing in Publication Data

Name(s): Dasgupta, Uday.
Title: Multistage CMOS amplifiers : analytical case studies in frequency
compensation / Uday Dasgupta.
Description: Singapore : IMASOL, 2022.
Identifier(s): ISBN 978-981-18-4087-6 (PDF)
Subject(s): LCSH: Operational amplifiers--Design and construction. | Operational
amplifiers--Mathematical models. | Electronic circuit design.
Classification: DDC 621.3815--dc23
The book was submitted to National Library Board, Singapore for legal deposit.
Opening Pages Dedication, Preface, Ack., Contents
Dedication
To the loving memory of my parents, especially my mother who always encouraged me to

further my knowledge.
To Kalyanbrata Chakraborty, D. Litt., Indologist who inspired and encouraged me to write,

leading by example with his own publications.
To all practicing engineers and students who wish to explore a bit further.
3
Multistage CMOS Amplifiers – Analytical Case Studies in Frequency Compensation
Reviewer’s Opinion
“I strongly recommend this book to all involved in analog CMOS circuit design. In particular,
this is an excellent must-have reference book on CMOS amplifiers for practicing engineers
and graduate students.
This book provides many good design examples and gives a detailed comparison of CMOS
amplifiers with different circuit topologies and frequency compensation techniques. It
provides a good glimpse of CMOS amplifier design approaches developed over the past four
decades.
This book has shown that mathematical and theoretical analysis of amplifier design is still
possible and manageable via realistic approximations. The theoretical approach can help to
provide additional insights into the underlying working mechanisms of the CMOS amplifier
circuits which can be further exploited by the designer.”
Tan Khen Sang, PhD.
Formerly
Director, Institute of Microelectronics (A-STAR), Singapore.
Senior Advisor Executive Office, MediaTek Singapore Pte. Ltd.
4
Preface
Operational Amplifiers have been studied almost since the birth of electronics itself. In
today’s Digital world, it is one of the very few Analog entities to survive. In this book we
look at this resilient building-block from a new angle. Intended to be a reference book for
graduate students and practicing engineers, it is hoped that it provides something to add to
their existing knowledge.
No CAD tool or any kind of specialised software, except those mentioned in the next page,
was used to prepare the material in this book. This renders it suitable for a multidisciplinary
audience.
The book is available only in electronic format (pdf) for use in desktops, laptops, and tablets.
It is wrapped up in a folder containing individual chapters/components in separate pdf files.
This arrangement permits the reader to view several chapters/components simultaneously on
different windows. A single pdf file version is also included in the folder.
Though sufficient care has been exercised to keep the material provided accurate, it is
possible that some errors remain. I shall be grateful if those are pointed out via the email
address imasol681@gmail.com. Comments and suggestions are also welcome.
Uday Dasgupta
June 2022, Singapore.
5
Acknowledgements
(1) I am indebted to several of my ex-colleagues as technical interaction with them played an

important role in the writing of this book.
(2) I am grateful to Dr. Tan Khen Sang for spending time reviewing the book and providing
his considered opinion.
(3) This book was entirely composed with Microsoft Office 365, using Word for text, tables,
equations and pdf conversion, PowerPoint for diagrams and Excel for plots.
(4) Google web search was used to find necessary background information.
(5) Wikipedia was consulted as it came up in some of the above Google searches.
6
Contents
Opening Pages 1
Title page 1
Dedication 3
Reviewer’s Opinion 4
Preface 5
Acknowledgements 6
Contents 7
Chapter 1. Introduction 13
1.1. Blitzkrieg of Integrated Circuit Process Technology 13

1.2. Evolution of Linear and Mixed-Signal Integrated Circuits 13
1.3. Considerations in Embedded Operational Amplifier Design 14
1.4. Objective and Scope 15
1.5. Organisation 16
Chapter 2. Relevant Mathematical Methods and Concepts 17
2.1. Obtaining the Amplifier Transfer Function 17

2.2. Factorising the Transfer Function Polynomials 21
2.3. Gain Crossover Point for the Transfer Function 26
2.4. PZL Parameters and Amplifier Design 27
Chapter 3. Single-Stage Amplifier 36
3.1. Introductory Notes 36

3.2. Circuit Analysis and Transfer Function 37
3.3. Poles and Zeros of the Transfer Function 39
3.4. Design to Meet Specifications 39
3.5. Concluding Remarks 45
Chapter 4. Two-Stage Amplifier with Miller Compensation 46

Chapter 5. Two-Stage Amplifier with Cascode-Miller Compensation 57

7
Chapter 6. Three-Stage Amplifier with Nested Miller Compensation 75

Chapter 7. Three-Stage Miller Compensated Amplifier with Active Feedforward

around Centre-Stage 89

Chapter 8. Three-Stage Miller Compensated Amplifier with Passive Feedforward

around Centre-Stage 102

Chapter 9. Three-Stage Cascode-Miller Compensated Amplifier with Passive

Feedforward around Centre-Stage 116

Chapter 10. Three-Stage Amplifier with Centre-Stage Miller Compensation 132

Chapter 11. Two-Stage Miller Compensated Amplifier with Active Feedforward 143

8
Chapter 12. Three-Stage Nested Miller Compensated Amplifier with Active

Feedforward 154

Chapter 13. Four-Stage Double Nested Miller Compensated Amplifier with Active
Feedforward 166

Chapter 14. Two-Stage Amplifier with Non-Miller Active Feedforward

Compensation 180

Chapter 15. Three-Stage Amplifier with Non-Miller Active Feedforward

Compensation 190

Chapter 16. Four-Stage Amplifier with Non-Miller Active Feedforward

Compensation 202

Appendix 1. Symbols and Notations 215
A1-1. Mathematical notations 215

A1-2. Frequency and related parameters/variables 215
A1-3. Circuit parameters and signal voltages 216
A1-4. Performance parameters 216
A1-5. PZL and other parameters/variables 216
A1-6. Circuit symbols/notations 217
9
Appendix 2. Useful Results Pertaining to Magnitude Response 218
A2.1. Deviation of Gain Crossover Frequency from ω0 due to Close-In Poles/Zeros 218
A2.2. Magnitude Response Peaking due to Damping Factor of Complex Pole Pair 222
Appendix 3. Formulae for Plots in Chapter 3 224
A3.1. Frequency Response from the Transfer Function 224

A3.2. Plotting the Unity Feedback Factor Loop-Gain Responses 224









10




Appendix 17. Categorized Comparison of Amplifiers 250

A17-1. Single-Stage amplifier 250
A17-2. Two-Stage amplifiers 250
A17-3. Three-Stage amplifiers 250
A17-4. Four-stage amplifiers 250
Appendix 18. Hypothetical Process Technology ABC 251
A18-1. ABC CMOS process technology data 251
Appendix 19. Units and Prefixes 252
A19-1. Symbols/abbreviations for units and related information 252

A19-2. Symbols for unit-prefixes and related information 252
Bibliography 253
R1. Papers 253

R2. Books 253
R3. Datasheets 254
Index 255
A, B, C 255
C, D, E, F, G, I 256
L, M, N, O, P 257
R, S, T, V, Z 258
11
The space in this page is left intentionally blank.
12
Chapter 1 Introduction Hst., Obj., Scp., Org.
Chapter 1
Introduction
1.1. Blitzkrieg of Integrated Circuit Process Technology
Since Jack Kilby’s (Texas Instruments, February 1959) and Robert Noyce’s (Fairchild
Semiconductor, July 1959) invention of the Monolithic Integrated Circuit, semiconductor
process technology for the same has made its advances in leaps and bounds. Speaking of
miniaturization only, starting from a minimum feature size of a few tens of micro-meters
back in the 1960s we are now at a few tens of nano-meters and that is an astounding
thousand-fold reduction in just above half a century’s time.
It goes without saying that during this period the active and passive devices in integrated
circuits too went through a series of evolutionary processes. Talking of transistors only, we
saw Bipolar devices first, followed by PMOS, NMOS, and finally CMOS devices. Following
that, we did see Bipolar and CMOS devices being integrated on the same semiconductor
substrate, but that trend did not quite catch up. CMOS was back again because it offered high
enough operating speeds with down-scaling while using a relatively simple process
technology.
1.2. Evolution of Linear and Mixed-Signal Integrated Circuits
Linear (or analog) circuits were the first type to be realized in integrated form, beginning with
the ubiquitous Operational Amplifier. The first of those being mass produced was A702, a
brainchild of Bob Widlar (Fairchild Semiconductor, 1964). Various improved versions of this
circuit followed in about a decade’s time, spearheaded by several individuals working for
several companies. A few pioneering ones being A709 (Bob Widlar, Fairchild
Semiconductor, 1965), LM101 (Bob Widlar, National Semiconductor, 1967), A741 (Dave
Fullagar, Fairchild Semiconductor, 1968), MC1556 (Solomon, Davis and Lee, Motorola
Semiconductor, 1969), LM108 (Bob Widlar, National Semiconductor, 1969), A725 (George
Erdi, Fairchild Semiconductor, 1969), OP05 (George Erdi, Precision Monolithics Inc., 1972)
and OP07 (George Erdi, Precision Monolithics Inc., 1975) [R2-11,12].
During this space of time other types of linear integrated circuits like voltage followers and
voltage regulators were invented too. The process technology for all the above was all-
Bipolar, CMOS entering the scene much later. The process technology for the latter was
developed at Fairchild Semiconductor in 1963. However, the invention was commercially
exploited by Radio Corporation of America (RCA) in the latter half of the 1960s. They used
CMOS devices to implement ultra-low power digital circuits and semiconductor memories.
Subsequently, the company introduced the pioneering CD4000 series CMOS digital logic
family in 1968. To seamlessly interface analog signals at the input and output of an
application with this new digital logic family, RCA further introduced CA3130 in 1974 and
an improved version CA3140 shortly afterwards.
13
Multistage CMOS Amplifier – Analytical Case Studies in Frequency Compensation
CA3130 is presumably the first commercial operational amplifier to use CMOS devices along
with Bipolar devices on the same semiconductor substrate [R3-1]. We can safely assume the
era of CMOS linear integrated circuits began around the introduction of CA3130. As the
tremendous integration potential of CMOS process technology became apparent, CMOS
linear circuits with operational amplifier at the core got embedded in applications containing
analog and digital functions instead of being implemented stand-alone like the older Bipolar
linear integrated circuits. Since then, several companies notably Motorola, Texas Instruments
and Analog Devices in the United States; Philips, SGS-Thompson/ST Microelectronics and
Siemens/Infineon in Europe; Toshiba, Hitachi and Mitsubishi in Japan have been churning
out several complex CMOS integrated mixed-signal applications on a regular basis.
1.3. Considerations in Embedded Operational Amplifier Design
The characteristics of CMOS devices have been changing with technology down-scaling. The
output resistances degraded significantly, though the transconductances improved. However,
the increase in transconductance was unable keep up with the reduction in output resistance
and, therefore, the voltage amplification factor or voltage gain [R2-2] per device has been
dropping all along. The ability of the CMOS device to operate with voltage stress has also
been going down with down-scaling, necessitating lower power supply voltages and
abolishment of stacked-up devices or cascodes [R2-9]. Thus, available gain per stage for
CMOS amplifiers have been going down steadily with the years.
Operational Amplifiers are nearly always operated with negative feedback. The important
performance parameters of a such a feedback amplifier depend heavily on its open-loop gain
[R2-1,2,8]. Though two-stage designs were good enough for quite some time since their
inception, more stages are now required to obtain the same amount of open-loop gain and, in
turn, the same level of closed-loop performance [R2-10].
It is well known that Operational Amplifiers need frequency compensation, or simply

compensation to guarantee stable operation under negative feedback. For this purpose, some
additional components are added to the basic amplifier converting it to what is known as a
compensated amplifier. These components alter the poles and zeros of the uncompensated
amplifier. Though the stability of the amplifier can be ensured, some performance parameters
of the uncompensated amplifier are invariably sacrificed. It is also well known that addition
of more stages makes the problem of compensating the amplifier more complex [R2-2,8,10].
Only two broad categories of compensation techniques are feasible for application in an
embedded amplifier [R2-10]. The compensation for the first category shapes the amplifier
frequency response with just one pole (and no zero) below the unity-gain frequency. Known
as dominant pole compensation (a special case of phase-lag compensation), it can be used to
design unconditionally stable amplifiers. Frequency shaping for the second category is done
using multiple poles and zeros (one less than the number of poles) below the unity-gain
frequency. These amplifiers can be designed to have more 3-dB bandwidth but may
sometimes be only conditionally stable. This type of compensation is known phase-lead
compensation [R2-1,2,8,10].
14
1.4. Objective and Scope
It must be obvious by now that embedded CMOS Operational Amplifiers or simply CMOS
Amplifiers, as they are known today, are the subjects of study in this book. At least two
books [R2-9,10] were published with similar titles. These books focus more on circuit design
principles, compensation techniques in general and implementation of a few specific
amplifier types. On the other hand, this book focuses on mathematical analysis and
theoretical design of some compensated amplifier types available in the literature.
Today’s integrated circuit design is a complex task because the circuits, and more
importantly, the MOS device models have become increasingly complex with down-scaling.
Therefore, engineers and researchers in this field must depend heavily on computer
simulation. We are aware of the downside of this practice. Simulation gives us the ultimate
answer with sufficient accuracy but leaves us with little clue of the underlying mechanisms
taking place. However, we are left with little choice since conducting mathematical analyses
on today’s integrated circuits is a daunting task as well as an impractical proposition.
Nevertheless, we shall show in this book that it is feasible to apply mathematical analyses to
small parts of a complex circuit such as embedded amplifiers. The performance of such an
amplifier is most important in its linear region of operation and at relatively low frequencies.
Therefore, analyses based on simplified low-frequency small-signal models [R2-2] for the
MOS devices can ensure reasonably accurate results. However, realistic approximations must
be made, wherever necessary, to keep the equations and results manageable and simple. For a
theoretical design based on the results of analysis, small-signal parameter values from the
circuit simulator may be obtained and used. Usage of square-law voltage-current relationship
for the MOS device was avoided in this book (except for estimation of cell area) since that
describes a sub-micron MOS device rather poorly. It must also be kept mind that several high
frequency poles and zeros naturally present in simulation was neglected here. Therefore,
results presented in this book differ from simulation results at high frequencies. Additionally,
the design examples presented provide just one solution, not necessarily the most optimum
one. A savvy reader may alter the parameters to obtain a solution of his/her choice.
Mathematical analysis on various compensated amplifiers, using dominant pole as well as

phase-lead compensation, are presented to better understand how the compensation works,
how to adjust MOS device parameters to obtain a desired amount of compensation, what
trade-offs are involved in this process and how various types of compensation compare.
Similar analyses do exist in the literature for a few amplifier types [R1-1-3,5-8,11] but most
are rather sketchy. This book attempts to bridge that gap, providing readers with a systematic
and general approach to address problems in analysis and design of multistage amplifiers.
As discussed in the previous section, an important aspect in the design of an amplifier is the
measure of its stability with negative feedback. This book focuses primarily on that.
However, with some additional thoughts, it should be possible to apply and extend the
methods and results obtained here to other behavioural aspects of the amplifier too. Lastly, it
is recommended to read the chapters in the sequence of their numbers.
15
1.5. Organisation
Chapter 2 explains all necessary mathematical methods with examples, obtaining important
formulae to be used in later chapters. The remaining chapters deal with analysis and design of
various types of amplifiers. Nearly all of those were published and practically realised.
Chapter 3 describes a single-stage amplifier.
Chapter 4 describes the most famous two-stage amplifier with Miller compensation.
Chapter 5 describes a variant of the amplifier in the previous chapter − the two-stage
amplifier with Cascode-Miller compensation.
Chapter 6 describes the classical three-stage amplifier with Nested Miller compensation.
Chapter 7 describes an early three-stage compensation method using Miller compensation

and feedforward around the centre stage.
Chapter 8 describes a pure CMOS version of the amplifier in the previous chapter.
Chapter 9 describes a variant of the amplifier in the previous chapter − the three-stage
amplifier with Cascode-Miller compensation.
Chapter 10 describes a little-known compensation technique for a three-stage amplifier that

uses Miller compensation from the centre stage instead of the output stage.
Chapters 11-13 describe Miller compensation applied to two-stage, three-stage, and four-
stage amplifiers, respectively, using feedforward to position zeros in the amplifier transfer
function.
Chapters 14-16 describe a non-Miller compensation method applied to two-stage, three-stage,

and four-stage amplifiers, respectively, using feedforward to insert zeros in the amplifier
transfer function.
Appendix 1 lists and explains all the textual and circuit symbols used.
Appendix 2 provides analyses to estimate effects of proximity of a pole or a zero to the unity-
gain frequency and response peaking due to damping factor of a complex pole pair.
Appendix 3 to 16 obtain all the formulae required for plotting unity feedback factor loop-gain
magnitude and phase responses of the amplifiers described in the respective chapters.
Appendix 17 provides a performance comparison of all the amplifiers studied in this book.
Appendix 18 provides data for a hypothetical process technology used to estimate the cell
area and power consumption for the amplifiers designed.
Appendix 19 lists and provides information on all the units used and its prefixes.
16
Chapter 2 Mathematical Methods Formulae and Examples
Chapter 2
Relevant Mathematical Methods and Concepts
2.1. Obtaining the Amplifier Transfer Function
Let us consider an arbitrary three-stage amplifier with three nodes having a small-signal
equivalent circuit [R2-2] as shown below:
Fig. 2-1. Small-signal equivalent circuit for an arbitrary amplifier.
In Fig. 2-1, v1, v2 and vo represent the signal amplitudes at nodes N1, N2 and OUT
respectively with respect to the ground reference ‘gnd’. R and C stand for various resistive
and capacitive circuit parameters, while g m1 , g m2 and g m3 stand for transconductance circuit
parameters of the first, second and third stages of the amplifier respectively.
2.1.1. Nodal Equations
Standard analytical methods such as KCL (Kirchoff’s Current Law) based nodal analysis
[R2-2,3] may be applied to find the equations for the circuit in Fig. 2-1 such as:
(G1 + jωC1 + jωCC + yF )v1 − yF v2 − jωCC vo = −g m1 vi (2-1)
−(yF + g m2 )v1 + (G2 + jωC2 + yF )v2 = 0 (2-2)
−jωCC v1 + g m3 v2 + (GL + jωCL + jωCC )vo = 0 (2-3)
In the above equations, G1 , G2 and GL are the conductances of the resistors R1, R2 and R3
respectively and yF the admittance of the series combination of R F and CF such that:
1 1 1 jωC
G1 = R , G2 = R , GL = R and yF = 1+jωCF R (2-4)
1 2 L F F
In Eqs. (2-1) to (2-4), ω represents angular frequency and j = √−1. To find the transfer
function of the amplifier, we take Laplace transforms [R2-1,3,5] of Eqs. (2-1) to (2-4),
neglecting initial conditions, to obtain:
17
(G1 + sC1 + sCC + YF )V1 − YF V2 − sCC Vo = −g m1 Vi (2-5)
−(YF + g m2 )V1 + (G2 + sC2 + YF )V2 = 0 (2-6)
−sCC V1 + g m3 V2 + (GL + sCL + sCC )Vo = 0 (2-7)

1 1 1 sC
G1 = R , G2 = R , GL = R and YF = 1+sCF R (2-8)
1 2 L F F
Here, ‘s’ is the Laplace transform variable and YF, V1, V2, Vo and Vi are the Laplace
transforms of yF, v1, v2, v3 and vi respectively.
2.1.2. Solving the Nodal Equations
Cramer’s rule [R2-3,5,6] provides us with a convenient method for solving a system of linear
equations such as Eqs. (2-5) to (2-7). These equations can be written in vector-matrix form
[R2-1,3,5,6] as:
G1 + sC1 + sCC + YF −YF −sCC V1 −g m1 Vi

[ −YF − g m2 G2 + sC2 + YF 0 ] [V2 ] = [ 0 ] (2-9)
−sCC g m3 GL + sCL + sCC Vo 0
Using the abovementioned rule, we can find Vo from Eq. (2-9) as:
G1 +sC1 +sCC +YF −YF −gm1 Vi
| −YF −gm2 G2 +sC2 +YF 0 |
−sCC gm3 0
Vo = G1 +sC1 +sCC +YF −YF −sCC
| −YF −gm2 G2 +sC2 +YF 0 |
−sCC gm3 GL +sCL +sCC
Using cofactor expansion for the numerator determinant along its third column:
−YF −gm2 G2 +sC2 +YF
−gm1 Vi | |
−sCC gm3
Vo = G1 +sC1 +sCC +YF −YF −sCC
| −YF −gm2 G2 +sC2 +YF 0 |
Whence we arrive at the transfer function as:

−YF −gm2 g2 +sC2 +YF
Vo (s) −gm1 | |
−sCC gm3
Av (s) = = G1 +sC1 +sCC +YF −YF −sCC (2-10)
Vi (s)
| −YF −gm2 G2 +sC2 +YF 0 |
2.1.3. Constitution of the Transfer Function
Expanding the determinants in the numerator and denominator of Eq. (2-10) fully, we obtain
the transfer function of the amplifier in standard form such as:
bm sm +bm−1 sm−1 +⋯+b1 s+1
Av (s) = A0 (2-11)
an sn +an−1 sn−1 +⋯+a1 s+1
18
The constant A0 in Eq. (2-11) is a dimensionless quantity known as the DC amplification or

gain. This interpretation is readily verified by substituting s = 0 in the equation. It may also
be observed that the last terms of the numerator and denominator polynomials in the transfer
function are both equal to unity. Therefore, each of the denominator terms a1 s to an s n and
the numerator terms b1 s to bm s m must also be dimensionless. Since ‘s’ is essentially an
angular frequency, the coefficients a1 and b1 must be time-constants [R2-1] each. Then, each
of a2 and b2 must be products of two time-constants, each of a3 and b3 must be products of
three time-constants and so on. However, the above polynomial coefficients a1 to an and b1
to bm may include a dimensionless quantity (like gain or ratio) as a factor or be a sum of
several time constants or both.
2.1.4. Determinant Expansion, Pre-Conditioning
Let an element of a determinant of order k be represented by 𝑎𝑝𝑞 were, p is the row number
and q the column number. When the determinant is expanded fully using successive cofactor
expansions, 𝑘! terms are generated [R2-4,5,6]. Each such term is the product of exactly k
elements, no two of which have the same p as well as q values. In other words, those are
elements in different rows and columns.
Thus, a determinant of order k needs (𝑘 + 1)! symbols to write in fully expanded form,
assuming one symbol (excluding sign) for an element 𝑎𝑝𝑞 . This exercise requires quite some
space and effort for large values of 𝑘. The problem becomes even more tedious if the
elements 𝑎𝑝𝑞 themselves consist of several terms like those in the determinants of Eq. (2-10).
However, labour involved in reducing Eq. (2-10) to the form of Eq. (2-11) can be alleviated
to some extent if the determinants in its numerator and denominator are pre-conditioned
using Elementary Row/Column Operations [R2-4,5,6] as described below:
Step 1 (break the bridge between nodes 1 and 2)
Replace column 1 by sum of column 1 and column 2 for the numerator determinant. Repeat
the same operation for the denominator determinant. This helps to get rid of the term YF (1-2
node-bridge) from column 1 of both the determinants to yield:
G +sC2 −gm2 G2 +sC2 +YF
−gm1 | 2 |
gm3 −sCC gm3
Av (s) = G1 +sC1 +sCC −YF −sCC
|G2 +sC2 −gm2 G2 +sC2 +YF 0 |
gm3 −sCC gm3 GL +sCL +sCC
Step 2 (break the bridge between nodes 1 and OUT)
Replace column 1 by sum of column 1 and column 3 for the denominator determinant. This
helps to get rid of the term sCC (1-OUT node-bridge) from its column 1 to yield:
G +sC2 −gm2 G2 +sC2 +YF
−gm1 | 2 |
gm3 −sCC gm3
Av (s) = G1 +sC1 −YF −sCC
| G2 +sC2 −gm2 G2 +sC2 +YF 0 |
GL +sCL +gm3 gm3 GL +sCL +sCC
19
Step 3 (remove common factors from columns)
Factor out −g m2 from column 1 and g m3 from column 2 of the numerator determinant. In a
similar operation, factor out G1 , G2 , and GL from columns 1, 2 and 3 respectively of the
denominator determinant to arrive at:
G sC G2 sC Y
1− 2 − 2 + 2+ F
gm2 gm2 gm3 gm3 gm3
gm1 gm2 gm3 | sC g |
C
− m3 1
gm2 gm2
Av (s) = sC Y sC
1+ 1 − F − C
G1 G2 GL
|G2 sC2 gm2 sC2 YF |
G1 G2 GL G + G − G 1+
G
+
G
0
| 1 1 1 2 2 |
GL sCL gm3 gm3 sC sC
+ + 1+ L + C
G1 G1 G1 G2 GL GL
Step 4 (write elements in terms of time-constants and ratios)
Replace all conductances and admittances using Eq. (2-8) to obtain:

sCF
1 sC 1 sC2 gm3
1− − 2 + +
gm1 gm2 gm3 R1 R2 RL || gm2 R2 gm2 gm3 R2 gm3 1+sCF RF ||
sCC gm3
− 1
gm2 gm2
Av (s) = sCF R2
1+sC1 R1 − −sCC RL
1+sCF RF
| R1 sCF R2 |
+sC2 R1 −gm2 R1 1+sC2 R2 + 0
| R2 1+sCF RF |
R1
+sCL R1 +gm3 R1 gm3 R2 1+sCL RL +sCC RL
RL
Step 5 (identify time-constants and ratios in elements)
Note: This step is presented for the convenience of illustration only and may be skipped
while working on a real case.
Write the transfer function obtained above in compact form using Tab. 2-1 below:
Tab. 2-1. Symbols for gain, ratios, and time-constants.
Gain Reciprocal g m -ratio R-ratio C-ratio CR time- C/g m time-

Apq of gain Γpq Υpq Θpq constant constant
Λ pq τpq ζpq
1 gmp Rp Cp Cp
g mp R q Cp R q
gmp Rq gmq Rq Cq gmq
Then, we arrive at:

sζF3
1−Λ22 −sζ22 Λ32 +sζ23 +
| 1+sτFF |
sζC2 −Γ32 1
Av (s) = A11 A22 A3L sτF2
1+sτ11 − −sτCL
1+sτFF
|| sτ ||
Υ12 +sτ21 −A21 1+sτ22 + F2 0
1+sτFF
Υ1L +sτL1 +A31 A32 1+sτLL +sτCL
20
Step 6 (remove element denominators, if any, by factoring out and cancellation)

1
Factor out from column 2 of both numerator and denominator determinants. The two
1+sτFF
factors, being identical, cancel leaving behind:
−sζ22 +1−Λ22 s2 τF ζ23 +s(Λ32 τF +ζ23 +ζF3 )+Λ32
| |
sζC2 −Γ32 sτFF +1
Av (s) = A0 sτ11 +1 −sτF2 −sτCL where,
| sτ21 +Υ12 −A21 s2 τFF τ22 +s(τ22 +τFF +τF2 )+1 0 |
sτL1 +Υ1L +A31 A32 (sτFF +1) sτCL +sτLL +1
A0 = A11 A22 A3L = g m1 g m2 g m3 R1 R 2 R L (2-12)
It may be noted that the elements of numerator and denominator determinants in Eq. (2-12)
are polynomials in ‘s’. It should now be clear now that once the numerator and denominator
determinants of Eq. (2-12) are fully expanded, the transfer function of the circuit in Fig. 2-1,
given by Eq. (2-10), will indeed be a rational polynomial as in Eq. (2-11). For a quick check,
we may set s = 0 in Eq. (2-12) to find A0 to be the DC gain. The expansion process is also
simplified since only polynomial additions and multiplications are involved now.
2.2. Factorising the Transfer Function Polynomials
The next job is to find the poles and zeros [R2-1,2,3] by factorisation of the numerator and
denominator polynomials of a transfer function as in Eq. (2-11). This can be done using one
of the mathematical methods described in the sub-sections below.
2.2.1. Factorisation of Quadratic Polynomials
Let us consider a quadratic polynomial of the form:
𝑃2 (𝑥) = 𝑎2 𝑥 2 + 𝑎1 𝑥 + 𝑎0 (2-13)
The roots of 𝑃2 (𝑥) = 0 are given by:
𝑎1 𝜅1,2 𝑎2 𝑎0
𝑥1,2 = − where 𝜅1,2 = 1 ± √1 − 4 (2-14)
2𝑎2 𝑎12
Then, the factorised form is given by:

𝑎1 𝜅1 𝑎1 𝜅2
𝑃2 (𝑥) = 𝑎2 (𝑥 + ) (𝑥 + ) (2-15)
2𝑎2 2𝑎2
1 2𝑎2 𝑎1 𝜅2,1
Considering reciprocals of the roots = −𝑎 =− , we can also write:
𝑥1,2 1 𝜅1,2 2𝑎0
𝑎 𝜅
1 1 1 2 𝑎 𝜅
𝑃2 (𝑥) = 𝑎0 ( 2𝑎 𝑥 + 1) ( 2𝑎 𝑥 + 1) (2-16)
0 0
Quadratic Transfer Function Polynomials
A quadratic polynomial in the transfer function is of the form:
21
F2 (s) = a2 s2 + a1 s + 1 (2-17)
Real Roots
If the roots of Eq (2-17) are real, then it is written in factorised form using Eqs. (2-13), (2-14)
and (2-16) as:
a1 κ1 a1 κ2 4a2
F2 (s) = (sτ1 + 1)(sτ2 + 1) where, τ1 = , τ2 = and κ1,2 = 1 ± √1 − (2-18)
2 2 a21
Complex Roots
If the roots of Eq (2-17) are complex, then it is left unfactorized but written in a different
form [R2-1,2,3] such as:
1 1 a1
F2 (s) = s 2 τ2n + 2sδτn + 1 where, ωn = τ = and δ = 2 (2-19)
n √a2 √a2
In this case, ωn is known as the natural frequency and δ the damping factor of the roots of
F2 (s). As can be seen from Eqs. (2-18) and (2-19) that the roots are complex if δ < 1 and
real if δ ≥ 1. It can also be verified that ωn is the magnitude of the complex roots.
2.2.2. Factorisation of Polynomials of Degree ≥ 3
Formulae for finding roots of cubic and bi-quadratic equations do exist [R2-4,7] but are too
cumbersome to be used in algebraic analysis. No formulae are available for finding roots of
polynomials with degree higher than 4. Therefore, we need to use alternative methods for
factorisation of polynomials with degree higher than 2.
2.2.3. Approximate Partial Factorisation
Let an nth degree polynomial in the transfer function be described by:
Fn (s) = an s n + an−1 sn−1 + ⋯ + a1 s + 1 (2-20)
Let Fn (s) have roots:

1
sp = h , p = 1,2, … , n (2-21)
p
Using Eq. (2-21), Eq. (2-20) can be written in factorised form as:
Fn (s) = (sh1 + 1)(sh2 + 1)(sh3 + 1) … (shn + 1) (2-22)
2.2.3.1. Polynomials with a Single Small Magnitude Root
In this case, the roots of Fn (s) obey the following:
|s1 | ≪ |s2 |, |s3 |, … , |sn | or |h1 | ≫ |h2 |, |h3 |, … , |hn | (2-23)
Quadratic Polynomial
22
Using n = 2 in Eqs. (2-20) and (2-22):
F2 (s) = a2 s2 + a1 s + 1 = (sh1 + 1)(sh2 + 1) = s2 h1 h2 + s(h1 + h2 ) + 1 (2-24)
Equating coefficients of the quadratic polynomials in Eq. (2-24):
h1 h2 = a2 (2-25)
h1 + h2 = a1 (2-26)
Approximating Eq. (2-26) using Eq. (2-23):
h1 ≈ a1 (2-27)
Using Eq. (2-27) in Eq. (2-25):

a
h2 ≈ a2 (2-28)
1
Using Eqs. (2-27) and (2-28) in Eq. (2-24) we obtain the approximate factorisation formula
for the quadratic polynomial as:
a
F2 (s) = (sh1 + 1)(sh2 + 1) ≅ (a1 s + 1) (a2 s + 1) (2-29)
1
Cubic Polynomial
Using n = 3 in Eqs. (2-20) and (2-22):
F3 (s) = a3 s3 + a2 s 2 + a1 s + 1 = (sh1 + 1)(sh2 + 1)(sh3 + 1)
= s3 h1 h2 h3 + s 2 (h1 h2 + h2 h3 + h1 h3 ) + s(h1 + h2 + h3 ) + 1 (2-30)
Equating coefficients of the cubic polynomials in Eq. (2-30):
h1 h2 h3 = a3 (2-31)
h1 h2 + h2 h3 + h1 h3 = a2 (2-32)
h1 + h2 + h3 = a1 (2-33)
Approximating Eqs. (2-32) and (2-33) using Eq. (2-23):
h1 (h2 + h3 ) ≈ a2 (2-34)
h1 ≈ a1 (2-35)
Using Eq. (2-35) in Eqs. (2-31) and (2-34):

a
h2 h3 ≈ a3 (2-36)
1
a
h2 + h3 ≈ a2 (2-37)
1
23
Using Eqs. (2-24) and (2-35) to (2-37) in Eq. (2-30), we obtain the approximate partial
factorisation formula for the cubic polynomial as:
a a
F3 (s) = (sh1 + 1)[s 2 h2 h3 + s(h2 + h3 ) + 1] ≅ (a1 s + 1) (a3 s 2 + a2 s + 1) (2-38)
1 1
Generalisation
It is possible to generalise Eqs. (2-24) and (2-30) to show the nth degree polynomial described
by Eqs. (2-20) to (2-22) can also be written as Vieta’s formulae [R2-4,6] in another form:
Fn (s) = sn (product of all ′h′s) + sn−1 (sum of products of ′h′s taken n − 1 at a time)
+ sn−2 (sum of products of ′h′s taken n − 2 at a time) + ⋯ + s(sum of all ′h′s) + 1 (2-39)
Using Eqs. (2-20), (2-22), (2-39) and the methods illustrated with quadratic and cubic
polynomials above, it is possible to obtain the approximate partial factorisation formula for
an nth degree polynomial with one small magnitude root as:
a an−1 n−2 a
Fn (s) ≅ (a1 s + 1) (an s n−1 + s + ⋯ + a2 s + 1) provided:
1 a1 1
an an−1 a
a1 ≫ , , … , a2 (2-40)
a1 a1 1
2.2.3.2. Polynomials with Two Small Magnitude Roots
In this case, the roots of Fn (s) obey the following:
|s1 |, |s2 | ≪ |s3 |, |s4 |, … , |sn | or |h1 |, |h2 | ≫ |h3 |, |h4 |, … , |hn | (2-41)
Cubic Polynomial
Approximating Eqs. (2-32) and (2-33) using Eq. (2-41):
h1 h2 ≈ a2 (2-42)
h1 + h2 ≈ a1 (2-43)
Using Eq. (2-42) in Eq. (2-31):

a
h3 ≈ a3 (2-44)
2
factorisation formula for the cubic polynomial as:
a
F3 (s) = [s 2 h1 h2 + s(h1 + h2 ) + 1](sh3 + 1) ≅ (a2 s 2 + a1 s + 1) (a3 s + 1) (2-45)
2
Bi-Quadratic Polynomial
Using n = 4 in Eqs. (2-20), (2-22) and (2-39):
24
F4 (s) = a4 s4 + a3 s 3 + a2 s 2 + a1 s + 1 = (sh1 + 1)(sh2 + 1)(sh3 + 1)(sh4 + 1)
= s4 h1 h2 h3 h4 + s 3 (h1 h2 h3 + h1 h2 h4 + h1 h3 h4 + h2 h3 h4 )
+s 2 (h1 h2 + h1 h3 + h1 h4 + h2 h3 + h2 h4 + h3 h4 ) + s(h1 + h2 + h3 + h4 ) + 1 (2-46)
Equating coefficients of the bi-quadratic polynomials in Eq. (2-46):
h1 h2 h3 h4 = a4 (2-47)
h1 h2 h3 + h1 h2 h4 + h1 h3 h4 + h2 h3 h4 = a3 (2-48)
h1 h2 + h1 h3 + h1 h4 + h2 h3 + h2 h4 + h3 h4 = a2 (2-49)
h1 + h2 + h3 + h4 = a1 (2-50)
Approximating Eqs. (2-48) to (2-50) using Eq. (2-41):
h1 h2 (h3 + h4 ) ≈ a3 (2-51)
h1 h2 ≈ a2 (2-52)
h1 + h2 ≈ a1 (2-53)
Using Eq. (2-52) in Eq (2-47) and (2-51):

a
h3 h4 ≈ a4 (2-54)
2
a
h3 + h4 ≈ a3 (2-55)
2
factorisation formula for the bi-quadratic polynomial as:
F4 (s) = [s 2 h1 h2 + s(h1 + h2 ) + 1][s2 h3 h4 + s(h3 + h4 ) + 1]

a a
≅ (a2 s 2 + a1 s + 1) (a4 s 2 + a3 s + 1) (2-56)
2 2
Generalisation
Using Eqs. (2-20), (2-22), (2-39) and the methods illustrated with cubic and bi-quadratic
polynomials above, it is possible to obtain the approximate partial factorisation formula for
an nth degree polynomial with two small magnitude roots as:
a an−1 n−3 a
Fn (s) ≅ (a2 s 2 + a1 s + 1) (an s n−2 + s + ⋯ + a3 s + 1)
2 a2 2
provided:
a an−1 a
a2 ≫ an , a2
, … , a3 (2-57)
2 2
25
2.2.3.3. Polynomials with ‘m’ Small Magnitude Roots
Generalising the results obtained in Sections 2.2.3.1 and 2.2.3.2 it can be shown that the
approximate partial factorisation formula for an nth degree polynomial described by Eqs. (2-
20) to (2-22) with ‘m’ small magnitude roots is given by:
a an−1 n−m−1 am+1
Fn (s) ≅ (am s m + am−1 s m−1 + ⋯ + a1 s + 1) (a n s n−m + s + ⋯+ s + 1)
m am am
provided:
a an−1 am+1
am ≫ a n , ,…, (2-58)
m am am
2.3. Gain Crossover Point for the Transfer Function
2.3.1. Transfer Function in terms of Poles and Zeros
With the numerator and denominator polynomials factorised, an arbitrary four pole, two zero
amplifier transfer function may be written using Eqs. (2-18) and (2-19) to be:
A0 (sτz1 +1)(sτz2 +1)
Av (s) = (sτ 2 τ2 +2sδ
(2-59)
p1 +1)(sτp2 +1)(s p34 p34 τp34 +1)
The subscripts 1, 2, 3 and 4 are assigned in the ascending order of magnitudes of the poles
and likewise for zeros. τz1 , τz2 are the time-constants (or reciprocals) corresponding to real
zeros ωz1 , ωz2 whereas, τp1 , τp2 are the same to real poles ωp1 , ωp2 . For the complex pole
pair ωp34 , the corresponding time-constant (or reciprocal) is τp34 while δp34 is the damping
factor. In fact, the above are negated values or magnitudes of poles/zeros (corner frequencies
[R2-1,3]) but we shall still call those poles/zeros [R2-2] as it is commonly done.
2.3.2. The Unity-Gain Frequency
Unity-gain (or gain crossover) frequency ωc of an amplifier transfer function is the angular
frequency at which its magnitude (or gain) is unity. It is an important parameter connected
with the stability of the amplifier. Substituting s = jωc [R2-1,2,3] in Eq. (2-59) we obtain:
A0 (1+jωc τz1 )(1+jωc τz2 )
Av (jωc ) = (1+jω 2 2 (2-60)
c τp1 )(1+jωc τp2 )(1−ωc τp34 +2jωc δp34 τp34 )
We can solve for ωc from Eq. (2-60) by equating the magnitude of its RHS with unity. It is
clear that ωc is a function of the poles and zeros of the amplifier but finding an exact formula
is not possible in most cases since the equation is nonlinear. Therefore, we need to linearise
the problem by assuming that the poles and zeros are located far away from ωc . Under that
condition the dB-magnitude plot of the transfer function crosses the 0 dB horizontal line at a
rate of −20 dB per decade and a phase of −900 [R2-1,2,3].
We shall identify the unity-gain frequency for the abovementioned linearised, ideal condition
with a different symbol ω0 . Normally, ωc and ω0 are quite close but may differ in various
situations to be discussed in later sections. In the next sub-section, we shall find a formula for
ω0 using the linearisation technique mentioned above.
26
2.3.3. Formula for Unity-Gain Frequency
For convenience, we shall use the amplifier in Eq. (2-59) as an example. It is general enough
and results for other amplifiers can be deduced from those for this one.
Dominant Pole Compensation
For this case, the distribution of the poles and zeros is described by:
ωz1 , ωz2 , ωp2 , ωp23 ≫ ω0 and ωp1 ≪ ω0 (2-61)
Eq. (2-61) can be written as:
ω0 τz1 , ω0 τz2 , ω0 τp2 , ω0 τp34 ≪ 1 and ω0 τp1 ≫ 1 (2-62)
Equating magnitude [R2-1] of Eq. (2-60) with ωc = ω0 to unity and using Eq. (2-62):
A0 |1+jω0 τz1 ||1+jω0 τz2 | A0 (1)(1) A0
1 = |Av (jω0 )| = |1+jω 2 2 ≅ |jω =ω
0 τp1 ||1+jω0 τp2 ||1−ω0 τp34 +2jω0 δp34 τp34 | 0 τp1 |(1)(1) 0 τp1
Thus, we find:
A
ω0 = τ 0 = A0 ωp1 and generalising this result:
p1
ω0 = (DC gain)(first pole) (2-63)
Phase-Lead Compensation
For this case, the distribution of the poles and zeros is described by:
ωz2 , ωp23 ≫ ω0 and ωp1 , ωp2 , ωz1 ≪ ω0 (2-64)
Eq. (2-64) can be written as:
ω0 τz2 , ω0 τp34 ≪ 1 and ω0 τp1 , ω0 τp2 , ω0 τz1 ≫ 1 (2-65)
Equating magnitude [R2-1] of Eq. (2-60) with ωc = ω0 to unity and using Eq. (2-65):
A0 |1+jω0 τz1 ||1+jω0 τz2 | A0 |jω0 τz1 |(1) A0 τz1
1 = |Av (jω0 )| = |1+jω 2 2 ≅ |jω =ω
0 τp1 ||1+jω0 τp2 ||1−ω0 τp34 +2jω0 δp34 τp34 | 0 τp1 ||jω0 τp2 |(1) 0 τp1 τp2
Thus, we find:
A τ A0 ωp1 ωp2
ω0 = τ 0 τz1 = and generalising this result:
p1 p2 ωz1
(DC gain)(product of poles below ω0 )

ω0 = (2-66)
(product of zeros below ω0 )
2.4. PZL Parameters and Amplifier Design
In this section we describe a design method that puts the criterion of stability at the foremost.
27
It allows quick evaluation of the measure of stability and, thus, requires less iterations.
2.4.1. The Concept
Introducing PZL Parameters
Stability of a feedback amplifier depends on how its poles and zeros are located with respect
to ω0 . For the amplifier as in Eq. (2-59) to be stable, we have determined some such
relationships as in Eqs. (2-61) and (2-64) for two different types of compensation schemes.
However, for a practical design it necessary to satisfy these relationships with realistic
margins replacing inequalities with equations. This can be done using a few parameters
which we name as Pole Zero Locator (PZL) parameters. Discussions in this as well in the
following sub-sections will show that, apart from easing the amplifier design process, these
parameters can be used to circumvent problems of working with transfer function
polynomials of higher degree which cannot be factorised.
Amplifier Design using PZL Parameters
The PZL parameters can be defined suitably to relate poles and zeros of the amplifier with
ω0 , replacing inequalities as in Eqs. (2-61) and (2-64) with equations. An equation to
calculate a measure of stability such as phase margin [R2-1,2] may then be formed in terms
of these parameters. Next, the parameters can be assigned suitable values to obtain decent
measures of stability using the stability equation. This will ensure, to a large extent, that the
inequalities in Eqs. (2-61) and (2-64) have been satisfied with realistic margins.
Expressions for poles and zeros can be found in terms of circuit parameters (like resistance,
capacitance, and transistor transconductance) from the transfer function using the
factorisation methods described in Section 2.2. Thus, a set of equations connecting PZL
parameters and ω0 with circuit parameters can be formed. We have seen in Section 2.3.3 that
ω0 is a function of poles and/or zeros and, therefore, a function of circuit parameters. Key
circuit parameters like transistor transconductances can then be obtained in terms of other
circuit parameters by solving the abovementioned equations and using the PZL parameter
values assigned previously. Some of the other circuit parameters may be free or may be
determined from additional factors or may have been already specified. Thus, values for
every circuit parameter can be determined.
2.4.2. Defining PZL Parameters
There could be many ways to define PZL parameters, the process being somewhat subjective.
But once defined, we must stick to that definition. Some pole and/or zero may be related to
some other pole and/or zero in a known manner. In that case, a lower number of parameters
may be defined to eliminate redundant equations. PZL parameters need not be defined for
poles and zeros which are known to be located far away from ω0 since their contributions to
the stability equation are relatively fixed (either nearly 900 or nearly 00 phase margin).
Therefore, as many different PZL parameters will be needed as the number of unrelated poles
28
or zeros near and around ω0 . Care should also be taken so that such a process does not lead to
inconsistent equations [R2-5,6] to be solved.
PZL Parameters for Dominant Pole Compensation
For the amplifier described by Eqs. (2-59) and (2-61) we may write:
ω0
ωp1 = using Eq. (2-63) as it is a low-frequency far-away pole and,
A0
ωz1 = λω0 , ωz2 = μω0 , ωp2 = ρω0 , ωp34 = σω0 (2-67)
Where, λ, μ, ρ and σ are PZL parameters. If, for example, it is known that ωp2 is a high-
frequency far-away pole, then ρ need not be used. Instead, ωp2 could be related to ω0 using
circuit parameters.
PZL Parameters for Phase-Lead Compensation
For the amplifier described by Eqs. (2-59) and (2-64) we may write:
ω ω ω ω
ωp1 = A 0ω z1 , ωp2 = A 0ω z1 using Eq. (2-66) as those are low-frequency far-away poles and,
0 p2 0 p1
ωz1 = λω0 , ωz2 = μω0 , ωp34 = σω0 (2-68)
Where, λ, μ and σ are PZL parameters.
2.4.3. Locating Zeros of Unfactorized Transfer Function Polynomials
We illustrate the method using a cubic transfer function polynomial F3 (s) which cannot be
factorised to find zeros explicitly using the any of the methods described in Section 2.2.
F3 (s) = a3 s3 + a2 s 2 + a1 s + 1 (2-69)
Eq. (2-69) can be written in factorised form as:
F3 (s) = (sτ1 + 1)(s2 τ223 + 2sδ23 τ23 + 1) (2-70)
Defining PZL parameters to locate zeros of F3 (s) with magnitude ω1 and ω23 relative to ω0 :
1
ω1 = τ = σω0 (2-71)
1
1
ω23 = τ = μω0 (2-72)
23
Substituting Eqs. (2-71) and (2-72) in Eq. (2-70), multiplying and rearranging:
1 2δ 1 2δ 1
F3 (s) = s 3 σμ2 ω3 + s 2 (σμω
23 23
2 + μ2 ω2 ) + s (μω + σω ) + 1 (2-73)
0 0 0 0 0
Comparing coefficients of Eq. (2-73) with those of Eq. (2-69) we arrive at the following
equations:
29
1
a3 = (2-74)
σμ2 ω30
2δ 1
a2 = σμω232 + μ2 ω2 (2-75)
0 0
2δ 1
a1 = μω23 + σω (2-76)
0 0
Now, a1 , a2 , a3 and ω0 are functions of circuit parameters. After assigning values to σ and μ
to locate ω1 and ω23 as desired, Eqs. (2-74) to (2-76) can be solved to find key circuit
parameters in terms of other circuit parameters and the design can be completed as described
in Section 2.4.1. Thus, by using this method, a full factorisation of a transfer function
polynomial can be circumvented. It should be evident from the above example that this
method can be extended for application in higher degree polynomials.
2.4.4. Forming the Stability Equation
We shall use phase margin ϕm to form the stability equation as it is simpler to do so. In the
chapters to follow we shall see there are no poles in the right half s-plane for the transfer
functions under our consideration and right-half s-plane zeros are far-away high-frequency
ones. Therefore, phase margin alone should be a good first-hand indicator of the amplifier
stability [R2-1]. Thus, ϕm in terms of PZL parameters will form our stability equation with
which design can proceed. We shall look at gain margin Gm in the next sub-section.
Phase Margin with Unity Feedback Factor
With unity feedback factor (transfer function of the feedback path is unity), feedback signal
from the amplifier undergoes a fixed phase shift of −1800 because of subtraction from input
signal. Therefore, a maximum of another −1800 of phase shift is allowed through the
amplifier at the unity-gain frequency before the overall loop phase shift reaches the critical
value of −3600 or 00 and instability sets in. Thus, phase margin with unity feedback factor is
the amplifier phase shift relative to −1800 at the unity-gain frequency. Thus:
Phase margin = (amplifier phase shift at ω0 ) −(−1800 ) and that implies:
Phase margin = 1800 + (amplifier phase shift at ω0 ) = 1800 + 〈Av (jω0 )〉 (2-77)
Using Eq. (2-60) with ωc = ω0 in (2-77), phase margin ϕm of the amplifier in (2-59) with
unity feedback factor [R2-1] is given by:
ϕm = 1800 + tan−1(ω0 τz1 ) + tan−1(ω0 τz2 ) − tan−1(ω0 τp1 ) − tan−1(ω0 τp2 )
2ω0 δp34 τp34

− tan−1 ( ) (2-78)
1−ω20 τ2p34
Stability Equation for Dominant Pole Compensation
Using Eq. (2-67) in Eq. (2-78), we find the stability equation or, in other words, phase margin
for the amplifier in Eq. (2-59) in terms of PZL parameters as:
30
1 1 1 2σδp34
ϕm = 1800 + tan−1 ( ) + tan−1 ( ) − tan−1(A0 ) − tan−1 ( ) − tan−1 ( ) (2-79)
λ μ ρ σ2 −1
Stability Equation for Phase-Lead Compensation
Using Eq. (2-68) in Eq. (2-78), we find the stability equation or, in other words, phase margin
for the amplifier in Eq (2-59) in terms of PZL parameters as:
1 1 A0 ωp2 A0 ωp1 2σδp34
ϕm = 1800 + tan−1 (λ) + tan−1 (μ) − tan−1 ( ) − tan−1 ( ) − tan−1 ( )
ωz1 ωz1 σ2 −1
(2-80)
2.4.5. Assigning Values to PZL Parameters
We refer to Eqs. (2-79) and (2-80) for the discussions in this sub-section.
Suitable PZL Parameter Values
It must be obvious by now that the values for PZL parameters are positive real numbers.
These values help to locate the poles/zeros relative to ω0 . Assigning unduly large PZL
parameter values to locate poles and zeros far above ω0 (in the case of dominant pole
compensation) would cause ϕm to approach an ideal value of 900. However, that would also
result in unacceptably large power consumption since abnormally large device
transconductances would then have to be realized. Similarly, assigning unduly small
parameter values to locate zeros far below ω0 (in the case of lead compensation) would also
result in ϕm to be nearly 900 but large resistors and capacitors, consuming precious real-
estate, would then be needed.
Proximity of Poles and Zeros to 𝜔0
The PZL parameters, therefore, must be assigned values to locate poles/zeros in the vicinity
of ω0 so that an acceptable ϕm value may be obtained for the budgeted power and area
consumption. However, poles/zeros should not be located too close to ω0 . That, apart from
resulting in poor stability, would grossly invalidate the assumptions we made in obtaining
formulae for ω0 in Section 2.3.3. Consequently, ωc will differ from ω0 and the stability
equation may fail to predict ϕm with reasonable accuracy.
Analyses in Appendix 2.1 investigate the effects of proximity of single poles/zeros to ω0 .

The results may be used as guidelines for assigning PZL parameter values. However, those
are not accurate enough for cases of multiple poles/zeros near ω0 .
The Problem of Approximation
Apart from the proximity of poles/zeros to ω0 , there is one other reason why ωc may differ
from ω0 . That is caused by the errors introduced in approximating the transfer function while
finding poles/zeros, as discussed in Section 2.2.3. If the poles/zeros are inaccurate by
themselves, one cannot expect ω0 to be accurate since it is a function of poles/zeros.
31
Locating a Pole and a Zero near 𝜔0 in Dominant Pole Compensation
In case of dominant pole compensation, zeros can help to compensate for ϕm loss due to
poles beyond ω0 but can cause problems under certain conditions. A zero located
immediately after ω0 causes the magnitude curve to go essentially parallel to, while
remaining slightly below, the frequency axis at higher frequencies. In that case ωc could
exceed ω0 , invalidating the ϕm figures obtained from the stability equation in turn.
If there is a real pole beyond the abovementioned zero, that would improve the situation
somewhat and the overall result may be acceptable. But if a complex pole pair with small
damping factor is located beyond the zero, then there is a possibility of the magnitude curve
going up, crossing the frequency axis, and coming down again [R1-3]. This multiple crossing
of the frequency axis could cause severe stability problems [R2-1].
There are less problems if a pole, real or complex, is located between ω0 and a zero instead.
However, that will cause the ϕm figures to be worse. Therefore, to obtain good ϕm figures
and to minimise the possibility of multiple gain crossovers at the same time, it is
recommended to locate the zero as close to the pole as possible. Analyses in Appendix 2.2
investigate the effects of damping factor of a complex pole pair on the magnitude response.
As these results suggest, it is best to have a damping factor no less than 0.5.
2.4.6. Design Completion and Evaluation
Once all the PZL parameters are decided, a good estimate of ϕm can be obtained from the
stability equation. If the result is not satisfactory, another set of the parameters may be tried.
Thus, the stability equation serves as a useful tool for appropriately locating poles/zeros
around ω0 and, therefore, in the design of the amplifier. As described in Section 2.4.1, the
circuit parameter values can be calculated from the final set of PZL parameters and that
completes the first phase of the design process.
Subsequently, the calculated value of ω0 and ωc obtained from the magnitude plot (described
in the next sub-sections) need to be compared. Discrepancies between the two will also be
reflected in the comparative ϕm results. For large discrepancies, alternative PZL parameter
values locating the poles/zeros further away from ω0 may be tried. If that does not help
much, then inaccuracies due to approximations mentioned in the previous section are likely to
be responsible. In practical designs, some such discrepancies may be acceptable.
Unity Feedback Factor Loop-Gain Magnitude and Phase Plots
After the design is completed, we need to evaluate the design using magnitude and phase
plots of the transfer function. To put it more accurately, we shall plot the magnitude and
phase of the loop-gain when the amplifier is used with unity feedback factor (transfer
function of the feedback path is unity). As we proceed further, it will be evident that these
plots are relatively easy to interpret and compare.
Since the feedback factor is unity, the magnitude of the loop-gain is identical to that of the
amplifier transfer function itself. Therefore, dB magnitude of the unity feedback factor loop-
32
gain for the amplifier in Eq. (2-59) can be found by setting s = jω in the equation and finding
the magnitude in dB [R2-1] to obtain:
AvdB (ω) = 20log|Av (jω)| = 20log(A0 ) + 10log(1 + jω2 τ2z1 ) + 10log(1 + jω2 τ2z2 )
2
−10log(1 + jω2 τ2p1 ) − 10log(1 + jω2 τ2p2 ) − 10log [(1 − ω2 τ2p34 ) + 4ω2 δ2p34 τ2p34 ] (2-81)
Furthermore, the phase of the unity feedback factor loop-gain is always 1800 at low
frequencies. This happens because of subtraction of the feedback signal from the input signal.
If the signal is applied at the inverting instead of non-inverting input terminal of an amplifier,
a negative sign appears along with A0 in its transfer function. However, that sign is irrelevant
for loop gain considerations since appropriate input terminals would be used in an application
to ensure negative feedback. Therefore, the phase of the unity feedback factor loop-gain for
the amplifier in Eq. (2-59) can be found by discarding any negative sign associated with A0 ,
setting s = jω in the equation and finding the phase [R2-1] to obtain:
Φv (ω) = 1800 + 〈Av (jω)〉 = 1800 + tan−1(ωτz1 ) + tan−1(ωτz2 ) − tan−1 (ωτp1 )
2ωδp34 τp34
− tan−1 (ωτp2 ) − tan−1 ( ) (2-82)
1−ω2 τ2p34
The unity feedback factor loop-gain magnitude and phase responses can be plotted using Eqs.
(2-81) and (2-82). Plots for other feedback factors, including frequency dependent ones, can
be obtained simply by modifying the amplifier transfer function multiplying the feedback
path transfer function with it.
Phase Margin and Gain Margin from the Unity Feedback Factor Loop-Gain Plots
In line with the discussions in section 2.3, ωc can be found from the loop-gain dB magnitude
plot to be the frequency at which the curve crosses the 0dB horizontal line. Phase margin ϕm
can be found from the loop-gain phase plot to be the phase at the frequency ωc . This will be
evident if we compare Eq. (2-82) with Eqs. (2-77) and (2-78). Thus:
ϕm = Φv (ωc ) (2-83)
The frequency at which the loop-gain phase curve crosses the 00 horizontal line is the phase
crossover frequency ωπ . Gain margin Gm can be found from the loop-gain dB magnitude plot
to be the amount in dB by which the curve falls below the 0dB horizontal line at ωπ [R2-1,2].
Thus:
Gm = 0 − AvdB (ωπ ) = −AvdB (ωπ ) (2-84)
Amplifiers with Passive, Frequency Independent Feedback Factors
A passive, frequency independent block β in the feedback path [R2-2] of a feedback

amplifier has its transfer function or feedback factor values in the range 0 ≤ β ≤ 1. In our
discussions so far, β had a value of 1. We shall now consider cases with all values of β with
the transfer function modified to βAv (s).
33
The relationship between β and the amplifier closed-loop DC gain Acl0 is given by the
famous equation [R2-2]:
1
Acl0 ≅ β provided |Av | ≫ 1 (2-85)
The loop-gain magnitude plot AvdB (ω, β) is given, using Eqs. (2-81) and (2-85) by:
AvdB (ω, β) = 20log|βAv (jω)| = 20log|Av (jω)| + 20log(β)
≅ AvdB (ω) − 20log(Acl0 ) (2-86)
Therefore, the loop-gain magnitude curve shifts vertically down as β changes from 1 to 0 or,
in other words, Acl0 changes from 1 to A0 (approximately).
The loop-gain phase plot Φv (ω, β) is given, using Eq. (2-82), by:
Φv (ω, β) = 1800 + 〈βAv (jω)〉 = 1800 + 〈Av (jω)〉 + 〈β〉 = Φv (ω) (2-87)
This happens because the block β is frequency independent and 〈β〉 = 0. Therefore, the loop-
gain phase curve remains unchanged as β changes from 1 to 0.
Unconditionally Stable Amplifiers
Let us consider β = 1 to start with. In most cases, the loop-gain magnitude curve AvdB (ω)
given by Eq. (2-81) is a decreasing function of frequency. If ωπ > ωc then both ϕm and Gm
have positive values and, therefore, the amplifier is stable for β = 1. This includes cases in
which phase crossover does not take place and, therefore, no value for Gm can be found.
As β decreases, the loop-gain magnitude curve AvdB (ω, β) given by Eq. (2-86) shifts down
causing the gain crossover frequency to go down below ωc . If the loop-gain phase curve
Φv (ω, β ) given by Eq. (2-87) is a decreasing function too, both ϕm and Gm go up (or remain
unchanged) and, therefore, remain positive. This means this amplifier is stable for any value
of Acl0 between 1 and A0 (approximately) and is said to be unconditionally stable [R2-1,10].
This behaviour is typical of amplifiers using dominant pole compensation. Examples of such
amplifiers can be found in Chapters 3 to 9 and 11 to 13.
Conditionally Stable Amplifiers
We begin with β = 1 as before. If ωπ < ωc but ϕm has a positive value, then there may be
two phase crossover frequencies ωπ1 < ωπ2 < ωc as the loop-gain phase curve Φv (ω) given
by Eq. (2-82) crosses the 00 horizontal line twice. Obviously, the amplifier is not
unconditionally stable. We need to examine the stability of such an amplifier for different
values of β to check for which values it is stable and which values it is not.
From the discussions in the previous sub-sections, we know the gain crossover frequency for
AvdB (ω, β) goes down with β while the phase crossover frequencies ωπ1 and ωπ2 for
Φv (ω, β) remains unchanged.
34
For those β values the gain crossover frequencies are below ωπ1 we have both ϕm and Gm
positive with ωπ1 serving as the phase crossover frequency, indicating a stable condition.
For those β values the gain crossover frequencies are above ωπ2 we have both ϕm and Gm
positive (or ϕm positive but no value for Gm as phase crossover does not take place),
indicating a stable condition too.
For those β values the gain crossover frequencies are ωπ1 and ωπ2 exactly, we have both ϕm
and Gm to be 0, indicating instability.
For those β values the gain crossover frequencies are between ωπ1 and ωπ2 we have ϕm
negative though Gm positive, ωπ2 serving as the phase crossover frequency, indicating
instability too.
The closed-loop DC gain values Acl01 and Acl02 corresponding to gain crossover at
ωπ1 and ωπ2 can be found, using Eq. (2-86), to be:
AvdB (ω, β) = AvdB (ω) − 20log(Acl0 ) = 0
Using ω = ωπ1 , ωπ2 in the solution for the above:
20log(Acl01 ) = AvdB (ωπ1 ) and 20log(Acl02 ) = AvdB (ωπ2 ) (2-88)
From the discussions above and Eq. (2-88) we conclude that such an amplifier is
conditionally stable [R2-1,10] for any Acl0 value in dB between 0 and 20log(A0 ) except for
those between and inclusive of AvdB (ωπ1 ) and AvdB (ωπ2 ) (approximately).
This behaviour can sometimes, if not always, be observed in amplifiers using phase lead
compensation. Examples of such amplifiers can be found in Chapters 10 and 14 to 16.
It is worth mentioning here that there are other factors, apart from reduction in β, that can
cause AvdB (ω) to go down. If the amplifier output reaches the power supply rails,
nonlinearity may force AvdB (ω) to drop down to 0dB causing instability to set in at
frequencies between and inclusive of ωπ1 and ωπ2 .
Rest of the space in this page is left intentionally blank.
35
Chapter 3 Single-Stage Amplifier Load Capacitor
CHAPTER 3
Single-Stage Amplifier
3.1. Introductory Notes
Employing Alan Blumlein’s invention of the long-tailed pair (filed 1936, patented 1938) as
the transconductance provider and Bob Widlar’s invention of the current mirror (conceived
1964, filed 1965 and patented 1967) as the active load [R2-12], one can come up with an
excellent differential input to single-ended output amplifier.
The active devices in Blumlein’s long-tailed pair were vacuum tubes, while those in Widlar’s
current mirror bipolar transistors. This idea was implemented in the input stages of some of
the early bipolar integrated operational amplifiers like LM101 (Bob Widlar in 1967) and its
derivative A741 (Dave Fullagar in 1968) [R2-11,12]. It still used in the input stages of
amplifiers today as no simple enough alternative has yet been found.
The object of our discussion in this chapter is a CMOS implementation of the idea. This
circuit is also known as the Operational Transconductance Amplifier or OTA. This has only
one high-impedance node at its output and can be compensated effectively by connecting a
compensation capacitor from that node to ground. Variants of this OTA have been used in
gm-C filters and input stages of multistage amplifiers.
36
3.2. Circuit Analysis and Transfer Function
Circuit Diagram
Fig. 3-1. Circuit schematic for the amplifier.
The circuit parameters for the amplifier are defined below:
Tab. 3-1. Circuit parameters for the amplifier.
No. Circuit parameter Symbol

1 Input device transconductance (MP1 or MP2) g m1
2 Mirror load transconductance (MN1 or MN2) g mm
3 Net resistance loading node N1 1/g mm
4 Net capacitance loading node N1 cp
5 Net resistance loading node OUT ro1
6 Net capacitance loading node OUT (compensation capacitance) CC
Block Diagram
Fig. 3-2. Block diagram for the amplifier.
Referring to Figs. 3-1, 3-2 and Tab. 3-1, transistors MP1, MP2 are the amplifying transistors of
the stage represented by the two blocks marked g m1 where g m1 is the transconductance of
either MP1 or MP2.
37
Transistors MN1, MN2 are the mirror load transistors of the stage represented by the block
marked g mm where g mm is the transconductance of either MN1 or MN2. The load capacitor CC
provides compensation to the amplifier.
Small-Signal Equivalent Circuit
The small-signal equivalent circuit for the amplifier can be drawn from its block diagram as
shown below:
Fig. 3-3. Simplified small-signal equivalent circuit for the amplifier.
Only low-frequency MOS models have been used in Fig. 3-3 to keep the analysis simple.
Network Equations and Solutions
For convenience, we shall work with conductances instead of resistances such as:
1
g o1 = (3-1)
ro1
Applying Laplace transforms and KCL to nodes N1 and OUT in Fig. 3-3:
1
(g mm + scp )V1 = 2 g m1 Vi (3-2)
1
g mm V1 + (g o1 + sCC )Vo = − 2 g m1 Vi (3-3)
Eqs. (3-2) and (3-3) can be written in vector-matrix form as:

1
g mm + scp 0 V g m1 Vi
[ ] [ 1 ] = [ 21 ] (3-4)
g mm g o1 + sCC Vo − g m1 Vi
2
Appling Cramer’s rule to solve Vo from Eq. (3-4):

1
gmm +scp g V
2 m1 i
| 1 |
gmm − gm1 Vi
2
Vo = gmm +scp 0
| |
gmm go1 +sCC
Expanding the numerator determinant:
38
1 1
− gm1 (gmm +scp )Vi − gm1 gmm Vi
2 2
Vo = gmm +scp 0
| |
gmm go1 +sCC
Whence we find the transfer function to be:

1 1
Vo − gm1 (gmm +scp )− gm1 gmm
2 2
Av (s) = = gmm +scp 0
Vi | |
gmm go1 +sCC
Simplifying the numerator and factoring out g mm and g o1 from the first and second columns
respectively of the denominator determinant:
scp scp
−gm1 gmm ( +1) −gm1 ( +1)
2gmm 2gmm
Av (s) = scp = scp
1+ 0 1+ 0
gmm gmm
gmm go1 | sC | go1 | sC |
1 1+ C 1 1+ C
go1 go1
Replacing the conductance using Eq. (3-1) and expanding the denominator determinant, we
arrive at the transfer function in its final form as:
scp
−gm1 ro1 ( +1)
2gmm
Av (s) = scp (3-5)
(sCC ro1 +1)( +1)
gmm
3.3. Poles and Zeros of the Transfer Function
Writing Eq. (3-5) in terms of its poles and zero:

−A0 (sτz +1)
Av (s) = (sτ (3-6)
p1 +1)(sτp2 +1)
Comparing Eqs. (3-5) and (3-6), the first pole is given by:
1 1
ωp1 = τ =C (3-7)
p1 C ro1
The second pole is given by:

1 gmm
ωp2 = τ = (3-8)
p2 cp
The zero is given by:

1 2gmm
ωz = τ = (3-9)
z cp
3.4. Design to Meet Specifications
3.4.1. Design Equations
DC Gain and Unity-Gain Frequency
Comparing Eqs. (3-5) and (3-6), magnitude of the DC gain is given by:
39
A0 = g m1 ro1 (3-10)
We decide ωp1 to be the dominant pole. Then, using Eqs. (2-63), (3-7) and (3-10) the unity-
gain frequency is given by:
gm1
ω0 = (3-11)
CC
Defining PZL Parameters
We do not define any PZL parameter for ωp1 noting that it is a low-frequency far-away pole.
However, it can be written in terms of ω0 by re-writing Eq. (2-63) as:
ω0
ωp1 = (3-12)
A0
We define PZL parameter σ for the second pole and zero. Noting from Eqs. (3-8) and (3-9)
that the zero is at twice the frequency of the second pole, we obtain:
ωp2 = σω0 (3-13)
ωz = 2σω0 (3-14)
Circuit Parameters in terms of PZL Parameters
Combining Eqs. (3-8), (3-11) and (3-13):

gmm σcp
= (3-15)
gm1 CC
Stability Equation (Phase Margin)
Using setting s = jω0 in Eq. (3-6) and using Eq. (2-77), the phase margin is given by:
ϕm = 1800 + tan−1(ω0 τz ) − tan−1(ω0 τp1 ) − tan−1(ω0 τp2 )
Using Eqs. (3-12) to (3-14) in the above:

1 1
ϕm = 1800 + tan−1 (2σ) − tan−1(A0 ) − tan−1 (σ) (3-16)
3.4.2. Design Calculations
The table below lists the target performance parameters for the amplifier:
Tab. 3-2. Amplifier specifications.
No. Performance parameter Symbol Value Units

1 Magnitude of DC gain A0 > 30 dB
2 Unity-gain frequency f0 ~ 50 MHz
3 Phase margin ϕm > 60 degrees
4 Gain margin Gm > 10 dB
5 Capacitive load CL 1.6 pF
40
Deciding PZL and Circuit Parameter Values
To meet specifications in Tab. 3-2 we proceed as follows:
We decide on σ = 6.4 placing ωp2 and ωz well above ω0 in frequency. Using this value of σ
̃ m is 85.60 .
in Eq (3-16) and assuming A0 to be a large number, the estimated phase margin ϕ
We choose g m1 = 500μS and CC = CL = 1.6pF so that f0 = 49.74MHz by Eq. (3-11).
Using cp = 100fF, we find g mm = 200μS from Eq. (3-15).
Using ro1 = 200kΩ, we find A0 = 100 = 40dB from Eq. (3-10).
Now, we can find a more accurate phase margin figure using Eq. (3-16):
ϕm = 1800 + 4.480 − 900 − 8.880 = 85.60 .
Based on the above calculations and Fig. 3-1, the circuit parameters, frequency parameters
and estimated cell statistics for the amplifier are summarised in the following three tables:
Tab. 3-3. Design values for circuit parameters.
No. Circuit parameter Symbol Value Units

1 MP1 or MP2 transconductance g m1 500 μS
2 MN1 or MN2 transconductance g mm 200 μS
3 Capacitance loading node N1 cp 100 fF
4 Output resistance ro1 200 kΩ
5 Compensation/Load capacitance CL = CC 1.6 pF
Tab. 3-4. Design values for frequency parameters.
No. Frequency parameter Symbol Value Units

1 First pole fp1 497.4 kHz
2 Unity-gain frequency f0 49.74 MHz
3 Second pole fp2 318.34 MHz
4 Zero fz 636.67 MHz
Tab. 3-5. Amplifier cell statistics estimated for ABC process technology (Appendix 18).
No. Cell statistic Symbol Value Units

1 Cell area Acell 35 × 35 μm2
2 Power consumption @ VDD − VSS = 1.5V Pcell 45 μW
3.4.3. Design Evaluation
Unity feedback factor loop-gain response plots can be obtained from the transfer function in
Eq. (3-5). Appendix 3 lists all necessary formulae. The plots, using parameter values in Tab.
3-3, are shown in Figs. 3-4 and 3-5. Performance parameters for the amplifier may be read
41
off from the plots or from the plot data in Tab. 3-7. The table below compares these figures
with those calculated in the previous sub-section and the specifications in Tab. 3-2.
Tab. 3-6. Comparison of performance parameters.
No. Performance parameter Symbol Calculated Evaluated Specs. Units

1 Magnitude of DC gain A0 40 40 > 30 dB
2 Unity-gain frequency f0 /fc 49.74 50 ~ 50 MHz
3 Phase margin ϕm 85.6 86.1 > 60 degrees
4 Phase crossover frequency fπ − NN − MHz
5 Gain margin Gm − NA > 10 dB
42
Fig. 3-4. Unity feedback factor loop-gain magnitude response for the amplifier.
Fig. 3-5. Unity feedback factor loop-gain phase response for the amplifier.
43
Tab. 3-7. Data listing for loop-gain response plots in Figs. 3-4 and 3-5.
44
3.5. Concluding Remarks
This amplifier is meant to drive high-impedance or capacitive loads only. With heavy
resistive and capacitive loads, its DC gain and unity-gain bandwidth are drastically reduced
as shown by Eqs. (3-10) and (3-11) respectively.
The entries in Tab. 3-4 show that ωp2 and ωz are at considerably high frequencies compared
to ω0 . This pole and zero are not very far apart and partially cancel each other as shown by
Eqs (3-8) and (3-9) and Figs. (3-4) and (3-5). Therefore, it is not surprising that ϕm is close
to 900 .
As can be seen from Eqs. (3-15) and (3-16), an increase in CC for this amplifier causes σ and,
therefore, ϕm to increase. This happens because ωp2 and ωz remain stationary while ω0 goes
down in frequency according to Eqs. (3-8), (3-9) and (3-11). For sufficiently high values of
CC , ϕm approaches 900 . Under such conditions, not much error will be committed if we
assume this amplifier to have just one pole ωp1 , neglecting ωp2 and ωz .
In the following chapters, we shall simplify our analyses by making the abovementioned
assumption for stages using this amplifier under similar conditions.
45
Chapter 4 Two-Stage Amplifier Miller
CHAPTER 4
Two-Stage Amplifier with Miller Compensation
Since the invention of John Milton Miller in 1920, the Miller capacitor has been used to
achieve frequency compensation in operational amplifiers built with any type of active
device, including vacuum tubes. The circuit we are going to study in this chapter is a CMOS
version of the first two stages of the A741 bipolar operational amplifier, introduced in 1968
[R2-11,12, R3-2].
CMOS implementations of this amplifier were already in use since 1974. By 1977-78, it was
found that a resistor, dubbed “nulling resistor” in early literature, had to be inserted in series
with the Miller capacitor for acceptable phase margin figures [R1-1]. Relatively low
transconductance of CMOS devices mandated this change over Bipolar implementations.
However, efficient output stages like those in Bipolar amplifiers were not possible to
implement because of non-availability of comparable voltage follower structures in CMOS.
Nevertheless, this amplifier can be designed to drive resistive loads for on-chip and
moderately low-impedance off-chip applications. The greatest advantage of this amplifier lies
in the simplicity of its frequency compensation. It is well understood in the circuit design
community, has the potential of providing great results with the least amount of effort and is
probably the most widely used embedded amplifier in integrated circuits.
46
Circuit Diagram

1 First stage transconductance (MP1 or MP2) g m1
2 Net resistance loading first stage (node N1) ro1
3 Net capacitance loading first stage (node N1) cp1
4 Second stage transconductance (MN3) g m2
5 Net resistance loading second stage (node OUT) RL
6 Net capacitance loading second stage (node OUT) CL
7 Compensation resistance RC
8 Compensation capacitance CC
Block Diagram
Fig. 4-2. Block diagram for the amplifier
47
Referring to Figs. 4-1, 4-2 and Tab. 4-1, transistors MP1, MP2, MP3, MN1 and MN2 constitute
the first stage represented by the block marked g m1 where g m1 is the transconductance of
either MP1 or MP2. Transistors MN3 and MP4 constitute the second stage represented by the
block marked g m2 where g m2 is the transconductance of MN3. RC and CC provide Miller
compensation to the amplifier.
shown below:
Other than low-frequency MOS models being used, the first stage of the amplifier has been
simplified in Fig. 4-3 as per discussions in Section 3.5.
For convenience, we shall consider conductances instead of resistances such as:

1 1
g o1 = r , GL = R (4-1)
o1 L
and admittances instead of impedances such as:

1 jωC
yC = 1 = 1+jωCC R (4-2)
RC + C C
jωCC
We shall assume the following to approximate some results later:
g m1 , g m2 ≫ g o1 , GL and cp1 ≪ CC , CL (4-3)
(g o1 + scp1 + YC )V1 − YC Vo = −g m1 Vi (4-4)
(g m2 − YC )V1 + (GL + sCL + YC )Vo = 0 (4-5)
Eqs. (4-4) and (4-5) can be written in vector-matrix form as:
48
g o1 + scp1 + YC −YC V −g V
[ ] [ 1 ] = [ m1 i ] (4-6)
g m2 − YC GL + sCL + YC Vo 0
Applying Cramer’s rule to solve Vo from Eq. (4-6):

go1 +scp1 +YC −gm1 Vi
| |
gm2 −YC 0
Vo = go1 +scp1 +YC −YC
| |
gm2 −YC GL +sCL +YC

gm1 Vi (gm2 −YC )
Vo = go1 +scp1 +YC −YC
| |

Vo (s) gm1 (gm2 −YC )
Av (s) = = go1 +scp1 +YC −YC
Vi (s) | |
Replacing the first column of the denominator determinant by the sum of its first and second
columns:
gm1 (gm2 −YC )
Av (s) = go1 +scp1 −YC
| |
GL +sCL +gm2 GL +sCL +YC
Factoring out g m2 from the numerator determinant and, at the same time, g o1 and GL from
the first and second columns respectively of the denominator determinant:
Y
gm1 gm2 (1− C )
gm2
Av (s) = cp1 Y
1+s − C
go1 GL
go1 GL | G Y
|
L +s CL +gm2 C
1+s L + C
go1 go1 go1 GL GL
Replacing the conductances and admittances using Eqs. (4-1) and (4-2):
sCC
gm1 gm2 ro1 RL [1− ]
gm2(sRC CC +1)
Av (s) = sCC RL
1+scp1 ro1 −
sCC RC +1
|r sCC RL
|
o1 +sC r +g
RL L o1 m2 ro1 1+sCL RL +
sCC RC +1
1
We now factor out from the numerator square bracket as well as from the second
sCC RC +1
column of the denominator determinant. The factor cancels out leaving behind:
sCC
gm1 gm2 ro1 RL (sCC RC +1− )
gm2
Av (s) = 1+scp1 ro1 −sCC RL
|ro1 (1+sCL RL )(sCC RC +1)+sCC RL |
+sCL ro1 +gm2 ro1
RL
49
Expanding the denominator determinant and re-arranging terms in the numerator and
denominator, we arrive at the transfer function in its final form as:
1
gm1 gm2 ro1 RL [sCc (RC − )+1]
gm2
Av (s) = s3 c 2 (4-7)
p1 CC CL ro1 RC RL + s [cp1 (CC RC +CL RL +CC RL )ro1 +CC CL ro1 RL +CC CL RC RL ]
+ s[ cp1 ro1 + CL RL + CC (ro1 +RC +RL +gm2 ro1 RL )]+1
Factorization
To find the poles and zeros of Eq. (4-7) we need to factorise the denominator and for that
purpose we approximate it using Eq. (4-3) to obtain:
1
̃ v (s) = 3
A 2 [c
gm2
(4-8)
s c p1 CC CL ro1 RC RL +s p1 (CC +CL )+CC CL ]ro1 RL +sCC gm2 ro1 RL +1
Factorising the denominator of Eq. (4-8) using Eq. (2-40):

1
̃ v (s) =
A
gm2
C
cp1 CL RC CL +cp1 (1+ L )
CC
(sCC gm2 ro1 RL +1)[s2 +s +1]
gm2 gm2
Factorising the quadratic polynomial in the denominator once more using Eq. (2-40):
1
̃ v (s) =
A C
gm2
(4-9)
(sCC gm2 ro1 RL +1)(s a +1)(sCb RC +1)
gm2
where:
C
Ca = CL + cp1 (1 + CL ) (4-10)
C
1 1 1 1
=c +C +C (4-11)
Cb p1 C L
Poles and Zeros

A0 (sτz +1)
̃ v (s) =
A (4-12)
(sτ p1 +1)(sτp2 +1)(sτp3 +1)
Comparing Eqs. (4-9) and (4-12) the first pole is given by:
1 1
ωp1 = τ =C (4-13)
p1 C gm2 ro1 RL

1 gm2
ωp2 = τ = (4-14)
p2 Ca
50
The third pole is given by:

1 1
ωp3 = τ =C (4-15)
p3 b RC
And the zero is given by:

1 1
ωz = τ = 1 (4-16)
z Cc (RC − )
gm2
Comparing Eqs. (4-9) and (4-12) magnitude of the DC gain is given by:
A0 = g m1 g m2 ro1 R L (4-17)
gm1
ω0 = (4-18)
CC
However, it can be expressed in terms of ω0 re-writing Eq. (2-63) as:
ω0
ωp1 = (4-19)
A0
We define PZL parameters σ and μ for ωp2 and ωz such that:
ωp2 = σω0 (4-20)
ωz = μωp2 = σμω0 (4-21)
We do not define any PZL parameter for ωp3 noting it to be a high-frequency far-away pole.
However, we can write it in terms of ω0 using Eqs. (4-15) and (4-18) as:
CC
ωp3 = g ω0 (4-22)
m1 RC Cb
Combining Eqs. (4-14), (4-18) and (4-20) we find:

gm2 σCa
= (4-23)
gm1 CC
51

1 1
RC = g + (4-24)
m2 σμgm1
Setting s = jω0 in Eq. (4-12) and using Eq. (2-77), the phase margin is given by:
ϕm = 1800 + tan−1(ω0 τz ) − tan−1(ω0 τp1 ) − tan−1(ω0 τp2 ) − tan−1(ω0 τp3 )
Substituting Eqs. (4-20) to (4-24) in the above:

1 1 C C
ϕm = 1800 + tan−1 (σμ) − tan−1(A0 ) − tan−1 (σ) − tan−1 (σCb + σμCb ) (4-25)
a c
The table below lists the target performance parameters for the amplifier:

5 Resistive load RL 10 kΩ
6 Capacitive load CL 6 pF
We decide on σ = 2.286 and μ = 1.591 placing ωz slightly above ωp2 in frequency with
σμ = 3.637. Using these values of σ and μ in Eq. (4-25), assuming A0 to be a large number
̃ m is 81.740 .
and neglecting contribution due to ωp3 , the estimated phase margin ϕ
Next, we choose g m1 = 500μS and CC = 1.6pF so that f0 = 49.74MHz by Eq. (4-18).
Using cp1 = 200fF, we find Ca = 7pF from Eq. (4-10) and Cb = 173fF from Eq. (4-11).
Subsequently, we find g m2 = 5mS using Eq. (4-23) and R C = 750Ω using Eq. (4-24).
Using ro1 = 200kΩ, we find A0 = 5000 ≈ 73.98dB from Eq. (4-17).
ϕm = 1800 + 15.370 − 900 − 23.630 − 2.320 = 79.420 .
52

1 First stage transconductance g m1 500 μS
2 First stage resistive load ro1 200 kΩ
3 First stage capacitive load cp1 200 fF
4 Second stage transconductance g m2 5 mS
5 Second stage resistive load RL 10 kΩ
6 Second stage capacitive load CL 6 pF
7 Compensation resistance RC 750 Ω
8 Compensation capacitance CC 1.6 pF

5 Third pole fp3 1.23 GHz
No. Cell statistic Symbol Estimated value Units

1 Cell area excluding RL1 and CL1 Acell 38 × 38 μm2

1 Magnitude of DC gain A0 73.98 74 > 70 dB
53
Fig. 4-4. Unity feedback factor loop-gain magnitude response for the amplifier
Fig. 4-5. Unity feedback factor loop-gain phase response for the amplifier
54
55
Compared to the amplifier in Chapter 3, this amplifier has higher gain, and the gain does not
go down drastically with resistive load. Presence of a second stage is responsible for the
improvements. However, the amplifier is still somewhat sensitive to very low resistive loads
with which its unity-gain bandwidth too tends to go down [R1-9].
From Eqs. (4-10) and (4-23) we can observe that g m2 requirement for this amplifier is nearly
proportional to CL . Thus, large values of g m2 would be needed for the amplifier to drive large
values of CL , causing power and area consumption to go up. On the other hand, small values
of g m2 would be needed for the amplifier to drive small values of CL , causing the DC gain to
go down.
However, Eq. (4-23) also shows that usage of large σ values can effectively mitigate the
abovementioned problem of DC gain loss. In that case R C , and not g m2 , need to be reduced
according to Eq. (4-24). In conclusion, this amplifier is best suited to work with small to
moderate CL and moderate to large R L values.
56
Chapter 5 Two-Stage Amplifier Cascode-Miller
CHAPTER 5
Two-Stage Amplifier with Cascode-Miller Compensation
This variant of the Miller compensation technique was employed in one of the very early
operational amplifier designs using CMOS devices – the CA3130, introduced in 1974 [R3-1].
The benefits of this compensation technique over Miller’s became a topic of discussion in the
early ’80s (R. Read and J. Weiser [R1-1]). Finally, a preliminary analysis to explain the
benefits became available in 1983 [R1-2]. A comprehensive analysis [R1-3] followed a year
later. Eventually, however, this technique became popularly known within the integrated
circuit design community as “Ahuja compensation,” being named after the author of the 1983
publication.
The main advantages of this compensation technique over Miller’s are firstly, the phase
margin degradation with capacitive load is much less [R1-2,3] and secondly, the power
supply rejection ratio (PSRR) figures at high frequencies are considerably better [R1-1,2,3].
However, there are disadvantages too. It may be difficult to obtain a smooth Miller-like
magnitude and phase response for the compensated amplifier just beyond the unity-gain
frequency. The responses tend to peak up in those regions. This too can be attributed to low
transconductance of CMOS devices [R1-3,13].
The above difficulty is probably the reason why this compensation technique gained
popularity much later (around 1995), by when sufficient downscaling of CMOS technology
had taken place and relatively large transconductances could be obtained without expending a
lot of power.
In this chapter we investigate two variants of this compensation. The first variant (type 1) was
described in [R1-1,2] whereas the second variant (type 2) was described in [R1-3]. However,
it is the second variant that eventually became popular [R1-13].
57
5.2.1. Amplifier Type 1
Circuit Diagram
The cascode compensation transistor MPC for this amplifier is separate from the first stage.
Fig. 5-1. Circuit schematic for amplifier type 1.
The circuit parameters are defined below:
Tab. 5-1. Circuit parameters for amplifier type 1.

3 Net resistance loading second stage (node OUT) cp1
4 Cascode transistor transconductance (MPC) g mc
5 Cascode transistor output resistance (MPC) roc
6 Cascode transistor gate-source capacitance (MPC) cpc
7 Cascode bias transistor output resistance (MP5) rob
Block Diagram
Fig. 5-2. Block diagram for amplifier type 1.
58
either MP1 or MP2. Transistors MP7 and MN3 constitute the second stage represented by the
block marked g m2 where g m2 is the transconductance of MN3. MP4, MP5, MP6 and MPC
constitute a stand-alone cascode current source pair. The cascode transistor MPC couples the
capacitor CC from the amplifier output to the first stage output providing cascode-Miller
compensation. MPC is represented by the block marked g mc , g mc being its transconductance.
shown below:
Fig. 5-3. Simplified small-signal equivalent circuit for amplifier type 1.
simplified in Fig. 5-3 as per discussions in Section 3.5. The cascode current source pair has
been replaced simply by its equivalent output resistance.

1 1 1 1
g o1 = r , g oc = r , g ob = r , GL = R (5-1)
o1 oc ob L
g m1 , g m2 ≫ g o1 , g oc , g ob , GL and cp1 , cpc ≪ CC , CL (5-2)
Applying Laplace transforms and KCL to nodes N1, Nc and OUT in Fig. 5-3:
(g o1 + g oc + scp1 )V1 − (g mc + g oc )Vc = −g m1 Vi (5-3)
−g oc V1 + (g mc + g oc + g ob + scpc + sCC )Vc − sCC Vo = 0 (5-4)
g m2 V1 − sCC Vc + (GL + sCL + sCC )Vo = 0 (5-5)
Eqs. (5-3) to (5-5) can be written in vector-matrix form as:
59
g o1 + g oc + scp1 −g mc − g oc 0 V1 −g m1 Vi
[ −g oc g mc + g oc + g ob + scpc + sCC − sCC ] [ Vc ] = [ 0 ]
g m2 −sCC GL + sCL + sCC Vo 0
(5-6)

go1 +goc +scp1 −gmc −goc −gm1 Vi
| −goc gmc +goc +gob +scpc +sCC 0 |
gm2 −sCC 0
Vo = g01 +goc +scp1 −gmc −goc 0
| −goc gmc +goc +gob +scpc +sCC − sCC |
gm2 −sCC GL +sCL +sCC
−goc gmc +goc +gob +scpc +sCC
−gm1 Vi | |
gm2 −sCC
Vo = go1 +goc +scp1 −gmc −goc 0

−goc gmc +goc +gob +scpc +sCC
−gm1 | |
Vo (s) gm2 −sCC
Av1 (s) = = go1 +goc +scp1 −gmc −goc 0 (5-7)
Vi (s)
| −g oc g mc +g oc +gob +scpc +sCC − sC C |

−goc gmc +sCC
−gm1 | |
̃ v1 (s) = gm2 −sCC
A go1 +goc +scp1 −gmc −goc 0
| −goc gmc +sCC − sCC |
Replacing the first row of the numerator determinant by the sum of its rows and, at the same
time, replacing the second column of the denominator determinant by the sum of its second
and third columns:
gm2 −goc gmc
−gm1 | g −sCC |
̃ v1 (s) =
A m2
go1 +goc +scp1 −gmc −goc 0
| −goc gmc − sCC |
gm2 GL +sCL GL +sCL +sCC
columns:
gm2 −goc gmc
−gm1 | g −sCC |
̃ v1 (s) =
A m2
go1 +scp1 −gmc −gmc −goc 0
| gmc −goc gmc − sCC |
GL +sCL +gm2 GL +sCL GL +sCL +sCC
60
Approximating the above one more time using Eq. (5-2):

gm2 gmc
−gm1 |g −sCC |
̃ v1 (s) =
A m2
go1 +scp1 −gmc −gmc 0
| gmc gmc − sCC |
Replacing the first row of the denominator determinant by the sum of its first and second
rows:
gm2 gmc
−gm1 |g −sCC |
̃ v1 (s) =
A m2
go1 +scp1 0 − sCC
| gmc gmc − sCC |
Factoring out g m2 and g mc from the first and second columns respectively of the numerator
determinant and, at the same time, g o1 , g mc and GL from the first, second and third columns
1 1
−gm1 gm2 gmc |1 −s CC |
̃ v1 (s) =
A cp1
gmc
C
1+s 0 −s C
go1 GL
| gmc C |
go1 gmc GL 1 −s C
go1 GL
| |
GL C g GL C C C
+s L + m2 +s L 1+s L +s C
go1 go1 go1 gmc gmc GL GL
The factor g mc cancels out, being common to both numerator and denominator. Replacing the
conductances using Eq. (5-1):
1 1
−gm1 gm2 ro1 RL |1 −s CC |
̃ v1 (s) =
A scp1 ro1 +1 0
gmc
− sCC RL
| gmc ro1 1 − sCC RL |
r C 1
sCL ro1 +gm2 ro1 + o1 s L+ sCL RL +sCC RL +1
RL gmc gmc RL
Expanding the numerator and denominator determinants fully and re-arranging terms we
arrive at the transfer function for amplifier type 1 in its final form as:
C
gm1 gm2 ro1 RL (s C +1)
̃ v1 (s) =
A cp1 CC CL ro1 RL
gmc
cp1CC ro1 C C R (5-8)
s3 + s2 [cp1 (CC +CL )ro1 RL + + C L L]
gmc gmc gmc
C
+s[(CC +CL )RL + C +cp1 ro1 + CC gm2 ro1 RL ] +1
gmc
It may be noted that the parameters roc , rob and cpc do not appear in Eq. (5-8).
5.2.2. Amplifier Type 2
Circuit Diagram
The cascode compensation transistor MNC is included in the first stage.
61
Fig. 5-4. Circuit schematic for amplifier type 2.
The circuit parameters are defined in the table below:
Tab. 5-2. Circuit parameters for amplifier type 2.

4 Cascode transistor transconductance (MNC) g mc
5 Cascode transistor output resistance (MNC) roc
6 Cascode transistor gate-source capacitance (MNC) cpc
7 Cascode bias transistor output resistance (MN2) rob
8 Second stage transconductance (MP6) g m2
Block Diagram
Fig. 5-5. Block diagram for amplifier type 2.
Referring to Figs. 5.4, 5-5 and Tab. 5.2, transistors MP1, MP2, MP3, MN1, MN2, MN3, MNC, MP4
and MP5 constitute a folded cascode first stage represented by the block marked g m1 where
g m1 is the transconductance of either MP1 or MP2. Transistors MP6 and MN4 constitute the
second stage represented by the block marked g m2 where g m2 is the transconductance of
62
MP6. The cascode transistor MNC couples the capacitor CC from the amplifier output to the
first stage output providing Cascode-Miller compensation. MNC is represented by the block
marked g mc , g mc being its transconductance.
shown below:
Fig. 5-6. Simplified small-signal equivalent circuit for amplifier type 2.
simplified in Fig. 5-6 as per discussions in Section 3.5. The folded cascode current mirror has
been replaced simply by its equivalent output resistance.
Applying Laplace transforms and KCL to nodes N1, Nc and OUT in Fig. 5-6:
gm1
(g o1 + g oc + scp1 )V1 − (g mc + g oc )Vc = − Vi (5-9)
2
gm1
−g oc V1 + (g mc + g oc + g ob + scpc + sCC )Vc − sCC Vo = − Vi (5-10)
2
g m2 V1 − sCC Vc + (GL + sCL + sCC )Vo = 0 (5-11)

g
g o1 + g oc + scp1 −g mc − g oc 0 V1 − m1 Vi
2
[ −g oc g mc + g oc + g ob + scpc + sCC − sCC ] [ Vc ] = [− gm1 V ]
2 i
g m2 −sCC GL + sCL + sCC Vo
0
(5-12)
63
1
go1 +goc +scp1 −gmc −goc − gm1 Vi
2
| 1
−g oc gmc +goc +gob +scpc +sCC − gm1 Vi |
2
gm2 −sCC 0
1 −goc gmc +goc +gob +scpc +sCC 1 go1 +goc +scp1 −gmc −goc
− gm1 Vi | |+ gm1 Vi | |
2 g m2 −sCC 2 gm2 −sCC
Whence we obtain the transfer function as:

1 −goc gmc +goc +gob +scpc +sCC 1 go1 +goc +scp1 −gmc −goc
− gm1 | |+ gm1 | |
Vo (s) 2 gm2 −sCC 2 gm2 −sCC
Av2 (s) = = g01 +goc +scp1 −gmc −goc 0 (5-13)
Vi (s)
It may be observed that the denominator determinants in Eqs. (5-7) and (5-13) are identical.
However, that is not the case for the numerators. The reason for this can be understood
comparing Figs. 5-3 and 5-6. The only difference between the two is in the point of
application of the input signal. As a result, the coefficient matrices in Eqs. (5-6) and (5-12)
are identical, accounting for identical denominators. However, the excitation vectors in those
equations are different and that explains the difference in the numerators.

1 −goc gmc +sCC 1 go1 +goc +scp1 −gmc −goc
− gm1 | | + gm1 | |
2 gm2 −sCC 2 gm2 −sCC
̃ v2 (s) =
| −goc gmc +sCC − sCC |
Replacing the first row of the both the numerator determinants by the sum of their rows and,
at the same time, replacing the second column of the denominator determinant by the sum of
its second and third columns:
1 gm2 −goc gmc 1 gm2 +go1 +goc +scp1 −gmc −goc −sCC
− gm1 | gm2 −sCC | + 2gm1 | |
̃ v2 (s) = 2 gm2 −sCC
| −goc gmc − sCC |
gm2 GL +sCL GL +sCL +sCC
Replacing first column of the denominator determinant by sum of its first and second ones:
1 gm2 −goc gmc 1 gm2 +go1 +goc +scp1 −gmc −goc −sCC
− gm1 | gm2 −sCC | + 2gm1 | |
̃ v2 (s) = 2 gm2 −sCC
A go1 +scp1 −gmc −gmc −goc 0
| gmc −goc gmc − sCC |
64
Approximating the above one more time using Eq. (5-2):

1 gm2 gmc 1 gm2 +scp1 −gmc −sCC
− gm1 |g | + gm1 | |
2 m2 −sCC 2 gm2 −sCC
̃ v2 (s) =
A go1 +scp1 −gmc −gmc 0
| gmc gmc − sCC |
Replacing the first row of the denominator determinant by the sum of its first and second
rows:
1 gm2 gmc 1 gm2 +scp1 −gmc −sCC
− gm1 |g −sCC | + 2gm1 | gm2 |
̃ v2 (s) = 2 m2 −sCC
A go1 +scp1 0 − sCC
| gmc gmc − sCC |
Factoring out g m2 and g mc from the first and second columns respectively of the numerator
determinants and, at the same time, g o1 , g mc and GL from the first, second and third columns
cp1 C
1 1 1+s −1−s C
1 1 gm2 gmc
C
− gm1 gm2 gmc |1
2 −s C | + 2gm1 gm2 gmc | C
|
gmc 1 −s C
gmc
̃ v2 (s) =
A cp1 C
1+s 0 −s C
go1 GL
| gmc C |
go1 gmc GL 1 −s C
go1 GL
| |
GL C g GL C C C
+s L + m2 +s L 1+s L +s C
go1 go1 go1 gmc gmc GL GL
The factor g mc cancels out, being common to both numerator and denominator. Replacing the
conductances using Eq. (5-1):
cp1 C
1 1 1+s −1−s C
1 1 gm2 gmc
C
− gm1 gm2 ro1 RL |1
2 −s C | + 2gm1 gm2 ro1 RL | CC
|
gmc 1 −s
gmc
̃ v2 (s) =
A scp1 ro1 +1 0 − sCC RL
| gmc ro1 1 − sCC RL |
r C 1
sCL ro1 +gm2 ro1 + o1 s L+ sCL RL +sCC RL +1
RL gmc gmc RL
Expanding the numerator and denominator determinants fully and re-arranging terms we
arrive at the transfer function for amplifier type 2 in its final form as:
cp1 CC CC
gm1 gm2 ro1 RL (−s2 +s + 1)
2gm2 gmc 2gmc
̃ v2 (s) =
A cp1 CC CL ro1 RL cp1CC ro1 CC CL RL (5-14)
s3 + s2 [cp1 (CC +CL )ro1 RL + + ]
gmc gmc gmc
CC
+s[(CC +CL )RL + +cp1 ro1 + CC gm2 ro1 RL ] +1
gmc
It may be noted that the parameters roc , rob and cpc do not appear in Eq. (5-14). This was
also the case for Eq. (5-8).
65
5.3. Poles and Zeros of the Transfer Functions
Factorization
To find the poles and zeros of Eqs. (5-8) and (5-14) we need to factorise the numerators and
denominators and, for that purpose, we approximate those using Eq. (5-2) to obtain:
C
̃ v1 (s) =
A cp1 CC CL ro1 RL C
gmc
(5-15)
s3 L
+ s2 (1+ )cp1 CC ro1 RL + sCC gm2 ro1 RL +1
gmc CC
and
Cp1 CC C
gm1 gm2 ro1 RL (−s2 +s C +1)
2gm2 gmc 2gmc
̃ v2 (s) =
A cp1 CC CL ro1 RL C (5-16)
s3 + s2 (1+ L )cp1 CC ro1 RL + sCC gm2 ro1 RL +1
gmc CC
Factorizing the denominators of Eqs. (5-15) and (5-16) and the numerator of Eq. (5-16) using
Eq. (2-40):
C
̃ v1 (s) =
A cp1 CL
gmc
C cp1 (5-17)
(sCC gm2 ro1 RL +1)[s2 +s(1+ L ) +1]
gm2 gmc CC gm2
and
CC Cp1
gm1 gm2 ro1 RL (s +1)(−s +1)
2gmc gm2
̃ v2 (s) =
A cp1 CL CL cp1 (5-18)
(sCC gm2 ro1 RL +1)[s2 +s(1+ ) +1]
gm2 gmc CC gm2
Poles and Zeros
Writing Eqs. (5-15) and (5-16) in terms of their poles and zeros:
A0 (1+sτz )
̃ v1 (s) =
A 2 2
(5-19)
(1+sτ p1 )(s τp23 +2sδp23 τp23 +1)
and
A0 (1+sτz1 )(1+sτz2 )
̃ v2 (s) =
A (5-20)
(1+sτ )(s2 τ2 +2sδ
p1 τ
p23 p23 p23 +1)
Comparing Eqs. (5-17) and (5-19) as well as Eqs. (5-18) and (5-20) the first pole for any of
the amplifier types is given by:
1 1
ωp1 = τ =g (5-21)
p1 m2 ro1 RL CC
Using Eq. (2-19), natural frequency and damping factor of the second and third poles for any
of the amplifier types are given by:
66
1 gm2 gmc
ωp23 = = √ (5-22)
τp23 cp1 CL
and
1 C gmc cp1
δp23 = 2 (1 + CL ) √ g (5-23)
C m2 CL
The zero for amplifier type 1 is given by:

1 gmc
ωz = τ = (5-24)
z CC
The zeros for amplifier type 2 are given by:

1 2gmc
ωz1 = τ = (5-25)
z1 CC
1 g
ωz2 = τ = − cm2 (5-26)
z2 p1
Note that ωz2 is a right half s-plane (R.H.P.) zero while ωz1 is left half s-plane (L.H.P.) one.
Comparing Eqs. (5-17) and (5-19) as well as Eqs. (5-18) and (5-20) magnitude of the DC
gain for any of the amplifier types is given by:
A0 = g m1 g m2 ro1 R L (5-27)
We decide ωp1 to be the dominant pole. Then using Eqs. (2-63), (5-21) and (5-27), unity-
gain frequency for any of the amplifier types is given by:
gm1
ω0 = (5-28)
CC
However, it can be expressed in terms of ω0 by re-writing Eq. (2-63) as:
ω0
ωp1 = (5-29)
A0
ωp23 = σω0 (5-30)
ωz = μωp23 = σμω0 (5-31)

67
Using Eqs. (5-24), (5-25) and (5-31), ωz1 can be written as:
ωz1 = 2σμω0 (5-32)
We do not define any PZL parameter for ωz2 noting that it is a high-frequency far-away zero.
However, it can be written in terms of ω0 combining Eqs. (5-22), (5-24), (5-26), (5-30) and
(5-31) to obtain:
σC
ωz2 = − μCL ω0 (5-33)
C
From Eqs. (5-24), (5-28) and (5-31) we find:

gmc
= σμ (5-34)
gm1
From Eqs. (5-22), (5-28) and (5-30) we find:

gm2 σcp1 CL
= (5-35)
gm1 μC2C
Using Eqs. (5-34) and (5-35) we can re-write Eq. (5-23) as:
μ C
δp23 = 2 (1 + CC) (5-36)
L
Setting s = jω0 in Eq. (5-19) and using Eq. (2-77), phase margin for amplifier type 1:
2ω0 δp23 τp23

ϕm1 = 1800 + tan−1(ω0 τz ) − tan−1(ω0 τp1 ) − tan−1 ( )
1−ω0 2 τ2p23
Using Eqs. (5-29) to (5-31) in the above:

1 2σδp23
ϕm1 = 1800 + tan−1 (σμ) − tan−1(A0 ) − tan−1 ( ) (5-37)
σ2 −1
Setting s = jω0 in Eq. (5-20) and using Eq. (2-77), phase margin for amplifier type 2:
2ω0 δp23 τp23

ϕm2 = 1800 + tan−1(ω0 τz1 ) + tan−1(ω0 τz2 ) − tan−1 (ω0 τp1 ) − tan−1 ( )
1−ω0 2 τ2p23
Using Eqs. (5-29), (5-30), (5-32) and (5-33) in the above:

1 μC 2σδp23
ϕm2 = 1800 + tan−1 (2σμ) − tan−1 (σCC) − tan−1 (A0 ) − tan−1 ( ) (5-38)
L σ2 −1
68
The table below lists the target performance parameters for any of the amplifier types:

We decide on σ = 2.6 and μ = 1 placing ωz right on top of ωp23 and ωz1 , ωz2 higher up in
frequency with σμ = 2.6. Using these values of σ and μ in Eqs. (5-37) and (5-38), assuming
A0 to be a large number and neglecting contribution due to ωz2 , the estimated phase margins
̃ m1 and ϕ
ϕ ̃ m1 are 85.050 for amplifier type 1 and 74.900 for amplifier type 2.
Next, we choose g m1 = 500μS and CC = 1.6pF so that f0 = 49.74MHz by Eq. (5-28) and
g mc = 1.3mS using Eq. (5-34).
We now choose cp1 = 200fF.
Then, g m2 = 2.03mS using Eq. (5-35) and δp23 = 0.54 using (5-36)
Choosing ro1 = 200kΩ, we find A0 = 4060 ≈ 72.17dB using Eq. (5-27).
Now, we can find a more accurate phase margin figure for amplifier type 1 using Eq. (5-37):
ϕm1 = 1800 + 21.040 − 900 − 25.990 = 85.050
and a more accurate phase margin figure for amplifier type 2 using Eq. (5-38):
ϕm2 = 1800 + 10.890 − 1.760 − 900 − 25.990 = 73.140 .
Based on the above calculations and Figs. 5-1, 5-4, the circuit parameters, frequency
parameters and estimated cell statistics for the amplifier are summarised in the following
three tables:
69
Tab. 5-4. Design values for circuit parameters (any of the amplifier types).

4 Cascode transistor transconductance g mc 1.3 mS
5 Second stage transconductance g m2 2.03 mS

3 Second/third pole fp23 (δp23 ) 129.32 (0.54) MHz (−)
4 Zero amp. type 1 fz 129.32 MHz
5 First zero amp. type 2 fz1 258.64 MHz
6 Second zero amp. type 2 fz2 (R.H.P.) 1.62 GHz

Type 1 Type 2
1 Cell area excluding RL1 and CL1 Acell 38 × 38 36 × 36 μm2
2 Power consumption @ VDD − VSS = 1.5V Pcell 195 255 μW
Eqs. (5-15) and (5-16). Appendix 5 lists all necessary formulae. The plots, using parameter
values in Tab. 5-4, are shown in Figs. 5-7 to 5-10. Performance parameters for the amplifier
may be read off from the plots or from the plot data in Tab. 5-8. The table below compares
these figures with those calculated in the previous sub-section and the specifications in Tab.
5-3.
No. Performance Symbol Calculated Evaluated Specs. Units

parameter Type 1 Type 2 Type 1 Type 2
1 Magnitude of DC gain A0 72.17 72.17 72.2 72.2 > 70 dB
2 Unity-gain frequency f0 /fc 49.74 49.74 55 52 ~ 50 MHz
3 Phase margin ϕm 85.05 73.14 82 72.5 > 60 degrees
4 Phase crossover freq. fπ − − NN 180 − MHz
5 Gain margin Gm − − NA 14 > 10 dB
70
Fig. 5-7. Unity feedback factor loop-gain magnitude response for amplifier type 1
Fig. 5-8. Unity feedback factor loop-gain phase response for amplifier type 1
71
Fig. 5-9. Unity feedback factor loop-gain magnitude response for amplifier type 2
Fig. 5-10. Unity feedback factor loop-gain phase response for amplifier type 2
72
Tab. 5-8. Data listing for loop-gain response plots in Figs. 5-7, 5-8 (left) and in Figs. 5-9, 5-10 (right).
73
Low transconductance values g mc of the cascode compensation transistor MPC in Fig. 5-1 or
MNC in Fig. 5-4 is the primary cause behind increased design complexity of this amplifier
over the one in Chapter 4. Being coupled to or built within the first stage, sufficient power is
not readily available to obtain the required amount of transconductance for this transistor. As
can be seen from Eq. (5-23), this causes δp23 to be rather small. On top of that, Eqs. (5-24)
and (5-28) point to the possibility of ωz for amplifier type 1 being located uncomfortably
near ω0 . However, Eq. (5-25) shows that the problem is relatively less severe for amplifier
type 2.
Combining both the above effects, the gain magnitude and phase plots for this amplifier may
show undesirable peaking and unevenness near ω0 if the circuit parameters are not
determined properly. Under extreme conditions, such as light capacitive loads, the magnitude
plot might show multiple gain crossovers indicating stability problems, as discussed in
Section 2.4.5. However, the above difficulty can be mitigated without spending too much
power. A 2009 publication [R1-13] describes a possible solution.
The performance of this amplifier with resistive loads is on par with that of the amplifier in
Chapter 4 with a slight edge for very low load resistances [R1-9]. However, its performance
with capacitive loads is different on several counts. The presence of a small capacitance cp1
in Eq. (5-35) indicates that this amplifier does not need large values of g m2 when driving
large values of CL . At the same time, it means small g m2 values must be used for small CL
values, and that causes a substantial drop in DC gain.
Studying Eqs. (5-34) and (5-35) further we observe that large values of σ would be needed to
mitigate the abovementioned problem of DC gain loss. That, in turn, would need large g mc
values which is difficult to obtain as mentioned in the first paragraph of this section.
Therefore, it is difficult to design this amplifier for small capacitive loads. In conclusion, this
amplifier is best suited to work with large CL and large R L values.
Tab. 5-7 shows that the evaluated fc values deviate slightly but significantly from the
calculated f0 ones, and this reflects in ϕm values too. As discussed in section 2.4.5, this is
likely to happen to amplifier type 1 since both fz and fp23 are located close to f0 , as shown in
Tab. 5-5. It can also be seen that the problem is less severe for amplifier type 2 since only
fp23 is close to f0 but fz1 is located further up in frequency.
From the first three rows of Tab. A17-2, it may be seen that the power and area consumed by
the amplifiers in this chapter are comparable to those of the amplifier in Chapter 4.
74
Chapter 6 Three-Stage Amplifier Nested Miller
CHAPTER 6
Three-Stage Amplifier with Nested Miller Compensation
This compensation technique was in use in the ’80s and ’90s using bipolar technology.
Earphone driver was probably the primary application in those times. A three-stage design
was chosen since high enough gain was needed to maintain harmonic distortion at low levels
while driving low-impedance transducers. But, with technology down-scaling, three stage
designs have become a necessity for embedded CMOS amplifiers even with high-impedance
on-chip loads.
The technique uses Miller pole-splitting twice by nesting an inner two-stage section (second
and third stages) within the outer two-stage (first stage and inner section) one. The inner
section is equivalent to a single stage at low frequencies because of the pole-split. Thus, two
compensation capacitors are required, one for each section.
Extending the concept of zero positioning introduced in Chapter 4, a CMOS version of this
amplifier requires one resistor to be inserted in series with each of the two compensation
capacitors. However, with two resistors and two capacitors to be determined, the design
process is more complicated. An analytical work published in 2002 [R1-7] provides more
insight into the problem and the solution.
Unlike Miller compensation, this compensation technique never gained widespread

popularity. This might be due to the additional complexity in determining the compensation
components. The circuit design community kept pushing the limits with two-stage designs
and, in the meantime, many alternative methods for compensating three-stage amplifiers were
proposed. Some of those techniques will be discussed in the following chapters.
75
Circuit Diagram

4 Second stage transconductance (MN3 with MP4 = MP5) g m2
5 Net resistance loading second stage (node N2) ro2
6 Net capacitance loading second stage (node N2) cp2
7 Third stage transconductance (MP6) g m3
8 Net resistance loading third stage (node OUT) RL
9 Net capacitance loading third stage (node OUT) CL
10 Compensation resistance to first stage RC
11 Compensation capacitance to first stage CC
12 Compensation resistance to second stage RD
13 Compensation capacitance to second stage CD
Block Diagram
76
either MN1 or MN2. Transistors MN3, MN4, MP4 and MP5 constitute the second stage
represented by the block marked g m2 where g m2 is the transconductance of MN3. The third
stage represented by the block marked g m3 is constituted by MP6 and MN5 where g m3 is the
transconductance of MP6. RD, CD and RC, CC provide nested Miller compensation to the
amplifier.
shown below:
Fig 6-3. Simplified small-signal equivalent circuit for the amplifier.

1 1 1
g o1 = r , g o2 = r , GL = R (6-1)
o1 o2 L

1 jωC 1 jωC
yC = 1 = 1+jωCC R , yD = 1 = 1+jωCDR (6-2)
RC + C C RD + D D
jωCC jωCD
g m1 , g m2 , g m3 ≫ g o1 , g o2 , GL and cp1 , cp2 ≪ CC , CD , CL (6-3)
Applying Laplace transforms and KCL to nodes N1, N2 and OUT in Fig. 6-3:
77
−g m2 V1 + (g o2 + scp2 + YD )V2 − YD Vo = 0 (6-5)
−YC V1 + (g m3 − YD )V2 + (GL + sCL + YC + YD )Vo = 0 (6-6)
[ −g m2 g o2 + scp2 + YD −YD V
] [ 2] = [ 0 ] (6-7)
−YC g m3 − YD GL + sCL + YC + YD Vo 0

go1 +scp1 +YC 0 −gm1 Vi
| −gm2 go2 +scp2 +YD 0 |
−YC gm3 −YD 0
Vo = go1 +scp1 +YC 0 −YC
| −gm2 go2 +scp2 +YD −YD |
−YC gm3 −YD GL +sCL +YC +YD
−gm2 go2 +scp2 +YD
−gm1 Vi | |
−YC gm3 −YD

−gm2 go2 +scp2 +YD
−gm1 | |
Vo (s) −YC gm3 −YD
Av (s) = = go1 +scp1 +YC 0 −YC (6-8)
Vi (s)
time, replacing the third column of the denominator determinant by the sum of its first and
third columns:
−gm2 −YC gm3 +go2 +scp2
−gm1 | |
−YC gm3 −YD
Av (s) = go1 +scp1 +YC 0 go1 +scp1
| −gm2 go2 +scp2 +YD −gm2 −YD |
−YC gm3 −YD GL +sCL +YD
Replacing the third column of the denominator determinant by the sum of its last two
columns:
−gm2 −YC gm3 +go2 +scp2
−gm1 | |
−YC gm3 −YD
Av (s) = go1 +scp1 +YC 0 go1 +scp1
| −gm2 go2 +scp2 +YD go2 +scp2 −gm2 |
−YC gm3 −YD gm3 +GL +sCL
Approximating the above using Eq. (6-3):
78
−gm2 −YC gm3 +scp2

−gm1 | |
̃ v (s) = −YC gm3 −YD
A go1 +scp1 +YC 0 go1 +scp1
| −gm2 go2 +scp2 +YD scp2 −gm2 |
−YC gm3 −YD gm3 +GL +sCL
Factoring out −g m2 and g m3 from the first and second columns respectively of the numerator
determinant and, at the same time, g o1 , g o2 and GL from the first, second and third columns
Y scp2
1+ C 1+
gm2 gm3
gm1 gm2 gm3 | YC Y
|
1− D
gm2 gm3
̃ v (s) =
A scp1 Y go1 scp1
1+ + C 0 +
go1 go1 GL GL
| g scp2 YD gm2 scp2 |
go1 go2 GL − m2 1+ + − +
| go1 go2 go2 GL GL |
Y gm3 YD gm3 sCL
− C − 1+ +
go1 go2 go2 GL GL
sCC scp2
1+ 1+
gm2 (1+sCC RC ) gm3
gm1 gm2 gm3 ro1 ro2 RL | sCC sCD
|
1−
gm2 (1+sCC RC ) gm3 (1+sCD RD )
̃ v (s) =
A sCC ro1 RL
1+scp1 ro1 + 0 +scp1 RL
1+sCC RC ro1
| sCD ro2 |
−gm2 ro1 1+scp2 ro2 + −gm2 RL +scp2 RL
1+sCD RD
| |
sCC ro1 sC r
− gm3 ro2 − D o2 1+gm3 RL +sCL RL
1+sCC RC 1+sCD RD
1 1
We now factor out from the first column and from the second column of
1+sCC RC 1+sCD RD
both the numerator and denominator determinants. The factors cancel out leaving behind:
sC scp2
1+sCC RC + C (1+sCD RD )(1+ )
gm2 gm3
gm1 gm2 gm3 ro1 ro2 RL | sC sCD
|
C
1+sCD RD −
gm2 gm3
̃ v (s) =
A RL
(1+sCC RC )(1+scp1 ro1 )+sCC ro1 0 +scp1 RL
ro1
| |
−gm2 ro1 (1+sCC RC ) (1+sCD RD )(1+scp2 ro2 )+sCD ro2 −gm2 RL +scp2 RL
−sCC ro1 gm3 ro2 (1+sCD RD )−sCD ro2 1+gm3 RL +sCL RL
Now it is time to fully expand the numerator and the denominator determinants. An
inspection of the anti-diagonal elements of the numerator determinant show that the
numerator polynomial is of degree 3. Similarly, the main diagonal elements of the
denominator determinant show that the denominator polynomial is of degree 5. A full
expansion would result in unmanageably large number of terms. Therefore, we need to make
some simplifications at this stage. Firstly, we choose:
1 2
RC = g and RD = g (6-9)
m2 m3
Using Eq. (6-9), the transfer function reduces somewhat to:
79
2sC 2sCD scp2

1+ C (1+ )(1+ )
g gm3 gm3
gm1 gm2 gm3 ro1 ro2 RL | sCm2 sCD
|
C
1+
gm2 gm3
̃ v (s) =
A sCC RL
(1+ )(1+scp1 ro1 )+sCC ro1 0 +scp1 RL
gm2 ro1
| sC 2sCD |
−gm2 ro1 (1+ C ) (1+ )(1+scp2 ro2 )+sCD ro2 −gm2 RL +scp2 RL
| gm2 gm3 |
2sC
−sCC ro1 gm3 ro2 (1+ D )−sCD ro2 1+gm3 RL +sCL RL
gm3
Full expansion of the determinants still yields large number of terms, particularly in the
denominator. Therefore, and secondly, we make use of Eq. (6-3) to approximate the results of
the expansions and arrive at the transfer function in its final form as:
2cp2 CC CD C C
gm1 gm2 gm3 ro1 ro2 RL [−s3 + s( C + D ) + 1]
gm2 g2 gm2 gm3
̃ v (s) =
A 2cp1 cp2 CC CD CL ro1 ro2 RL
m3
cp1 2cp2 (6-10)
s5 + s4 ( + )CC CD CL ro1 ro2 RL
gm2 gm3 gm2 gm3
3 2 (g )r
+ s CC CD CL ro1 ro2 RL + s CC CD m2 +gm3 o1 ro2 RL + sCC gm2 gm3 ro1 ro2 RL +1
It will be evident, as we continue further, that the choice as in Eq. (6-9) moves two (one right
half and the other left half s-plane) zeros to high frequencies leaving behind one left-half s-
plane zero. This result is achieved by removal of the s2 term in the numerator by cancellation.
Factorization
Factorizing the numerator and denominator of Eq. (6-10) using Eq. (2-40):
C C 2cp2 CC CD
gm1 gm2 gm3 ro1 ro2 RL [s( C + D ) + 1][−s2 +1]
gm2 gm3 gm3 (CC gm3 +CD gm2 )
̃ v (s) =
A 2cp1 cp2 CD CL cp1 2cp2 CD CL
s4 + s3 ( + )
g2
m2 g2
m3
gm2 gm3 gm2 gm3
(sCC gm2 gm3 ro1 ro2 RL +1)[ ]
C C g +g
+ s2 D L + sCD ( m2 m3 )+1
gm2 gm3 gm2 gm3
Factorizing the biquadratic polynomial enclosed by the square bracket in the denominator
using Eq. (2-57):
C C 2cp2 CC CD
gm1 gm2 gm3 ro1 ro2 RL [s( C + D ) + 1][−s2 +1]
gm2
gm3 gm3 (CC gm3 +CD gm2 )
̃ v (s) =
A 2c p1 c p2 c p1 2cp2
C C g +g
(sCC gm2 gm3 ro1 ro2 RL +1)[s2 D L + sCD ( m2 m3 )+1][ s2 g g + s( +
gm2 gm3
)+1]
gm2 gm3 gm2 gm3 m2 m3
Factorizing the last factors in the numerator and denominator further using Eq. (2-24):
C C 2cp2 CC CD 2cp2 CC CD
gm1 gm2 gm3 ro1 ro2 RL [s( C + D )+1][s√ +1][−s√ +1]
gm2 gm3 gm3 (CC gm3 +CD gm2 ) gm3 (CC gm3 +CD gm2 )
̃ v (s) =
A CD CL g +g 2cp2 cp1 (6-11)
(sCC gm2 gm3 ro1 ro2 RL +1)[s2 + sCD ( m2 m3 )+1](s +1)(s +1)
gm2 gm3 gm2 gm3 gm3 gm2
Poles and Zeros
Writing Eq. (6-10) in terms of its poles and zeros:
80
A0 (sτz1 +1)(sτz2 +1)(sτz3 +1)

̃ v (s) =
A 2 2 (6-12)
(sτ p1 +1)(s τp23 +2sδp23 τp23 +1)(sτp4 +1)(sτp5 +1)
1 1
ωp1 = τ =C (6-13)
p1 C gm2 gm3 ro1 ro2 RL
Using Eq. (2-19), the natural frequency and damping factor of the second and third poles are
given by:
1 gm2 gm3
ωp23 = =√ (6-14)
τp23 CD CL
g +gm3 C
δp23 = 2 m2 √ CD (6-15)
√ m2 gm3
g L
The fourth pole is given by:

1 g
ωp4 = τ = 2cm3 (6-16)
p1 p2
The fifth pole is given by:

1 gm2
ωp5 = τ = (6-17)
p1 cp1
The first zero is given by:

1 1
ωz1 = τ = CD C (6-18)
z1 + C
gm3 gm2
The second zero is given by:
1 g g gm2
ωz2 = τ = √2cm3 ( Cm3 + ) (6-19)
z2 p2 D CC
And the third zero is given by:
1 g g gm2
ωz3 = τ = −√2cm3 ( Cm3 + ) (6-20)
z3 p2 D CC
It may be noted that ωz2 and ωz3 have mirror symmetry about the jω axis in the s-plane, and
therefore, the phases due to these cancel each other.
81
A0 = g m1 g m2 g m3 ro1 ro2 R L (6-21)
gm1
ω0 = (6-22)
CC
ω0
ωp1 = (6-23)
A0
We define PZL parameters σ and μ for ωp23 and ωz1 such that:
ωp23 = σω0 (6-24)
ωz1 = μωp23 = σμω0 (6-25)
We do not define any PZL parameter for ωp4 and ωp5 noting those to be high-frequency far-
away poles. However, we can write the poles in terms of ω0 using Eqs. (6-16), (6-17) and (6-
22) as:
g C
ωp4 = 2gm3 cC ω0 (6-26)
m1 p2
g C
ωp5 = g m2c C ω0 (6-27)
m1 p1
Combining Eqs. (6-14), (6-18), (6-24) and (6-25) we arrive at the quadratic equation:
gm3 √CD CL gm3 C

− √g + CD = 0 (6-28)
gm2 μCC m2 C
Using Eq. (2-14) the preferred solution for Eq. (6-28) is given by:
gm3 κ√CD CL C 1 C
√g = where, κ = 1 + √1 − 4μ2 CC provided μ ≤ 2 √CL (6-29)
m2 2μCC L C
Combining Eqs. (6-14), (6-22), (6-24) and (6-29) we find:

gm2 2σμ
= (-)
gm1 κ
and
gm3 κσCD CL
= (6-31)
gm1 2μC2C
82
Using Eq. (6-29) we can re-write Eq. (6-15) as:

κC μC
δp23 = 4μCD + κCC (6-32)
C L
ϕm = 1800 + tan−1(ω0 τz1 ) + tan−1(ω0 τz2 ) + tan−1(ω0 τz3 ) − tan−1(ω0 τp1 )
2ω0 δp23 τp23

−tan−1 ( ) − tan−1 (ω0 τp4 ) − tan−1(ω0 τp5 )
1−ω20 τ2p23
As mentioned in the previous section, phases due to ωz2 and ωz3 cancel each other.
Substituting Eqs. (6-23) to (6-27) and (6-30), (6-31) in the above:

1 2σδp23 4μcp2 CC
ϕm = 1800 + tan−1 (σμ) − tan−1(A0 ) − tan−1 ( ) − tan−1 ( κσC )
σ2 −1 D CL
κcp1
− tan−1 (2σμC ) (6-33)
C
The table below lists the target performance parameters for amplifier.

To meet the specifications in Tab. 6-2 we proceed as follows:
We decide on σ = 2.25 and μ = 0.95 placing ωz1 nearly on top of ωp23 in frequency with
σμ = 2.1375. Using these values of σ and μ in Eq. (6-33), assuming A0 to be a large number
̃ m = 76.160 .
and neglecting contributions due to ωp4 and ωp5 , the estimated phase margin ϕ
Using g m1 = 500μS and CC = 1.6pF, f0 = 49.74MHz using Eq. (6-22).
Next, we find κ = 1.193 using Eq. (6-29).
We use CD = 2.5pF, cp1 = 100fF and cp2 = 200fF.
83
Then, g m2 = 1.79mS from Eq. (6-30) and g m3 = 4.14mS from Eq. (6-31).
Using Eq. (6-32), we find δp23 = 0.703.
Next, we find R C = 559Ω and R D = 483Ω using Eq. (6-9).
We choose ro1 = 200kΩ and ro2 = 55kΩ.
Then, A0 = 407583 ≈ 112.2dB using Eq. (6-21).
ϕm = 1800 + 25.070 − 900 − 37.910 − 1.730 − 10 = 74.430 .

5 Second stage resistive load ro2 55 kΩ
6 Second stage capacitive load cp2 200 fF
7 Third stage transconductance g m3 4.14 mS
8 Third stage resistive load RL 10 kΩ
9 Third stage capacitive load CL 6 pF
10 Compensation resistance to first stage RC 559 Ω
11 Compensation capacitance to first stage CC 1.6 pF
12 Compensation resistance to second stage RD 483 Ω
13 Compensation capacitance to second stage CD 2.5 pF

1 First pole fp1 122.04 Hz
3 First zero fz1 106.32 MHz
5 Second or third zero fz2 / fz3 (R.H.P.) 852.91 MHz
6 Fourth pole fp4 1.65 GHz
7 Fifth pole fp5 2.85 GHz

84

2 Unity-gain frequency f0 /fc 49.74 50.5 ~ 50 MHz
3 Phase margin ϕm 74.43 75 > 60 degrees
4 Phase crossover frequency fπ − 280 − MHz
5 Gain margin Gm − 20 > 10 dB
85
Fig 6-4 Unity feedback factor loop-gain magnitude response for the amplifier.
Fig 6-5 Unity feedback factor loop-gain phase response for the amplifier.
86
87
As can be seen from Eq. (6-21), this amplifier can be designed to provide sufficiently high
DC gains with large or medium values of R L . The DC gain does drop with small R L values
but not as much as the amplifiers in Chapters 4 and 5 because of the presence of one more
amplifying stage.
It may be noted from Eq. (6-29) that κ is nearly a constant with its values ranging from 1 to 2.
Therefore, Eq. (6-31) indicates that g m3 requirement can largely remain the same provided
changes in CL is countered with a change in CD in the opposite direction. In other words, this
amplifier can use largely the same g m3 value for driving small as well as large CL values,
provided CD is adjusted as mentioned.
Eqs. (6-30) and (6-31) together show that by choosing PZL or circuit parameters
appropriately, the amplifier can be designed to work with a wide range of CL values
providing optimum performance in terms of DC gain and power consumption.
It is possible to achieve large δp23 values for this amplifier. This will be evident from Eq. (6-
32). Consequently, the loop-gain magnitude and phase plots for this amplifier are smooth like
those for the amplifier in Chapter 4.
Tab. 6-6 shows that the evaluated fc value deviates slightly but significantly from the
calculated f0 one. As discussed in Section 2.4.5, this is likely to happen since both fz1 and
fp23 are located close to f0 , as shown in Tab. 6-4. It can also be seen that the problem is less
severe for this amplifier compared to the one in Chapter 5 because of a larger δp23 value.
However, the corresponding deviation in ϕm is not in the right direction. That is likely due to
approximation errors involved in finding high frequency poles/zeros.
This amplifier has one more set of compensation capacitor and resistor in addition to one
more gain stage compared to the amplifiers in Chapters 4 and 5. Therefore, it is expected to
be more expensive in terms of area and power. The first three rows of Tab. A17-2 and the
first row of Tab. A17-3 show how this amplifier fares.
88
Chapter 7 Three Stage Amplifier Miller, Active FF CS
CHAPTER 7
Three-Stage Miller Compensated Amplifier with
Active Feedforward around Centre-Stage
A three-stage amplifier can be Miller compensated like a two-stage one by feeding forward
the signal around its centre stage at high frequencies. Bipolar operational amplifiers OP05
and OP07 [R2-11,12, R3-3,4] introduced in 1972 and 1975 respectively are probably the
earliest ones to make use of this idea. A capacitor was used as the feedforward element in
these implementations. A resistor was used in series with this capacitor to favour the forward
path of the signal over the backward path. This implementation, though successful in Bipolar
designs, does not work well in CMOS as high values for the output stage transconductance
are required for proper compensation. Fig. 2-1 shows the small-signal equivalent circuit.
Later in 1986, another implementation of the same idea was published [R1-4]. Using
primarily a CMOS process, it used a specially created NPN Bipolar transistor for the
feedforward path. The Bipolar device, replacing the resistor in the former implementation,
was used as a voltage follower providing maximum signal feedforward while preventing any
signal feedback. However, this is no longer anything special as modern CMOS processes do
allow good Bipolar devices to be implemented with just one additional masking step. In this
chapter we shall be discussing the latter implementation only.
89
Circuit Diagram

1 First stage transconductance (MN1 or MN2) g m1
4 Second stage transconductance (MP3 with MN6 = MN7) g m2
7 Third stage transconductance (MN8) g m3
10 Feedforward capacitance CF
Block Diagram
Fig 7-2. Block diagram for the amplifier.
90
Referring to Figs. 7-1, 7-2 and Tab. 7-1, transistors MN1, MN2, MN4, MP1 and MP2 constitute
either MN1 or MN2. Transistors MP3, MP4, MN6 and MN7 constitute the second stage
represented by the block marked g m2 where g m2 is the transconductance of MP3 or MP4.
Transistors MN8 and MP5 make up the third stage represented by the block marked g m3 where
g m3 is the transconductance of MN8. The feedforward path around the second stage is
provided through the capacitor CF, driven by a voltage follower comprising of QN2 and MN5.
The voltage follower is assumed to be ideal (which is reasonable when using a good NPN
Bipolar transistor) and is represented by the block marked 1. Transistors QN1 and MN3 are
added for symmetrical loading of the first stage. RC and CC provide the usual Miller
compensation.
shown below:
simplified in Fig. 7-3 as per discussions in Section 3.5. The voltage follower for feedforward
has also been replaced with an ideal one as mentioned above.

1 1 1
g o1 = r , g o2 = r , GL = R (7-1)
o1 o2 L

1 jωC
yC = 1 = 1+jωCC R (7-2)
RC + C C
jωCC
g m1 , g m2 , g m3 ≫ g o1 , g o2 , GL and cp1 , cp2 ≪ CF , CC , CL (7-3)

91
−(sCF + g m2 )V1 + (g o2 + scp2 + sCF )V2 = 0 (7-5)
−YC V1 + g m3 V2 + (GL + sCL + YC )Vo = 0 (7-6)
We now define:
C2 = cp2 + CF (7-7)
Eqs. (7-4) to (7-6) can be written in vector-matrix form using Eq. (7-7) as:
[ −sCF − g m2 g o2 + sC2 0 V
] [ 2] = [ 0 ] (7-8)
−YC g m3 GL + sCL + YC Vo 0

go1 +scp1 +YC 0 −gm1 Vi
| −sCF −gm2 go2 +sC2 0 |
−YC gm3 0
| −sCF −gm2 go2 +sC2 0 |
−YC gm3 GL +sCL +YC
Using cofactor expansion of the numerator determinant along its third column:
−sCF −gm2 go2 +sC2
−gm1 Vi | |
−YC gm3
| −sCF −gm2 go2 +sC2 0 |

−sCF −gm2 go2 +sC2
Vo (s) −gm1 | |
−YC gm3
Av (s) = = go1 +scp1 +YC 0 −YC (7-9)
Vi (s)
| −sCF −gm2 go2 +sC2 0 |
Replacing the first column of the numerator determinant by the sum of its first and second
columns and doing the same to the denominator determinant:
go2 +scp2 −gm2 go2 +sC2
−gm1 | |
gm3 −YC gm3
Av (s) = go1 +scp1 +YC 0 −YC
|go2 +scp2 −gm2 go2 +sC2 0 |
gm3 −YC gm3 GL +sCL +YC
time, replacing the first column of the denominator determinant by the sum of its first and
third columns:
92
go2 +scp2 +gm3 −gm2 −YC go2 +gm3 +sC2

−gm1 | |
gm3 −YC gm3
Av (s) = go1 +scp1 0 −YC
|go2 +scp2 −gm2 go2 +sC2 0 |
GL +sCL +gm3 gm3 GL +sCL +YC

scp2 +gm3 −gm2 −YC gm3 +sC2
−gm1 | |
̃ v (s) = gm3 −YC gm3
A go1 +scp1 0 −YC
|scp2 −gm2 go2 +sC2 0 |
sCL +gm3 gm3 GL +sCL +YC
determinant and g o1 , g o2 and GL from the first, second and third columns respectively of the
denominator determinant:
Y scp2 gm3 sC
1+ C − − 1+ 2
gm2 gm2 gm2 gm3
gm1 gm2 gm3 | YC gm3
|
− 1
gm2 gm2
̃ v (s) =
A scp1 Y
1+ 0 − C
go1 GL
|scp2 g sC |
go1 go2 GL g − gm2 1+g 2 0
| o1 o1 o2 |
sCL gm3 gm3 sC Y
+ 1+ L + C
go1 go1 go2 GL GL
sCC scp2 gm3 sC
1+ − − 1+ 2
gm2 (1+sCC RC ) gm2 gm2 gm3
gm1 gm2 gm3 ro1 ro2 RL | sCC g
|
− m3 1
gm2 (1+sCC RC ) gm2
̃ v (s) =
A sCC RL
1+scp1 ro1 0 −
1+sCC RC
|sc r −g r 1+sC2 ro2 0 |
| p1 o1 m2 o1 |
sCC RL
sCL ro1 +gm3 ro1 gm3 ro2 1+sCL RL +
1+sCC RC
1
We now factor out 1+sC from the first column of the numerator determinant and the third
C RC
column of the denominator determinant. This factor cancels out leaving behind:
sCC scp2 gm3 sC2
+(1− − )(1+sCC RC ) 1+
gm2 gm2 gm2 gm3
gm1 gm2 gm3 ro1 ro2 RL | sCC gm3
|
− (1+sCC RC ) 1
gm2 gm2
̃ v (s) =
A 1+scp1 ro1 0 −sCC RL
|scp1 ro1 −gm2 ro1 1+sC2 ro2 0 |
sCL ro1 +gm3 ro1 gm3 ro2 (1+sCL RL )(1+sCC RC )+sCC RL
We may fully expand the numerator and denominator determinants now. An inspection of the
diagonal elements of the numerator determinant shows that the numerator polynomial is of
degree 2. Similarly, the main diagonal elements of the denominator determinant show that the
denominator polynomial is of degree 4. A full expansion would result in unmanageably large
number of terms. Therefore, we need to make some simplifications at this stage. Firstly, we
choose:
93
p C2
RC = where p = (7-10)
gm3 CF
Using Eq. (7-10), the transfer function reduces somewhat to:

sCC scp2 gm3 pC sC2
+(1− − )(1+s C ) 1+
gm2 gm2 gm2 gm3 gm3
gm1 gm2 gm3 ro1 ro2 RL | sCC gm3 pC
|
− (1+s C ) 1
gm2 gm2 gm3
̃ v (s) =
A 1+scp1 ro1 0 −sCC RL
scp1 ro1 −gm2 ro1 1+sC2 ro2 0
| |
pCC
sCL ro1 +gm3 ro1 gm3 ro2 (1+sCL RL )(1+s )+sCC RL
gm3
Full expansion of the determinants still yields large number of terms, particularly in the
denominator. Therefore, and secondly, we make use of Eq. (7-3) to approximate the results of
the expansions and arrive at the transfer function in its final form as:
pCC CF
gm1 gm2 gm3 ro1 ro2 RL [s( + ) + 1]
gm3 gm2
̃ v (s) =
A pcp1 CC C2 CL ro1 ro2 RL (7-11)
s4 + s3 CC C2 CL ro1 ro2 RL + s2 CC CF gm3 ro1 ro2 RL + sCC gm2 gm3 ro1 ro2 RL +1
gm3
We can see that the choice in Eq. (7-10) moves a possible right half s-plane zero to infinity
leaving behind a left half s-plane one. This result is achieved by removal of the s2 term in the
numerator by cancellation.
7.3. Poles and zeros of the Transfer Function
Factorization
Factorizing the denominator of Eq. (7-11) using Eq. (2-40):

pCC C
gm1 gm2 gm3 ro1 ro2 RL [s( + F ) + 1]
gm3 gm2
̃ v (s) =
A pcp1 C2 CL C C C
(sCC gm2 gm3 ro1 ro2 RL +1)[s3 + s2 2 L + s F +1]
gm2 g2
m3
gm2 gm3 gm2
Factorizing the cubic polynomial in the denominator using Eq. (2-57):

pCC C
gm1 gm2 gm3 ro1 ro2 RL [s(+ F ) + 1]
gm3 gm2
̃ v (s) =
A C C C pcp1 (7-12)
(sCC gm2 gm3 ro1 ro2 RL +1)(s2 2 L + s F +1)(s +1)
gm2 gm3 gm2 gm3
Poles and Zeros

A0 (sτz +1)
̃ v (s) =
A 2 2 (7-13)
(sτ p1 +1)(s τp23 +2sδp23 τp23 +1)(sτp4 +1)
1 1
ωp1 = τ =C (7-14)
94
Using Eq. (2-19) the natural frequency and damping factor of the second and third poles are
given by:
1 gm2 gm3
ωp23 = =√ (7-15)
τp23 C2 CL
CF gm3
δp23 = √g (7-16)
2√C2 CL m2

1 g
ωp4 = τ = pcm3 (7-17)
p4 p1

1 1
ωz = τ = pCC CF (7-18)
z +
gm3 gm2
7.4. Design to meet Specifications
Comparing (7-10) and (7-11) magnitude of the DC gain is given by:
A0 = g m1 g m2 g m3 ro1 ro2 R L (7-19)
gm1
ω0 = (7-20)
CC
ω0
ωp1 = (7-21)
A0
ωp23 = σω0 (7-22)
ωz = μωp23 = σμω0 (7-23)
We do not define any PZL parameter for ωp4 noting it to be a high-frequency far-away pole.
However, we can write the pole in terms of ω0 using Eqs. (7-17) and (7-20) as:
95
gm3 CC
ωp4 = ω0 (7-24)
pgm1 cp1
Combining (7-10), (7-15), (7-18), (7-22) and (7-23) we arrive at the quadratic equation:
gm3 √C2 CL gm3 pCC

− √g + =0 (7-25)
gm2 μCF m2 CF
Using Eqs. (2-14) and (7-10) the preferred solution for Eq. (7-25) is given by:
gm3 κ√C2 CL C 1 C
√g = where, κ = 1 + √1 − 4μ2 CC provided μ ≤ 2 √CL (7-26)
m2 2μCF L C
Combining Eqs. (7-10), (7-17), (7-20), (7-22) and (7-26):

gm2 2σμCF
= (-)
gm1 κCC
and
gm3 κσpCL
= (7-28)
gm1 2μCC

κ
δp23 = 4μ (7-29)
2ω0 δp23 τp23

ϕm = 1800 + tan−1(ω0 τz ) − tan−1 (ω0 τp1 ) − tan−1 ( ) − tan−1 (ω0 τp4 )
1−ω20 τ2p23
Substituting (7-21) to (7-24) and (7-28) in above:

1 2σδp23 2μcp1
ϕm = 1800 + tan−1 (σμ) − tan−1(A0 ) − tan−1 ( ) − tan−1 ( κσC ) (7-30)
σ2 −1 L
96
The table below lists the target performance parameters of the amplifier.

We decide on σ = 2.5974 and μ = 0.77 placing ωz slightly behind ωp23 in frequency with
σμ = 2. Using these values of σ and μ in Eq. (7-30), assuming A0 to be a large number and
̃ m = 91.390 .
neglecting contribution due to ωp4 , the estimated phase margin is ϕ
Using g m1 = 500μS and CC = 1.6pF, f0 = 49.74MHz using Eq. (7-20).
Next, κ = 1.606 using Eq. (7-26) and δp23 = 0.52 using (7-29).
We use CF = 1.6pF, cp1 = 100fF and cp2 = 200fF.
Then, C2 = 1.8pF using Eq. (7-7) and p = 1.125 using Eq. (7-10).
Next, we find g m2 = 1.25mS using Eq. (7-27) and g m3 = 5.71mS using Eq. (7-28).
Then, R C = 197Ω using Eq. (7-10).
We use ro1 = 200kΩ and ro2 = 55kΩ.
Then, A0 = 392,562.5 ≈ 111.88dB using Eq. (7-19).
Now, we can find a more accurate phase margin figure using (7-30):
ϕm = 1800 + 26.570 − 900 − 25.180 − 0.350 = 91.040 .
97

12 Feedforward capacitance CF 1.6 pF

3 Zero fz 99.48 MHz


98
99
100
but not as much as the amplifiers in Chapters 4 and 5. The presence of one more amplifying
stage like the amplifier in Chapter 6 is responsible for this behaviour.
It may be noted from Eqs. (7-7) and (7-10) that ‘p’ is nearly a constant with a value close to 1
and from Eq. (7-26) that κ behaves similarly with its values ranging from 1 to 2. Therefore,
Eq. (7-28) indicates that g m3 requirement for this amplifier is nearly proportional to CL . Thus,
large values of g m3 would be needed for the amplifier to drive large values of CL , causing
power and area consumption to go up. On the other hand, small values of g m3 would be
required for the amplifier to drive small values of CL , causing the DC gain to go down.
However, Eqs. (7-27) and (7-28) show that by choosing PZL or circuit parameters
appropriately, the abovementioned problems can be overcome to some extent. In conclusion,
this amplifier behaves more like the one in Chapter 4 with capacitive loads.
Unlike the amplifier in Chapter 6, it is difficult to achieve large δp23 values for this amplifier.
This will be evident comparing Eqs. (6-32) and (7-29). Consequently, the loop-gain
magnitude and phase plots for this amplifier are not as smooth as those for amplifiers in
Chapters 4 and 6.
Tab. 7-6 shows that the evaluated fc value deviates significantly from the calculated f0 one,
and this reflects in the ϕm value too. As discussed in Section 2.4.5, this is likely to happen
since both fz and fp23 are located close to f0 with fz being closer, as shown in Tab. 7-4. Small
δp23 value may also be partially responsible.
From the first two rows of Tab. A17-3 one can see that this amplifier consumes less area but
more power than the amplifier in Chapter 6.
101
Chapter 8 Three-Stage Amplifier Miller, Passive FF CS
CHAPTER 8
Three-Stage Miller Compensated Amplifier with
Passive Feedforward around Centre-Stage
In Chapter 7, we saw how compensation could be achieved using feedforward around the
centre stage of a three-stage CMOS amplifier using an NPN Bipolar transistor in series with a
capacitor in the feedforward path. However, an extra masking step is required to fabricate the
NPN device, leading to higher cost. Two publications, one in 2014 [R1-14] and the other in
2016 [R1-15], addressed this problem.
Eliminating the bipolar device, the above publications proposed the usage of passive
feedforward needing just one capacitor in the feedforward path. However, for the
feedforward to dominate the signal fed to the output stage at high frequencies, the bandwidth
of the centre-stage had to be reduced. This reduction was achieved without many side-effects
using a passive RC network and a MOS transistor, an idea published in 2008 [R1-12]. As it
turns out, the passive network does not affect the amplifier performance appreciably so long
as its time-constant is above a minimum value helping, in addition, to minimise signal
feedback through the feedforward path.
In this chapter we are going to discuss the amplifier published in 2016 mentioned above. This
implementation uses Miller compensation discussed in Chapter 4 for its overall compensation
like the amplifier in Chapter 7.
102
Circuit Diagram

1 First stage transconductance (MN1 or MN2) g m1
13 Resistance in the second stage bandwidth limiting network RD
14 Capacitance in the second stage bandwidth limiting network CD
Block Diagram
103
Referring to Figs. 8-1, 8-2 and Tab. 8-1, transistors MN1, MN2, MN3, MP1 and MP2 constitute
either MN1 or MN2. Transistors MP3, MP4, MN4 and MN5 constitute the second stage
represented by the block marked g m2 where g m2 is the transconductance of MP3 or MP4.
Transistors MN6 and MP5 make up the third stage represented by the block marked g m3 where
g m3 is the transconductance of MN6. Feedforward path around the second stage is provided
through the capacitor CF. RC and CC provide the usual Miller compensation for the amplifier.
RD and CD along with MP4 form a network to limit the bandwidth of the second stage and
enable feedforward through CF at high frequencies. This network can be shown to be
equivalent to a RC series network connected from the second stage output node to ground
[R1-12]. The components of this equivalent network are given by:
1
cD = g m2 R D CD and rD = g (8-1)
m2
shown below:
simplified in Fig. 8-3 as per discussions in Section 3.5. The network RD, CD, MP4 in Fig. 8-1
has been replaced with its approximate equivalent as in Fig. 8-2 and is given by Eq. (8-1).

1 1 1 1
g o1 = r , g o2 = r , g o3 = r and GL = R (8-2)
o1 o2 o3 L

1 jωCC 1 jωgm2 RD CD
yC = 1 = jωR and yD = 1 = using Eq. (8-1) (8-3)
RC + C CC +1 rD + jωRD CD +1
jωCC jωcD
104
g m1 , g m2 , g m3 ≫ g o1 , g o2 , GL and cp1 , cp2 ≪ CC , CD , CF , CL (8-4)
(g o1 + scp1 + sCF + YC )V1 − sCF V2 − YC Vo = −g m1 Vi (8-5)
−(g m2 + sCF )V1 + (g o2 + scp2 + sCF + YD )V2 = 0 (8-6)
−YC V1 + g m3 V2 + (GL + sCL + YC )Vo = 0 (8-7)
We now define:
C1 = cp1 + CF and C2 = cp2 + CF (8-8)
g o1 + sC1 + YC −sCF −YC V1 −g m1 Vi

[ −g m2 − sCF g o2 + sC2 + YD 0 ] [V2 ] = [ 0 ] (8-9)
−YC g m3 GL + sCL + YC Vo 0
Applying Cramer’s rule to solve for Vo from Eq. (8-9):

go1 +sC1 +YC −sCF −gm1 Vi
| −gm2 −sCF go2 +sC2 +YD 0 |
−YC gm3 0
Vo = go1 + sC1 +YC −sCF −YC
| −gm2 −sCF go2 +sC2 +YD 0 |
−gm2 −sCF go2 +sC2 +YD
−gm1 Vi | |
−YC gm3
Vo = go1 +sC1 +YC −sCF −YC
| −gm2 −sCF go2 +sC2 +YD 0 |
Whence we find at the transfer function to be:

−gm2 −sCF go2 +sC2 +YD
Vo (s) −gm1 | |
−YC gm3
Av (s) = = go1 +sC1 +YC −sCF −YC
Vi (s)
| −gm2 −sCF go2 +sC2 +YD 0 |
Replacing the first row of the numerator determinant by the sum of its first and second rows
and replacing the first column of the denominator determinant by the sum of its first and third
columns:
−gm2 −sCF −YC gm3 +go2 +sC2 +YD
−gm1 | |
−YC gm3
Av (s) = go1 +sC1 −sCF −YC
|−gm2 −sCF go2 +sC2 +YD 0 |
GL +sCL gm3 GL +sCL +YC
105
Replacing the second column of the denominator determinant by the sum of its first and
second columns and using Eq. (8-8) for simplification:
−g −sCF −YC gm3 +go2 +sC2 +YD
−gm1 | m2 |
−YC gm3
Av (s) = go1 +sC1 go1 +scp1 −YC
|−gm2 −sCF go2 −gm2 +scp2 +YD 0 |
GL +sCL gm3 +GL +sCL GL +sCL +YC

−gm2 −sCF −YC gm3 +sC2 +YD
−gm1 | |
̃ v (s) = −YC gm3
A go1 +sC1 go1 +scp1 −YC
|−gm2 −sCF go2 −gm2 +scp2 +YD 0 |
GL +sCL gm3 +sCL GL +sCL +YC
determinant and g o1 , g o2 and GL from the first, second and the third columns respectively of
the denominator determinant:
sC Y sC2 Y
1+ F + C 1+ + D
gm2 gm2 gm3 gm3
gm1 gm2 gm3 | Y
|
C 1
gm2
̃ v (s) =
A sC1 go1 scp1 Y
1+ + − C
go1 go2 go2 GL
| g sC g scp2 YD |
go1 go2 GL − gm2 −g F 1− m2 + +
go2 go2 go2
0
| o1 o1 |
GL sCL gm3 sCL sC Y
+ + 1+ L + C
go1 go1 go2 go2 GL GL
Replacing the conductances using Eq. (8-2) and admittances using Eq. (8-3):
sCC sgm2 RD CD
sCF gm2 sC2 gm3
|1+gm2 + sRCCC +1 1+gm3 + sRD CD +1 |
gm1 gm2 gm3 ro1 ro2 RL sCC
| |
gm2
1
sRCCC +1
̃ v (s) =
A ro2 sCC RL
1+sC1 ro1 +scp1 ro2 −
ro1 sRC CC +1
| sg r R C |
−gm2 ro1 −sCF ro1 1−gm2 ro2 +scp2 ro2 + m2 o2 D D 0
sRD CD +1
| |
ro1 sCC RL
+sCL ro1 gm3 ro2 +sCL ro2 1+sCL RL +
RL sRCCC +1
1
We now factor out sR from the first column of the numerator determinant as well as the
C CC +1
1
third column of the denominator determinant. At the same time, we factor out from
sRD CD +1
the second column of both numerator and denominator determinants. The product
1
(sRC CC +1)(sRD CD +1)
of the above two factors, being factors of both the numerator and
denominator, cancel out leaving behind:
106
sC sC sC2 sg R C
( F +1)(sRC CC +1)+ C ( +1)(sRD CD +1)+ m2 D D
g gm2 gm3 gm3
gm1 gm2 gm3 ro1 ro2 RL | m2 sC
|
C
sRD CD +1
gm2
̃ v (s) =
A r
1+sC1 ro1 ( o2 +scp1 ro2 )(sRD CD +1) −sCC RL
ro1
|−g r −sC r (1−gm2 ro2 +scp2 ro2 )(sRD CD +1)+sgm2 ro2 RD CD 0 |
| m2 o1 F o1 |
ro1
+sCL ro1 (gm3 ro2 +sCL ro2 )(sRD CD +1) (sCL RL +1)(sRC CC +1)+sCC RL
RL
We may fully expand the numerator and denominator determinants now. An inspection of the
diagonal elements of the numerator determinant show that the numerator polynomial is of
degree 3. Similarly, the main diagonal elements of the denominator determinant show that the
denominator polynomial is of degree 5. A full expansion would result in unmanageably large
number of terms especially in the denominator. Therefore, we need to make some
simplifications at this stage. Firstly, we choose:
p C cp2
RC = g where p = C2 and we define q = (8-10)
m3 F CF
Using Eq. (8-10) and simplifying the element 𝑎22 in the denominator determinant:
sC pC sC sC2 sg R C
( F +1)(s C +1)+ C ( +1)(sRD CD +1)+ m2 D D
g gm3 gm2 gm3 gm3
gm1 gm2 gm3 ro1 ro2 RL | m2 sC
|
C sRD CD +1
gm2
̃ v (s) =
A r
1+sC1 ro1 ( o2 +scp1 ro2 )(sRD CD +1) −sCC RL
ro1
|−gm2 ro1 −sCF ro1 1−gm2 ro2 +sRD CD +scp2 ro2 (sRD CD +1) 0 |
| |
ro1 pCC
+sCL ro1 (gm3 ro2 +sCL ro2 )(sRD CD +1) (sCL RL +1)(s +1)+sCC RL
RL gm3
Secondly, we make use of Eqs. (8-3) and (8-10) to approximate and simplify the results of the
expansions to arrive at the transfer function in its final form as:
qCC CD RD CF CD RD pC C
gm1 gm2 gm3 ro1 ro2 RL [s2 ( + )+s(CD RD + C + F )+1]
gm3 gm2 gm3 gm2
̃ v (s) =
A (8-11)
(cp1 +cp2 )C2 CC CL CD RD ro1 ro2 RL
s5 +s4 [C2 CC CL +(cp1 +cp2 )CF (CC +CL )]CD RD ro1 ro2 RL
gm3
g
+s3 (CL + m3 CF )CC CD gm2 RD ro1 ro2 RL +s2 CC CD gm2 gm3 RD ro1 ro2 RL +sCC gm2 gm3 ro1 ro2 RL +1
gm2
We can see that the choice in Eq. (8-10) moves a possible right half s-plane zero to infinity
leaving behind two left half s-plane ones. This result is achieved by removal of the s3 term in
the numerator by cancellation.
Factorization
For factorisation, we need to approximate the numerator of (8-11) further assuming:

pCC
CD R D ≫ g (8-12)
m3
Eqs. (8-8), (8-10) and (8-12) show that ‘p’ in coefficient of ‘s’ in the numerator quadratic
polynomial can be replaced with ‘q’. Doing that and factorizing the denominator of Eq. (8-
11) using Eq. (2-40) we arrive at:
107
qCC CD RD CF CD RD qC C
gm1 gm2 gm3 ro1 ro2 RL [s2 ( + )+s(CD RD + C + F )+1]
gm3 gm2 gm3 gm2
̃ v (s) =
A g
(cp1 +cp2 )C2 CL CD RD (CL + m3 CF )CD RD
(sCC gm2 gm3 ro1 ro2 RL +1)[s4 +s3 C3 CL CD RD + s2 gm2
+ sCD RD +1]
gm2 g2
m3
gm2 gm3 gm3
where:
(cp1 +cp2 )(CL +CC )

C3 = cp2 + CF [1 + ] (8-13)
CL CC
The numerator can now be factorised using Eq. (2-24). The bi-quadratic polynomial in the
denominator can be factorised once more using Eq. (2-40). Thus, we arrive at:
qCC CF
gm1 gm2 gm3 ro1 ro2 RL (sCD RD +1)[s( + )+1]
gm3 gm2
̃ v (s) =
A g
(cp1 +cp2 )C2 CL C C CL + m3 CF
gm2
(sCC gm2 gm3 ro1 ro2 RL +1)(sCD RD +1)[s3 2 +s2 3 L +s +1]
gm2 gm3 gm2 gm3 gm3
The factor (sCD R D + 1) appears in both numerator and denominator and, therefore, cancel
each other. The cubic polynomial in the denominator can be factorised using Eq. (2-57) and
thus we obtain:
qCC CF
gm1 gm2 gm3 ro1 ro2 RL [s(
+ ) + 1]
gm3 gm2
̃ v (s) =
A C C C g +C (8-14)
(sCC gm2 gm3 ro1 ro2 RL +1)(s2 3 L +s L m2 F gm3 + 1)(s Ca + 1)
gm2 gm3 gm2 gm3 gm3
where:
1 1 1 1
=c + pC + pC (8-15)
Ca p1 +cp2 L C
Poles and Zeros

A0 (sτz +1)
̃ v (s) =
A 2 2
(8-16)
(sτ p1 +1)(s τp23 +2sδp23 τp23 +1)(sτp4 +1)
1 1
ωp1 = τ =C (8-17)
Using Eq. (2-30) the natural frequency and damping factor of the second and third poles are
given by:
gm2 gm3
ωp23 = √ (8-18)
C3 CL
m2 g CL +gm3 CF
δp23 = 2√g (8-19)
m2 gm3 C3 CL
108
1 gm3
ωp4 = = (8-20)
τp4 Ca

1 1
ωz = τ = qCC CF (8-21)
z +
gm3 gm2
A0 = g m1 g m2 g m3 ro1 ro2 R L (8-22)
gm1
ω0 = (8-23)
CC
We do not define a PZL parameter for ωp1 noting that it is a low-frequency far-away pole.
However, it can be written in terms of ω0 by re-writing Eq. (2-63) as:
ω0
ωp1 = (8-24)
A0
ωp23 = σω0 (8-25)
ωz = μωp23 = σμω0 (8-26)
We do not define any PZL parameter for ωp4 noting that it is a high-frequency far-away pole.
However, we can write the pole in terms of ω0 using Eqs. (8-20) and (8-23) as:
g C
ωp4 = gm3Cc ω0 (8-27)
m1 a
Combining Eqs. (8-10), (8-18), (8-21), (8-25) and (8-26) we arrive at the quadratic equation:
gm3 √C3 CL gm3 qCC

− √g + =0 (8-28)
gm2 μCF m2 CF
Using Eqs. (2-14) and (8-10) the preferred solution for Eq. (7-28) is given by:
109
gm3 κ√C3 CL cp2 CC 1 C C

√g = where, κ = 1 + √1 − 4μ2 provided μ ≤ 2 √c 3 CL (8-29)
m2 2μCF C3 CL p2 C
Combining Eqs. (8-18), (8-23), (8-25) and (8-29):

gm2 2σμCF
= (8-30)
gm1 κCC
and
gm3 κσC C
= 2μC 3CL (8-31)
gm1 F C

κ μC
δp23 = 4μ + κCF (8-32)
3
2ω0 τp23 δp23

ϕm = 1800 + tan−1(ω0 τz ) − tan−1 (ω0 τp1 ) − tan−1 ( ) − tan−1(ω0 τp4 )
1−ω20 τ2p23
Using Eqs. (8-24) to (8-27) and (8-31) in the above we arrive at:
1 2σδp23 2μC C
ϕm = 1800 + tan−1 (σμ) − tan−1(A0 ) − tan−1 ( ) − tan−1 (kσCa CF ) (8-33)
σ2 −1 3 L
No. Performance parameters Symbol Value Units

2 Unity gain frequency f0 ~ 50 MHz
We decide on σ = 2.2 and μ = 1 locating ωz right on top of ωp23 in frequency with σμ =

2.2. Using these values of σ and μ in Eq. (8-33), assuming A0 to be a large number and
̃ m = 70.530 .
neglecting contribution due to ωp4 , the estimated phase margin is ϕ
110
Using g m1 = 500μS and CC = 1.6pF so that f0 = 49.74MHz from Eq. (8-23).
We also use cp1 = 100fF and cp2 = 200fF with CF = 1pF.
Then, C2 = 1.2pF, C3 = 1.44pF, Ca = 250fF using Eqs. (8-8), (8-10), (8-13) and (8-15).
Then, κ = 1.923 using Eq. (8-29).
Subsequently, g m3 = 5.71mS, g m2 = 715μS and δp23 = 0.84 using Eqs. (8-30) to (8-32)
respectively. Thus, R C = 210Ω using Eq. (8-10).
Next, we choose R D = 10kΩ and CD = 1pF so that the requirement specified by Eq. (8-12) is
met with ease.
Using ro1 = 200kΩ and ro2 = 100kΩ, the DC gain is found to be A0 = 408,265 ≈
12.22dB using Eq. (8-22).
̃ m = 1800 + 24.440 − 900 − 43.910 − 0.780 = 69.750 .

ϕ
No. Circuit parameters Symbol Value Units

4 Second stage transconductance g m2 715 μS
12 Feedforward capacitance CF 1 pF
13 Second stage bandwidth limiting resistance RD 10 kΩ
14 Second stage bandwidth limiting capacitance CD 1 pF
No. Description Symbol Value Units

2 Unity gain frequency f0 49.74 MHz
111

Tab. 8-6. Comparison of performance parameters
No. Performance parameters Symbol Calculated Evaluated Specs. Units

1 DC gain magnitude A0 112.22 112 > 100 dB
2 Unity gain frequency f0 /fc 49.74 55 ~ 50 MHz
112
Fig 8.4. Unity feedback factor loop-gain magnitude response for the amplifier.
Fig 8.5. Unity feedback factor loop-gain phase response for the amplifier.
113
Tab. 8-7. Data listing for loop-gain response plots in Figs. 8.4 and 8.5.
114
DC gains with large or medium values of R L . The DC gain does drops with small R L values
but not as much as the amplifiers in chapters 4 and 5 because of the presence of one more
amplifying stage. The amplifiers in chapters 6 and 7 behave similarly.
From Eqs. (8-4), (8-13) and (8-29) it may be noted that κ is a near constant with values
ranging from 1 to 2 while C3 : CF behaves similarly with its values approximately in the same
range. Therefore, Eq. (8-31) indicates that g m3 requirement for this amplifier is nearly
proportional to CL . Thus, large values of g m3 would be needed for the amplifier to drive large
values of CL , causing power and area consumption to go up. On the other hand, small values
of g m3 would be required for the amplifier to drive small values of CL , causing the DC gain
to go down.
However, Eqs. (8-30) and (8-31) also show that by choosing PZL and circuit parameters
appropriately, the abovementioned problems can be overcome to some extent. In conclusion,
this amplifier behaves more like the ones in Chapters 4 and 7 with capacitive loads.
Like the amplifier in Chapter 6 but unlike the amplifier in Chapter 7, good δp23 values can be
achieved for this amplifier. This will be evident from Eqs. (6-32), (7-29) and (8-32).
Consequently, the gain magnitude and phase plots for this amplifier are nearly as smooth as
those for amplifiers in Chapters 4 and 6.
Tab. 8-6 shows that the evaluated fc value deviates significantly from the calculated fc one,
since both fz and fp23 are located close to f0 , as shown in Tab. 8-4. However, the deviation is
unduly large for a good δp23 value. Therefore, it is likely that the approximation errors
involved in finding high frequency poles/zeros contributed significantly to this case.
The first three rows of Tab. A17-3 show that this amplifier has the best cell statistics among
all the three-stage amplifiers discussed so far.
115
Chapter 9 Three-Stage Amplifier Cascode-Miller, Passive FF CS
CHAPTER 9
Three-Stage Cascode-Miller Compensated Amplifier with
Passive Feedforward around Centre-Stage
In Chapter 7, we saw how compensation could be achieved using feedforward around the
centre stage of a three-stage CMOS amplifier using an NPN Bipolar transistor in series with a
capacitor in the feedforward path. However, an extra masking step is required to fabricate the
NPN device, leading to higher cost. Two publications, one in 2014 [R1-14] and the other in
2016 [R1-15], addressed this problem.
Eliminating the bipolar device, the above publications proposed the usage of passive
feedforward needing just one capacitor in the feedforward path. However, for the
feedforward to dominate the signal fed to the output stage at high frequencies, the bandwidth
of the centre-stage had to be reduced. This reduction was achieved without many side-effects
using a passive RC network and a MOS transistor, an idea published in 2008 [R1-12]. As it
turns out, the passive network does not affect the amplifier performance appreciably so long
as its time-constant is above a minimum value helping, in addition, to minimise signal
feedback through the feedforward path.
In this chapter we are going to discuss the amplifier published in 2014 mentioned above. This
implementation uses Cascode-Miller compensation discussed in Chapter 5 for its overall
compensation.
116
Tab. 9-1. Circuit parameters for amplifier.

3 Parasitic capacitance loading first stage (node N1) cp1
10 Cascode transistor transconductance (MN4) g mc
13 Resistance in the second stage bandwidth limiting network RD
14 Capacitance in the second stage bandwidth limiting network CD
Block Diagram
117
Referring to Fig. 9-1, Fig. 9-2 and Tab. 9-1, transistors MP1, MP2, MP3, MN1, MN2, MN3, MN4,
MP4 and MP5 constitute the folded-cascode first stage represented by the block labelled g m1
where g m1 is the transconductance of either MP1 or MP2. The compensation capacitor CC is
connected to the first stage output through the cascode transistor MN4. Transistors MN5, MN6,
MP6 and MP7 constitute the second stage represented by the block labelled g m2 where g m2 is
the transconductance of MP6 or MP7. Transistors MP8 and MN7 make up the third stage
represented by the block labelled g m3 where g m3 is the transconductance of MN7.
Feedforward path around the second stage is provided through the capacitor CF. RD and CD
form a network along with MP7 to limit the bandwidth of the second stage and enable
feedforward through CF. This network can be shown to be equivalent to a RC series network
connected from the second stage output node to ground [R1-12]. The components of this
equivalent network are given by:
1
cD = g m2 R D CD and rD = g (9-1)
m2
The simplified small-signal equivalent for the amplifier can be drawn from its block diagram
as shown:
Other than low-frequency MOS models being used, the first stage in Fig. 9.1 has been
simplified in line as per the discussions in Section 3.5. Output resistance and gate-source
capacitance of the cascode transistor MN4 and output resistance of its bias transistor MN2 have
not been included in Figs. 9-2 and 9-3 since we have already shown in Sections 5.2.1 and
5.2.2 that these circuit parameters have minimal effect on the overall performance of the
amplifier.

1 1 1 1
g o1 = r , g o2 = r , g o3 = r and GL = R (9-2)
o1 o2 o3 L
118

1 jωgm2 RD CD
yD = 1 = using Eq. (9-1) (9-3)
rD + jωRD CD +1
jωcD
g m1 , g mc , g m2 , g m3 ≫ g o1 , g o2 , GL and cp1 , cp2 ≪ CC , CD , CF , CL (9-4)
Using Laplace transforms and KCL at nodes N1, Nc, N2 and OUT we have:
Vi
(g o1 + scp1 + sCF )V1 − g mc Vc − sCF V2 = −g m1 (9-5)
2
Vi
(g mc + sCC )Vc − sCC Vo = −g m1 (9-6)
2
−(g m2 + sCF )V1 + (g o2 + scp2 + sCF + YD )V2 = 0 (9-7)
−sCC Vc + g m3 V2 + (GL + sCL + sCC )Vo = 0 (9-8)
We now define:
C1 = cp1 + CF and C2 = cp2 + CF (9-9)
Eqs. (9-5) to (9-8) can be written in vector-matrix form using (9-9) as:
V
g o1 + sC1 −g mc −sCF 0 V1 −g m1 2i
0 g mc + sCC 0 −sCC V Vi
[ ] [ c ] = −g m1 2 (9-10)
−g m2 − sCF 0 g o2 + sC2 + YD 0 V2
0 −sCC g m3 GL + sCL + sCC Vo 0
[ 0 ]

V
go1 +sC1 −gmc −sCF −gm1 i
2
| V |
0 gmc +sCC 0 −gm1 i
| 2|
−gm2 −sCF 0 go2 +sC2 +YD 0
0 −sCC gm3 0
Vo = go1 +sC1 −gmc −sCF 0
0 gmc +sCC 0 −sCC
| |
0 −sCC gm3 GL +sCL +sCC
Using cofactor expansion of the numerator determinant along its fourth column:
0 gmc +sCC 0 go1 +sC1 −gmc −sCF
V V
gm1 i|−gm2 −sCF 0 go2 +sC2 +YD |−gm1 i|−gm2 −sCF 0 go2 +sC2 +YD |
2 2
0 −sCC gm3 0 −sCC gm3
Vo = go1 +sC1 −gmc −sCF 0
0 gmc +sCC 0 −sCC
| |
119
0 gmc +sCC 0 go1 +sC1 −gmc −sCF

gm1 g
|−gm2 −sCF 0 go2 +sC2 +YD | − m1 |−gm2 −sCF 0 go2 +sC2 +YD |
2 2
Vo (s) 0 −sCC gm3 0 −sCC gm3
Av (s) = = go1 +sC1 −gmc −sCF 0
Vi (s)
0 gmc +sCC 0 −sCC
| |
For the first determinant in the numerator, we replace its third column with the sum of its first
and third columns. For the second determinant in the numerator, we replace its first column
with the sum of its first and second columns. For the denominator determinant we replace its
third column with the sum of its first and third columns and its second column by the sum of
its second and fourth columns and using Eq. (9-9) for simplification:
0 gmc +sCC 0 go1 −gmc +sC1 −gmc −sCF
gm1
|−gm2 −sCF 0 go2 −gm2 +scp2 +YD |− gm1 | −gm2 −sCF 0 go2 +sC2 +YD |
2 2
0 −sCC gm3 −sCC −sCC gm3
Av (s) = go1 +sC1 −gmc go1 +scp1 0
0 gmc 0 −sCC
|−g −sC 0 go2 −gm2 +scp2 +YD 0 |
m2 F
0 GL +sCL gm3 GL +sCL +sCC
Now we replace the third column of the second determinant in the numerator by the sum of
its first and third columns and using Eq. (9-9) for simplification:
0 gmc +sCC 0 go1 −gmc +sC1 −gmc go1 −gmc +scp1
gm1
|−gm2 −sCF 0 go2 −gm2 +scp2 +YD |− gm1 | −gm2 −sCF 0 go2 −gm2 +scp2 +YD |
2 2
Av (s) = go1 +sC1 −gmc go1 +scp1 0
0 gmc 0 −sCC
|−g −sC 0 go2 −gm2 +scp2 +YD 0 |
m2 F

0 gmc +sCC 0 −gmc +sC1 −gmc −gmc +scp1
gm1
|−gm2 −sCF 0 −gm2 +scp2 +YD |− gm1 |−gm2 −sCF 0 −gm2 +scp2 +YD |
2 2
̃ v (s) =
A go1 +sC1 −gmc go1 +scp1 0
0 gmc 0 −sCC
| |
−gm2 −sCF 0 go2 −gm2 +scp2 +YD 0
We now factor out g m2 , g mc , g m3 from the first, second, third columns respectively of the
first numerator determinant and −g m2 , g mc , g m3 from the first, second, third columns
respectively of the second numerator determinant. At the same time, we factor out g o1 , g mc ,
g o2 and GL from the first, second, third and fourth columns respectively of the denominator
determinant to arrive at:
120
sCC gmc sC1 g scp1

0 1+ 0 − −1 − mc +
gmc gm2 gm2 gm3 gm3
1 | sC g scp2 YD | | sC gm2 scp2 YD |
g g g g −1− F 0 − m2 + + + 1+g F 0 − + +
2 m1 m2 mc m3 | gm2 gm3 gm3 gm3 | | m2 gm3 gm3 gm3 |
sC sCC sC
[ 0 − C 1 − C 1 ]
gm2 gmc
̃ v (s) =
A
gmc
sC go1 scp1
1+ 1 −1 + 0
go1 go2 go2
| sC |
0 1 0 − C
GL
go1 gmc go2 GL g sC g scp2 YD
− m2 − F 0 1− m2 + + 0
| go1 go1 go2 go2 go2 |
GL sCL gm3 sC sC
0 + 1+ L + C
gmc gmc go2 GL GL
Replacing conductances using Eq. (9-2) and admittances using Eq. (9-3) and simplifying:
sCC
0 1+ 0
gmc
| sgm2 RD CD |
1 sC g scp2
g g g r r R gm3
2 m1 m2 m3 o1 o2 L −1− F 0 − m2 + +
| gm2 gm3 gm3 sRD CD +1 |
sCC
[ 0 − 1
gmc
gmc sC1 g sc p1
− −1 − mc +
gm2 gm2 gm3 gm3
| sgm2 RD CD |
+ 1+ sCF g scp2 gm3
0 − m2 + +
| gm2 gm3 gm3 sRD CD +1 |
sCC sCC
− 1 ]
gm2 gmc
̃ v (s) =
A ro2
1+sC1 ro1 −1 +scp1 ro2 0
ro1
| 0 1 0 −sCC RL |
sg r R C
−gm2 ro1 −sCF ro1 0 1−gm2 ro2 +scp2 ro2 + m2 o2 D D 0
sRD CD +1
| |
1 sC
0 + L gm3 ro2 1+sCL RL +sCC RL
gmc RL gmc
1
We now factor out from the third column of both numerator and denominator
sRD CD +1
determinants. This factor, being common to both the numerator and denominator, cancel out
leaving behind:
sCC
0 1+ 0
gmc
1 | sC g scp2 sg R C |
g g g r r R −1− F 0 (sRD CD +1)(− m2 + )+ m2 D D
2 m1 m2 m3 o1 o2 L | gm2 gm3 gm3 gm3 |
sCC
[ 0 − sRD CD +1
gmc
gmc sC1 gmc scp1
− −1 (sRD CD +1)(− + )
gm2 gm2 gm3 gm3
| sC gm2 scp2 sgm2 RD CD |
+ 1+g F 0 (sRD CD +1)(− +
gm3 gm3
)+
gm3
| m2 |
sCC sCC
− sRD CD +1 ]
gm2 gmc
̃v =
A r
1+sC1 ro1 −1 (sRD CD +1)( o2 +scp1 ro2 ) 0
ro1
| 0 1 0 −sCC RL |
−gm2 ro1 −sCF ro1 0 (sRD CD +1)(1−gm2 ro2 +scp2 ro2 )+sgm2 ro2 RD CD 0
| |
1 sCL
0 + gm3 ro2 (sRD CD +1) 1+sCL RL +sCC RL
gmc RL gmc
We may fully expand the numerator determinants now. An inspection of the elements of the
numerator determinants show that the numerator polynomial is of degree 4. A full expansion
results in unmanageably large number of terms. We do not present all the terms here but use
121
Eq. (9-4) to approximate the results of the expansion. At the same time, we simplify the
element 𝑎33 of the denominator determinant to obtain:
cp2 CF CC CD RD
C C C R 1 1
gm1 gm2 gm3 ro1 ro2 RL [−s4 +s3 F C D D ( + )
gm2 gmc gm3 2gm2 gmc gm3
C C 1 1 C C C C R 1 1 C C R
+s2 { F C ( + )+ 1 C + C D D ( + )+ F D D }
2gm2 gmc gm3 2gmc gm3 2 gmc gm3 gm2
CC 1 1 CF
+s{ ( + )+ +CD RD }+1]
2 gmc gm3 gm2
̃ v (s) =
A r
1+sC1 ro1 −1 (sRD CD +1)( o2 +scp1 ro2 ) 0
ro1
| 0 1 0 −sCC RL |
−gm2 ro1 −sCF ro1 0 1−gm2 ro2 +sRD CD +scp2 ro2 (sRD CD +1) 0
| |
1 sCL
0 + gm3 ro2 (sRD CD +1) 1+sCL RL +sCC RL
gmc RL gmc
The denominator determinant may be fully expanded now. An inspection of the elements of
the denominator determinant show that the denominator polynomial is of degree 5. A full
expansion yields an unmanageably large number of terms. We do not present all the terms
here but approximate and simplify the denominator using Eqs. (9-4) and (9-9). Thus, we
arrive at the transfer function in its final form as:
cp2 CF CC CD RDC C C R 1 1
gm1 gm2 gm3 ro1 ro2 RL [−s4 +s3 F C D D ( + )
C F CC( 1 1 C1 CC + CC CD R D 1 1 C C R
+s2 { + )+ ( + )+ F D D }
CC 1 1 CF
+s{ ( + )+ +CD RD }+1]
2 gmc gm3 gm2
̃ v (s) =
A (9-11)
(cp1 +cp2 )CF CC CL CD ro1 ro2 RD RL g
s5 +s4 [cp1 CC CL m2 +(cp1 +cp2 )CF (CC +CL )]CD ro1 ro2 RD RL
gmc gmc
+s3 CF CC CD gm3 ro1 ro2 RD RL +s2 CC CD gm2 gm3 ro1 ro2 RD RL +sCC gm2 gm3 ro1 ro2 RL +1
Factorization
For factorisation, we need to approximate the coefficient of ‘s2’ in the numerator of (9-11)
further. We assume the last two terms are much larger than the first two terms, meaning:
C 1 1 C CF C 1 1 g C CC
CD R D [ 2C (g +g )+g F ] ≫g [ 2C (g + g ) + 2g m2g 1 ]
mc m3 m2 m2 mc m3 mc m3 CF
The above can be reduced, with the help of (9-9), to:
CF g2 C
CD R D ≫ g provided CF ≥ 2gm2g C (9-12)
m2 mc m3
However, we drop only the second term in the coefficient of ‘s2’ to re-write Eq. (9-11) as:
cp2 CF CC CD RDC C C R 1 1
gm1 gm2 gm3 ro1 ro2 RL [−s4 +s3 { F C D D ( + )}
C C 1 1 C C R 1 1 C C R
+s2 { F C ( + )+ C D D ( + )+ F D D }
2gm2 gmc gm3 2 gmc gm3 gm2
CC 1 1 CF
+s{ ( + )+ +CD RD }+1]
2 gmc gm3 gm2
̃ v (s) =
A (cp1 +cp2 )CF CC CL CD ro1 ro2 RD RL g
s5 +s4 [cp1 CC CL m2 +(cp1 +cp2 )CF (CC +CL )]CD ro1 ro2 RD RL
gmc gmc
+s3 CF CC CD gm3 ro1 ro2 RD RL +s2 CC CD gm2 gm3 ro1 ro2 RD RL +sCC gm2 gm3 ro1 ro2 RL +1
122
Subsequently, factorising the numerator using Eq. (2-58) with m = 3 and the denominator
using Eq. (2-40), we arrive at:
C C C R 1 1 C C 1 1 C C R 1 1 C C R
gm1 gm2 gm3 ro1 ro2 RL [s3 F C D D ( + )+s2 { F C ( + )+ C D D ( + )+ F D D }
2gm2 gmc gm3 2gm2 gmc gm3 2 gmc gm3 gm2
CC 1 1 CF 2cp2
+s{ ( + )+ +CD RD }+1](−s +1)
2 gmc gm3 gm2 gmc +gm3
̃ v (s) =
A (cp1 +cp2 )CF CL CD RD (cp1 +cp2 )CF CL CD RD C C R
(sCC gm2 gm3 ro1 ro2 RL +1)[s4 +s3 +s2 F D D +sCD RD +1]
gmc gm2 gm3 gm2 gm3 C3 gm2
where:
1 cp1 gm2 1 1 1
= [(c ]C + C + C (9-13)
C3 p1 +cp2 )gmc F L C
Factorizing, once more, the numerator using Eq. (2-30) and denominator using Eq. (2-40):
C C 1 1 2cp2
gm1 gm2 gm3 ro1 ro2 RL (sCD RD +1)(s F +1)[s C ( + )+1](−s +1)
gm2 2 gmc gm3 gmc +gm3
̃ v (s) =
A (cp1 +cp2 )CF CL (cp1 +cp2 )CF CL C
(sCC gm2 gm3 ro1 ro2 RL +1)(sCD RD +1)[s3 +s2 +s F +1]
The factor (sCD R D + 1) appears in both the numerator and denominator and, therefore,
cancel out and we arrive at the factorised transfer function in its final form as:
C C 1 1 2cp2
gm1 gm2 gm3 ro1 ro2 RL (s F +1)[s C ( + )+1](−s +1)
gm2 2 gmc gm3 gmc +gm3
̃ v (s) =
A (9-14)
(cp1 +cp2 )CF CL (cp1 +cp2 )CF CL C
(sCC gm2 gm3 ro1 ro2 RL +1)[s3 +s2 +s F +1]
The cubic polynomial in the denominator of Eq. (9-14) cannot be factorised using any of the
methods described in Section 2.2. Therefore, we must leave it unfactorized. The last three
poles of Eq. (9-14) will be located using PZL parameters as described in Section 2.4.3.
Poles and Zeros
Writing Eq. (9-14) in terms of its poles and zeros:

A0 (sτz1 +1)(sτz2 +1)(sτz3 +1)
̃ v (s) =
A 2 τ2 +2sδ (9-15)
(sτ p1 +1)(s p23 p23 τp23 +1)(sτp4 +1)
1 1
ωp1 = τ =C (9-16)
The first zero is given by:

1 gm2
ωz1 = τ = (9-17)
z1 CF
The second zero is given by:

1 2
ωz2 = τ = 1 1 (9-18)
z2 CC ( + )
gmc gm3
123
and the third (right-half plane) zero is given by:

1 gmc +gm3
ωz3 = τ = − (9-19)
z3 2cp2
A0 = g m1 g m2 g m3 ro1 ro2 R L (9-20)
We decide ωp1 to be the dominant pole. Then. using Eqs. (2-63), (9-16) and (9-20) the unity-
gm1
ω0 = (9-21)
CC
We do not define a PZL parameter for locating ωp1 noting that it is a low-frequency far-away
pole. However, it can be written in terms of ω0 by re-writing Eq. (2-63) as:
ω0
ωp1 = (9-22)
A0
We define PZL parameters σ, μ and λ for ωp23 , ωp4 and ωz1 such that:
ωp23 = σω0 (9-23)
ωp4 = λωp23 = σλω0 (9-24)
ωz1 = μωp23 = σμω0 (9-25)
We now combine Eqs. (9-18) and (9-21) to obtain:

1
ωz2 = gm1 g ω0 (9-26)
+ m1
2gmc 2gm3
Eq. (9-26) relates ωz2 to ω0 with transconductance ratios to be determined later. Therefore,
we do not define a PZL parameter for it. We do not define a PZL parameter for ωz3 too since
it is a high-frequency far-away zero, but we combine Eqs. (9-19) and (9-21) to obtain:
(gmc +gm3 )CC
ωz3 = − ω0 (9-27)
2gm1 cp2
124
Substituting Eqs. (9-23) and (9-24) into the last two factors in the denominator of Eq. (9-15)
and multiplying those, we arrive at the cubic polynomial:
1 λ+2δp23 1+2λδp23
s 3 σ3 λω3 + s 2 +s +1
0 σ2 λω20 σλω0
Equating the above with the cubic polynomial (the second factor) in the denominator of (9-
14) we find:
1 (cp1 +cp2 )CF CL

= (9-28)
σ3 λω30 gmc gm2 gm3
λ+2δp23 (cp1 +cp2 )CF CL

= (9-29)
σ2 λω20 gm2 gm3 C3
and
1+2λδp23 CF
=g (9-30)
σλω0 m2
Combining (9-17), (9-25) and (9-30):

1 1
δp23 = 2μ − 2λ (9-31)

gm2 σμCF
= (9-32)
gm1 CC

μ
gmc σ(1+μλ− )C3
λ
= (9-33)
gm1 μCC
gm3 σλ(cp1 +cp2 )CL

= μ (9-34)
gm1 (1+μλ− )C3 CC
λ
ϕm = 1800 + tan−1(ω0 τz1 ) + tan−1(ω0 τz2 ) + tan−1(ω0 τz3 ) − tan−1(ω0 τp1 )
2ω0 δp23 τp23

− tan−1 ( ) − tan−1 (ω0 τp4 )
1−ω20 τ2p23
Substituting Eqs. (9-22) to (9-27) in the above we arrive at:

1 g g 2gm1 cp2
ϕm = 1800 + tan−1 (σμ) + tan−1 (2gm1 + 2gm1 ) − tan−1 [(g ]
mc m3 mc +gm3 )CC
125
2σ 1
− tan−1(A0 ) − tan−1 [( ) δp23 ] − tan−1 ( ) (9-35)
σ2 −1 σλ


2
We decide on σ = 3, μ = 3 and λ = 2 locating ωz slightly behind and ωp4 ahead of ωp23 in
frequency with σμ = 2 and σλ = 6. Using these values of σ, μ and λ in Eq. (9-35), assuming
A0 to be a large number and neglecting contributions due to ωz2 and ωz3 , the estimated phase
̃ m = 86.550 .
margin is ϕ
Next, we find δp23 = 0.5 using Eq. (9-31).
Using g m1 = 500μS and CC = 1.6pF, f0 = 49.74MHz from Eq. (9-21).
We use cp1 = 100fF, cp2 = 200fF and CF = 1pF
Then, g m2 = 625μS using Eq. (9-32).
Next, we find g mc = 3.86mS and C3 = 1.372pF using Eqs. (9-13) and (9-33).
Subsequently, we find g m3 = 4.1mS using Eq. (9-34).
We choose R D = 20kΩ and CD = 1pF so that the requirements in Eq. (9-12) are met.
Using ro1 = 200kΩ and ro2 = 160kΩ, the DC gain is found to be A0 = 410,000 ≈
112.26dB from Eq. (9-20).
Now, we can find a more accurate phase margin figure using (9-35):
ϕm = 1800 + 26.570 + 7.170 − 0.90 − 900 − 20.560 − 9.460 = 92.820 .
126

10 Cascode transistor transconductance g mc 3.86 mS
11 Compensation capacitor CC 1.6 pF
12 Feedforward capacitor CF 1 pF
13 Second stage bandwidth limiting resistance RD 20 kΩ
14 Second stage bandwidth limiting capacitance CD 1 pF

3 First zero fz1 99.48 MHz
5 Fourth pole fp4 298.44 MHz
6 Second zero fz2 394.94 MHz
7 Third zero fz3 3.17 (RHP) GHz

127
with those calculated in previous sub-section and the specifications in Tab. 9-2.

128
Fig 9.4. Unity feedback factor loop-gain magnitude response for the amplifier.
Fig 9.5. Unity feedback factor loop-gain phase response for the amplifier.
129
Tab. 9-7. Data listing for loop-gain response plots in Figs. 9.4 and 9.5.
130
amplifying stage. The amplifiers in Chapters 6 to 8 behave similarly.
Examining Eq. (9-13) with the help of Eq. (9-4) we can check that (cp1 + cp2 ): C3 in Eq. (9-
34) is a small ratio for large values of CL . Therefore, this amplifier can be designed to drive
large values of CL without needing large values of g m3 . On the other hand, when CL is small,
then Eq. (9-13) shows C3 is small too. In such a case, Eqs. (9-33) and (9-34) show that small
values of g m3 and g mc must be used. However, usage of small g m3 values pose more
problems than that of small g mc values since the former causes the DC gain to drop.
However, Eqs. (8-30) and (8-31) also show that by choosing PZL and circuit parameters
appropriately, the abovementioned problem with small CL values can be overcome to some
extent. In conclusion, this amplifier behaves more like the one in Chapters 5 with capacitive
loads but without the issue of multiple gain-crossovers mentioned in Section 5.5.
Eqs. (5-36), (6-32), (7-29), (8-32) and (9-31) show that like amplifiers in Chapters 5 and 7
and unlike amplifiers in Chapters 6 and 8, high enough δp23 values are difficult to obtain for
this amplifier. Consequently, the loop-gain magnitude and phase plots are not as smooth as
those for the amplifiers in Chapters 4, 6 and 8. Large g mc values are needed but as mentioned
in Section 5.5, the problem can be overcome using the technique described in [R1-13].
Tab. 8-6 shows that the evaluated fc value deviates significantly from the calculated f0 one,
since both fz1 and fp23 are located close to f0 with fz1 being closer, as shown in Tab. 9-4. A
relatively small δp23 value also is a contributing factor. Approximation errors involved in
finding high frequency poles/zeros may have contributed too, judging by the fact that the
abovementioned deviation is substantially large.
The first four rows of Tab. A17-3 show that this amplifier consumes the second largest area
but the second lowest power among all the three-stage amplifiers discussed so far.
131
Chapter 10 Three-Stage Amplifier Miller CS
CHAPTER 10
Three-Stage Amplifier with Centre-Stage Miller Compensation
By the turn of the twenty-first century, reduction in DC gain for two-stage amplifiers became
noticeable as the gain per stage due to technology scaling eventually came down markedly.
Researchers developed several methods for compensating a three-stage amplifier [R1-4-
8,10,12,14,15] over time. We studied some of those in Chapters 6 to 9. However, engineers in
the industry were reluctant to deviate too much from the trusted two-stage designs discussed
in Chapters 4 and 5. They wanted a simple solution to the three-stage amplifier compensation
problem.
In this chapter we shall be discussing a three-stage amplifier design that simply adds an extra
inverting stage at the output of a two-stage Miller compensated amplifier discussed in
Chapter 4. This design was probably in use by 2015 in the industry but has remained
relatively unknown. As far as it is known, no paper on this amplifier is available in
international journals or conference proceedings. However, the same appears embedded in an
application published as a 2016 industry co-supervised student dissertation [R2-13].
132
Circuit diagram

Block diagram
Fig. 10-2. Block diagram for the amplifier
133
We refer to Figs. 10-1, 10-2 and Tab. 10-1. It can be observed that Fig. 10-2 differs from Fig.
4-2 essentially by the addition of an inverting stage comprising of transistors MN4 and MP5
and represented by the block marked g m3 where g m3 is the transconductance of MN4. In
addition to this, the terminals named INM and INP are interchanged.
shown below:
Fig. 10-3. Simplified small-signal equivalent circuit for the amplifier
Since this amplifier simply adds a third stage to the amplifier in Chapter 4, we may borrow
useful results from that chapter and make necessary changes and additions. It can be noted
that elements R L and CL and node OUT in Fig. 4.3 are ro2 and cp2 and N2 respectively in Fig.
10-3. We may now obtain the transfer function for the first two stages in Fig. 10-3 applying
these changes to Eq. (4-7) and approximating the result using Eq. (4-3) to arrive at:
1
V2 (s) gm1 gm2 ro1 ro2 [sCc (RC − )+1]
̃ v1,2 (s) =
A = cp1 cp2
gm2
(10-1)
Vi (s) s3 cp1 cp2 CC ro1 ro2 RC + s2 (cp1 +cp2 + )CC ro1 ro2 + sCc gm2 ro1 ro2 +1
CC
Applying Laplace transforms and KCL at node OUT in Fig. 10-3:
g m3 V2 + (GL + sCL )Vo = 0 where GL is given by Eq. (4-1).
We may obtain the transfer function of the third stage from the above and Eq. (4-1) as:
V (s) −gm3 −g R
Av3 (s) = Vo(s) = G = sC m3 L
(10-2)
2 L +sCL R +1
L L
Using Eqs. (10-1) in (10-2) we can find the overall transfer function of the amplifier as:
̃ v1,2 Av3 = Vo (s) , whence we have:

̃ v (s) = A
A V (s) i
134
1
−gm1 gm2 gm3 r01 ro2 RL [sCC (RC − )+1]
̃ v (s) =
A cp1 cp2
gm2
(10-3)
(sCL RL +1)[s3 cp1 cp2 CC r01 ro2 RC + s2 (cp1 +cp2 + )CC ro1 ro2 + sCc gm2 ro1 ro2 +1]
CC
Factorization
Factorisation the cubic polynomial in the denominator of Eq. (10-3) using Eq. (2-40):
−gm1 gm2 gm3 ro1 ro2 RL (sCC RZ +1)
̃ v (s) =
A cp1 cp2 (10-4)
cp1 cp2 RC cp1 +cp2 +
CC
(sCC gm2 r01 ro2 +1)(sCL RL +1)[s2 +s + 1]
gm2 gm2
1 gm2 RC −1
where, RZ = RC − g = (10-5)
m2 gm2
Poles and Zeros

−A0 (sτZ +1)
̃ v (s) =
A 2 τ2 +2sδ (10-6)
(sτ p1 +1)(sτp2 +1)(s p34 p34 τp34 +1)
1 1
ωp1 = τ =g (10-7)
p1 m2 ro1 ro2 CC

1 1
ωp2 = τ =C (10-8)
p2 L RL
Using Eq. (2-19) the natural frequency and damping factor of the third and fourth poles are
given by:
gm2
ωp34 = √c (10-9)
p1 cp2 RC
1 cp2 cp1 √cp1 cp2

δp34 = 2√g [√c + √c + ] (10-10)
m2 RC p1 p2 CC

1 1
ωz = τ = C (10-11)
z c RZ
DC gain and unity-gain frequency
135
A0 = g m1 g m2 g m3 ro1 ro2 R L (10-12)
We decide to use phase-lead compensation with ωp1 , ωp2 and ωz below the unity-gain
frequency ω0 . Therefore, using Eqs. (2-66), (10-7), (10-8), (10-11) and (10-12) we find:
gm1 gm3 RZ
ω0 = (10-13)
CL
We do not define any PZL parameter for ωp1 and ωp2 noting those to be low-frequency far-
away poles. However, we can express those in terms of ω0 combining Eqs. (10-7) and (10-8)
with Eqs. (10-12) and (10-13) such as:
ω A 0 C C RZ
ωp1 = A 0 where A01 = (10-14)
01 C L RL
ω A 0 RZ
ωp2 = A 0 where A02 = g (10-15)
02 m2 ro1 ro2
ωp34 = σω0 (10-16)
ωz = μωp2 = σμω0 (10-17)
Circuit Parameters in terms of PZL parameters
Combining Eqs. (10-9), (10-11), (10-16) and (10-17) we arrive at the quadratic equation:
√cp1 cp2
g m2 R C − √g m2 R C − 1 = 0 (10-18)
μCC
Using Eq, (2-14) the only possible solution for Eq. (10-18) is given by:
κ√cp1 cp2 4μ2 C2C

√g m2 R C = 2μCC
where, κ = 1 + √1 + c (10-19)
p1 cp2
1 C
RZ = √CL (10-20)
√σμgm1 gm3 C
Using (10-20) in (10-13):
g
m1 gm3
ω0 = √ σμC (10-21)
L CC
Combining Eqs. (10-5) and (10-20) and using Eq. (10-19) in the result:
136
gm2 κ2 cp1 cp2 σμCC

=( − 1) √ (10-22)
√gm1 gm3 4μ2 C2C CL
Using (10-19) in (10-10):
μ C C
δp34 = κ (1 + c C + c C ) (10-23)
p1 p2
2ω0 δp34 τp34

ϕm = 1800 + tan−1 (ω0 τz ) − tan−1 (ω0 τp1 ) − tan−1 (ω0 τp2 ) − tan−1 ( )
1−ω20 τ2p34
Substituting (10-14) to (10-17) in above we arrive at:

1 2σ
ϕm = 1800 + tan−1 (σμ) − tan−1 (A01 ) − tan−1 (A02 ) − tan−1 [(σ2−1) δp34 ] (10-24)
The table below lists the target performance parameters of the amplifier:


1
We decide on σ = 6 and μ = 24 , locating ωp34 above and ωz below ω0 in frequency with
1
σμ = 4. Using these values of σ and μ in Eq. (10-24) and assuming A01 , A02 to be large
̃ m = 65.530 .
numbers, the estimated phase margin is ϕ
We use cp1 = 100fF and cp2 = 200fF and Cc = 2.2pF.
Then, κ = 2.637 using (10-19) and δp34 = 0.537 using (10-23).
From Eq. (10-21) we see that we must have √g m1 g m3 = 1.275mS for f0 = 49.96MHz.
We decide on g m1 = 500μS and g m3 = 3.25mS to meet the above requirement.
137
Then, g m2 = 542μS using Eq. (10-22), R C = 7.633kΩ using Eq. (10-19) and R Z = 5.788kΩ
using Eq. (10-5).
Using ro1 = 200kΩ, ro2 = 200kΩ we find A0 = 352,300 ≈ 110.94dB, A01 = 14,953.49
and A02 = 94.06 respectively from Eqs. (10-12), (10-14) and (10-15).
ϕm = 1800 + 75.960 − 900 − 89.390 − 10.430 = 66.140 .
Tab. 10.3. Design values for circuit parameters.

10 Compensation resistance RC 7.633 kΩ

2 Second pole fp2 531.15 kHz
3 Zero fz 12.49 MHz
5 Third/fourth pole fp34 (δp34 ) 299.76 (0.537) MHz (−)

Eq. (10-3). Appendix 10 lists all necessary formulae. The plots, using parameter values in
Tab. 10-3, are shown in Figs. 10-4 and 10-5. Performance parameters for the amplifier may
138
be read off from the plots or from the plot data in Tab. 10-7. The table below compares these
figures with those calculated in the previous sub-section and the specifications in Tab. 10-2.

5 Gain margin Gm − 17.5 > 10 dB
139
Fig. 10-4. Unity feedback factor loop-gain magnitude response for the amplifier
Fig. 10-5. Unity feedback factor loop-gain phase response for the amplifier
140
141
amplifying stage. The amplifiers in Chapters 6 to 9 behave similarly.
Eq. (10-21) shows ω0 , for this amplifier, unlike the amplifiers in Chapters 4 to 9, depends on
CL in addition to CC . This behaviour is caused by the usage of phase-lead compensation
instead of dominant pole compensation. It is also clear from this equation and Eq. (10-17)
that large CL CC values will be needed to locate ωz far below ω0 . However, CC cannot be too
large to optimise cell area and to comply with the restriction in Eq. (10-22) and, therefore, CL
needs to be large. At the same time, both Eqs. (10-21) and (10-22) show the g m1 g m3
requirement for this amplifier is directly proportional to CL . This means the product needs to
be small for small CL values and that will cause loss in DC gain. In summary, this amplifier is
easily designed for large CL values. However, it should also be possible to cater for smaller
CL values by choosing PZL and circuit parameters appropriately.
This amplifier is surprisingly efficient in terms of power and area consumption. It has the best
cell statistics among all three-stage amplifiers we have studied so far, and this will be evident
from the first five rows of Tab. A17-3.
142
Chapter 11 Two-Stage Amplifier Miller, Active FF
CHAPTER 11
Two-Stage Miller Compensated Amplifier
with Active Feedforward
We came across the usage of “nulling resistor(s)” in series with the Miller compensation
capacitor(s) in Chapters 4 and 6. The objective was to eliminate the right-half s-plane zero(s)
or to re-locate it(those) to the left-half s-plane so that better phase margins could be obtained.
A 1997 publication [R1-5] provided an alternative solution to the above problem. It proposed
replacing the “nulling resistor(s)” with active feedforward circuit(s) that could serve the same
purpose mentioned above. Named by the authors “Nested Gm-C Compensation,” the greatest
advantage of this technique is in the ease of generalization while building multistage
amplifiers.
In this chapter we shall be discussing this compensation technique when applied to a two-
stage amplifier. Three-stage and four-stage amplifiers using one and two levels of nesting of
a non-inverting input only version of this two-stage amplifier (referred to as “basic module”
in [R1-5]) will be discussed in the next two chapters.
At the time of publication of this book, this two-stage amplifier has rarely been used in
practice, probably because the amplifier in Chapter 4 is so well-known.
143
Circuit Diagram

7 Feedforward transconductance (MP1, MN1, MN3, MN4, MN5) g mf1
8 Feedforward transconductance ratio (g mf1 : g m1 ) k1
Block diagram
144
We refer to Figs 11.1 and 11.2 and Table 11.1. Transistors MP1, MP2, MP3, MN1 and MN2
constitute the first stage represented by the block marked g m1 where g m1 is the
transconductance of either MP1 or MP2. Transistors MN6 and MP5 constitute the second stage
represented by the block marked g m2 where g m2 is the transconductance of MN6. The
feedforward path with transconductance g mf1 is provided through transistors MP1, MN1, MN3,
MN4 and MN5 and is represented by the block marked g mf1 where g mf1 is a function of the
transconductances of the constituent transistors given by:
g g
g mf1 = k1 g m1 where k1 = 2gmN3 gmN5 (11-1)
mN1 mN4
shown below:
simplified in Fig. 11-3 as per discussions in Section 3.5. Any parasitic capacitance associated
with g mf1 has been neglected too.

1 1
g o1 = r , GL = R (11-2)
o1 L
g m1 , g m2 ≫ g o1 , GL ; cp1 ≪ CC , CL and k1 < 10 (11-3)
(g o1 + scp1 + sCC )V1 − sCC Vo = g m1 Vi (11-4)
(g m2 − sCC )V1 + ( GL + sCL + sCC )Vo = −g mf1 Vi (11-5)
We now define:
145
C1 = cp1 + CC , CT = CL + CC (11-6)
Eqs. (11-4) and (11-5) can be written in vector-matrix form using (11-1) and (11-6) as:
g o1 + sC1 −sCC V g V
[ ] [ 1 ] = [ m1 i ] (11-7)
g m2 − sCC GL + sCT Vo −k1 g m1 Vi

g +sC1 gm1 Vi
| o1 |
gm2 −sCC −k1 gm1 Vi
Vo = go1 +sC1 −sCC
| |
gm2 −sCC GL +sCT

−k1 gm1 Vi (go1 +sC1 )−gm1 Vi (gm2 −sCC )
Vo = g +sC1 −sCC
| o1 |
gm2 −sCC GL +sCT

Vo (s) −k1 gm1 (go1 +sC1 )−gm1 (gm2 −sCC )
Av (s) = = g +sC1 −sCC
Vi (s) | o1 |
gm2 −sCC GL +sCT
columns and using Eq. (11-6) we arrive at:
Vo (s) −k1 gm1 (go1 +sC1 )−gm1 (gm2 −sCC )
Av (s) = = go1 +scp1 −sCC
Vi (s) | |
gm2 +GL +sCL GL +sCT
Rearranging the numerator and factoring out g o1 from the first column and GL from the
second column of the denominator determinant we arrive at:
s(CC gm1 −k1 C1 gm1 )− gm1 gm2 − k1 gm1 go1
Av (s) = cp1 C
1+s −s C
go1 GL
go1 GL |g |
m2 + GL +s CL C
1+s T
go1 go1 go1 GL
Approximating the numerator using Eq. (11-3):

s(CC gm1 −k1 C1 gm1 )− gm1 gm2
̃ v (s) =
A cp1 C
1+s −s C
go1 GL
go1 GL |g |
m2 + GL +s CL C
1+s T
go1 go1 go1 GL
Rearranging the numerator and replacing the conductances using Eq. (11-2):
k C −C
−gm1 gm2 ro1 RL (s 1 1 C + 1)
̃ v (s) =
A 1+scp1 ro1
gm2
−sCC RL
| r |
gm2 ro1 + 01 +sCL ro1 1+sCT RL
RL
146
Finally, expanding the denominator determinant and using (11-6), we arrive at the transfer
function in its final form as:
k C −C
−gm1 gm2 ro1 RL (s 1 1 C + 1)
̃ v (s) = 2
A
gm2
(11-8)
s (c p1 CT +CC CL )ro1 RL + s(CC gm2 ro1 RL +CT RL +C1 ro1 ) + 1
Factorization
To find the poles and zeros of Eq. (11-8) we need to factorise the denominator and for that
purpose we approximate it using Eq. (11-3) to obtain:
k C −C
−gm1 gm2 ro1 RL (s 1 1 C + 1)
̃v = 2
A
gm2
(11-9)
s (c p1 CT +CC CL )ro1 RL + sCC gm2 ro1 RL + 1
Factorising the denominator of (11-9) using Eq. (2-40):

k C −C
−gm1 gm2 ro1 RL (s 1 1 C + 1)
̃v =
A
gm2
cp1 CT +CC CL (11-10)
(sCC gm2 ro1 RL + 1)[s + 1]
CC gm2
Poles and Zeros
̃ v = −A0(sτz+1)
A (11-11)
(sτ p1 +1)(sτp2 +1)
1 1
ωp1 = τ =C (11-12)
p1 C gm2 ro1 RL
And the second pole is given by:

1 CC gm2 gm2
ωp2 = τ =c = (11-13)
p2 p1 CT +CC CL Ca
where, using Eq. (11-6):

C
Ca = CL + cp1 (1 + CL ) (11-14)
C

1 gm2
ωz = τ = k (11-15)
z 1 C1 −CC
147
A0 = g m1 g m2 ro1 R L (11-16)
We decide ωp1 to be the dominant pole. Then, using Eqs. (2-63), (11-12) and (11-16) the
unity-gain frequency is given by:
gm1
ω0 = (11-17)
CC
Defining PZL parameters
However, it can be expressed in terms of ω0 re-writing Eq. (2-63) as:
ω0
ωp1 = (11-18)
A0
We define PZL parameters σ and λ for ωp2 and ωz such that:
ωp2 = σω0 (11-19)
ωz = λω0 (11-20)
Using Eqs. (11-13) and (11-17) in Eq. (11-19):

gm2 σCa
= (11-21)
gm1 CC

CC g C
k1 = + gm2 (λCC ) (11-22)
C1 m1 1
ϕm = 1800 + tan−1(ω0 τz ) − tan−1 (ω0 τp1 ) − tan−1(ω0 τp2 )
Using (11-19) and (11-20) in the above we arrive at:

1 1
ϕm = 1800 + tan−1 (λ) − tan−1(A0 ) − tan−1 (σ) (11-23)
The table below lists the target performance parameters of the amplifier:
148

We decide on σ = 2.286 and λ = 10 locating ωz well ahead of ωp2 in frequency. Using

these values of σ and λ in Eq. (11-23) and assuming A0 to be a large number, the estimated
̃ m = 72.080 .
phase margin is ϕ
We use cp1 = 200fF.
Then, Ca = 7pF from Eq. (11-14) and C1 = 1.8pF from Eq. (11-6).
Subsequently, we find g m2 = 5mS from Eq. (11-21).
Next, we find k1 = 1.778 from Eq. (11-22) and g mf1 = 889μS from Eq. (11-1).
Using ro1 = 200kΩ, we find A0 = 5000 ≈ 73.98dB from Eq. (11-16).
ϕm = 1800 + 5.710 − 900 − 23.630 = 72.080 .

7 Feedforward transconductance g mf1 889 μS
8 Feedforward transconductance ratio k1 1.778 −
149


Tab. 11-3 are shown in Figs. 11-4 and 11-5. Performance parameters for the amplifier may be
read off from the plots or from the plot data in Tab. 11-7. The table below compares these

150
151
152
A study of Eqs. (4-10), (4-23), (11-14) and (11-21) suggests the performances of this
amplifier with various R L and CL values are on par with those of the amplifier in Chapter 4.
However, there are differences and some of those are highlighted below.
Eq. (11-10) shows this amplifier has a single pole beyond ω0 while Eq. (4-9) shows the one
in Chapter 4 has two such poles. That implies, using g mf1 instead of R C one can re-locate ωz
without incurring any additional pole. However, Eqs (11-1), (11-20), (11-22) and (11-23)
show locating ωz at lower frequencies to achieve higher phase margin figures requires large
values of g mf1 to be realized, increasing area/power consumption in turn.
Comparing the first and fourth rows of Tab. A17-2, we see that this amplifier is slightly
worse off than the amplifier in Chapter 4 in terms of both area and power consumption.
153
Chapter 12 Three-Stage Amplifier Nested Miller, Active FF
CHAPTER 12
Three-Stage Nested Miller Compensated Amplifier
amplifiers.
In this chapter we shall be discussing this compensation technique when applied to a three-
stage amplifier using one level of nesting of the “basic module” as discussed in Section 11.1
[R1-11].
154
Circuit Diagram

1 First stage transconductance (MP1, MP2) g m1
10 First feedforward transconductance (MP1, MN1, MN3, MN4, MN5) g mf1
11 First feedforward transconductance ratio (g mf1 : g m1 ) k1
12 Second feedforward transconductance (MN7) g mf2
13 Second feedforward transconductance ratio (g mf2 : g m2 ) k2
Block diagram
155
Referring to Fig. 12.1, Fig. 12.2 and Table 12.1, transistors MP1, MP2, MP3, MN1 and MN2
transconductance of either MP1 or MP2. Transistors MN6, MN8, MP5 and MP6 constitute the
MN6. Transistors MN9 and MP7 make up the third stage represented by the block marked g m3
where g m3 is the transconductance of MP7. The first feedforward path with transconductance
g mf1 is provided through transistors MP1, MN1, MN3, MP4, MN4 and MN5 and is represented by
the block marked g mf1 . The second feedforward path with transconductance g mf2 is provided
through MN7 and is represented by the block marked g mf2 .
g g g
g mf1 = k1 g m1 where k1 = 2gmN3 gmN5 and g mf2 = k 2 g m2 where k 2 = gmN7 (12-1)
mN1 mN4 mN6
shown below:

1 1 1
g o1 = , g o2 = , GL = (12-2)
ro1 ro2 RL
g m1 , g m2 , g m3 ≫ g o1 , g o2 , GL ; cp1 , cp2 ≪ CC , CD , CL and k1 , k 2 < 10 (12-3)
(g o1 + scp1 + sCC )V1 − sCC Vo = g m1 Vi (12-4)
−g m2 V1 + (g o2 + scp2 + sCD )V2 − sCD Vo = 0 (12-5)

156
(g mf2 − sCC )V1 + (g m3 − sCD )V2 + (GL + sCL + sCC + sCD )Vo = −g mf1 Vi (12-6)
We now define:
C1 = cp1 + CC , C2 = cp2 + CD , CT = CL + CC + CD (12-7)
Eqs. (12-4) to (12-6) can be written in vector-matrix form using Eqs. (12-1) and (12-7) as:
g o1 + sC1 0 −sCC V1 g m1 Vi
[ −g m2 g o2 + sC2 −sCD ] [V2 ] = [ 0 ] (12-8)
k 2 g m2 − sCC g m3 − sCD GL + sCT Vo −k1 g m1 Vi
Using Cramer’s rule to solve for Vo from Eq. (12-8):

go1 +sC1 0 gm1 Vi
| −gm2 go2 +sC2 0 |
k2 gm2 −sCC gm3 −sCD −k1 gm1 Vi
Vo = go1 +sC1 0 −sCC
| −gm2 go2 +sC2 −sCD |
k2 gm2 −sCC gm3 −sCD GL +sCT
−gm2 go2 +sC2 g +sC1 0
gm1 Vi | |−k1 gm1 Vi | o1 |
k2 gm2 −sCC gm3 −sCD −gm2 go2 +sC2
Vo = go1 +sC1 0 −sCC
Whence we find the transfer function as:

−gm2 go2 +sC2 g +sC1 0
Vo (s) gm1 | |−k1 gm1 | o1 |
k2 gm2 −sCC gm3 −sCD −gm2 go2 +sC2
Av (s) = = go1 +sC1 0 −sCC
Vi (s)
We replace the second column of both the numerator determinants by the sum of the
respective first and second columns. At the same time, we replace the third column of the
denominator determinant by the sum of its first, second and third columns to arrive at:
−gm2 −gm2 +go2 +sC2 g +sC1 go1 +sC1
gm1 | |−k1 gm1 | o1 |
k2 gm2 −sCC k2 gm2 −sCC +gm3 −sCD −gm2 −gm2 +go2 +sC2
Av (s) = go1 +sC1 0 −sCC +go1 +sC1
| −gm2 go2 +sC2 −sCD +go2 +sC2 −gm2 |
k2 gm2 −sCC gm3 −sCD GL +sCT +gm3 −sCD +k2 gm2 −sCC
Using Eqs. (12-3) and (12-7) the transfer function approximates and simplifies to:
−gm2 −gm2 +sC2 g +sC1 go1 +sC1
gm1 | |−k1 gm1 | o1 |
k2 gm2 −sCC k2 gm2 −sCC +gm3 −sCD −gm2 −gm2 +sC2
̃ v (s) =
A go1 +sC1 0 go1 +scp1
| −gm2 go2 +sC2 go2 +scp2 −gm2 |
k2 gm2 −sCC gm3 −sCD k2 gm2 +gm3 +GL +sCL
Expanding the numerator determinants and re-arranging:
157
2 (C
̃ v (s) = gm1 [s C C2 −k1 C1 C2 )+s(CD gm2 −k2 C2 gm2 +k1 C2 go1 )−gm2 gm3 ]
A go1 +sC1 0 go1 +scp1
| −gm2 go2 +sC2 scp2 −gm2 |
k2 gm2 −sCC gm3 −sCD GL +sCL +gm3 +k2 gm2
Using Eq. (12-3) for another round of approximations the numerator simplifies to:
2
̃ v (s) = gm1 [sg (C+sC
A C C2 −k1 C1 C2 )+s(CD gm2 −k2 C2 gm2 )−gm2 gm3 ]
0 go1 +scp1
o1 1
| −gm2 go2 +sC2 go2 +scp2 −gm2 |
k2 gm2 −sCC gm3 −sCD GL +sCL +gm3 +k2 gm2
Now we can eliminate (remove to infinity) one of the zeros by choosing:

CC
k1 = (12-9)
C1
We use Eq. (12-9) to simplify the numerator. Then, we factor out g o1 , g o2 and GL from the
first, second and third columns respectively of the denominator determinant to arrive at:
k C −C
−gm1 gm2 gm3 (s 2 2 D +1)
gm3
̃ v (s) =
A C go1 cp1
1+s 1 0 +s
go1 GL GL
| g C go2 cp2 gm2 |
go1 go2 GL − m2 1+s 2 +s −
go1 go2 GL GL GL
| |
gm2 C gm3 C CL gm2 gm3
k2 −s C −s D 1+s +k2 +
go1 go1 go2 go2 GL GL GL
Using Eq. (12-2) to replace the conductances:

k C −C
−gm1 gm2 gm3 ro1 ro2 RL (s 2 2 D +1)
gm3
̃ v (s) =
A RL
1+sC1 ro1 0 +scp1 RL
ro1
| RL |
| −gm2 ro1 1+sC2 ro2 +scp2 RL −gm2 RL |
ro2
k2 gm2 ro1 −sCC ro1 gm3 ro2 −sCD ro2 1+sCL RL +k2 gm2 RL +gm3 RL
We fully expand the denominator determinant and simplify using Eqs. (12-7), (12-3) and re-
arrange to arrive at:
k C −C
−gm1 gm2 gm3 ro1 ro2 RL (s 2 2 D +1)
gm3
̃ v (s) =
A s3 (C1 C2 CL + cp1 C2 CC +cp2 C1 CD )ro1 ro2 RL
+s2 [(C1 C2 + C1 CD gm3 RL )ro1 ro2 +{cp2 CD +C2 (CL +CC )}ro2 RL +{cp1 CC +C1 (CL +CD )}ro1 RL ]
+s[CC gm2 gm3 ro1 ro2 RL +(C1 +k2 CC gm2 RL )ro1 +(C2 +CD gm3 RL )ro2 +CT RL ]+1
g
provided k 2 ≪ 1 + gm3 (12-10)
m2
For the next step, however, we need to further approximate Eq. (12-10) using Eq. (12-3) to
select the dominant terms in the coefficient of each power of ‘s’ to arrive at the transfer
k C −C
−gm1 gm2 gm3 ro1 ro2 RL (s 2 2 D +1)
gm3
̃ v (s) = 3
A 2
(12-11)
s C 1 C2 CL ro1 ro2 RL +s C1 CD gm3 ro1 ro2 RL +sCC gm2 gm3 ro1 ro2 RL +1
158
Factorization

k C −C
−gm1 gm2 gm3 ro1 ro2 RL (s 2 2 D +1)
gm3
̃ v (s) =
A C2 CL CD (12-12)
(sCC gm2 gm3 ro1 ro2 RL +1)(s2 +s +1)
k1 gm2 gm3 k1gm2
Poles and Zeros

−A0 (sτz +1)
̃ v (s) =
A 2 2
(12-13)
(sτ p1 +1)(s τp23 +2sδp23 τp23 +1)
1 1
ωp1 = τ =C (12-14)
p1 C gm2 gm3 r01 r02 RL
Using Eq. (2-19), the natural frequency and damping factor of the second and third poles are
given by:
1 k1 gm2 gm3
ωp23 = =√ (12-15)
τp23 C2 CL
CD gm3
δp23 = √k (12-16)
2√C2 CL 1 gm2

1 gm3
ωz = τ = k (12-17)
z 2 C2 −CD
A0 = g m1 g m2 g m3 ro1 ro2 R L (12-18)
We decide ωp1 to be the dominant pole. Then, using Eqs, (2-63), (12-14) and (12-18) the
gm1
ω0 = (12-19)
CC
159
ω0
ωp1 = (12-20)
A0
We define PZL parameters σ and λ for ωp23 and ωz such that:
ωp23 = σω0 (12-21)
ωz = λω0 (12-22)

gm2 gm3 σ2 C2 CL
= (12-23)
g2m1 k1 C2C
Using Eq. (12-23) in Eq. (12-16):

σ C g
δp23 = 2k (CDg m1) (12-24)
1 C m2

CD g C
k2 = + gm3 (λCC ) (12-25)
C2 m1 2
Setting s = jω0 in (12-13) and using Eq. (2-77), the phase margin is given by:
2ω0 δp23 τp23

ϕm = 1800 + tan−1(ω0 τz ) − tan−1 (ω0 τp1 ) − tan−1 ( )
1−ω20 τ2p23
Substituting Eqs. (12-20) to (12-22) in the above:

1 2σ
ϕm = 1800 + tan−1 (λ) − tan−1(A0 ) − tan−1 [(σ2−1) δp23 ] (-)
160

We decide on σ = 2.5 and λ = 10 locating ωz well ahead of ωp23 in frequency. Using these
values of σ and λ in Eq. (12-26) and assuming A0 to be a large number, the estimated phase
̃ m = 68.930 .
margin is ϕ
Next, we use cp1 = 100fF and cp2 = 200fF and CD = 1.6pF.
Then, C1 = 1.7pF and C2 = 1.8pF from Eq. (12-7) and k1 = 0.941 from Eq. (12-9).
We further use g m2 = 1.25mS. Then, we find:
g m3 = 5.6mS from (12-23), δp23 = 0.53 from Eq. (12-24) and k 2 = 1.884 from (12-25).
Then, g mf1 = 471μS and g mf2 = 2.355mS from (12-1).
It may be observed that the condition in (12-10) is satisfied to some extent.
Using ro1 = 200kΩ and ro2 = 50kΩ we find A0 = 350,000 ≈ 110.88dB from (12-18).
ϕm = 1800 + 5.71 − 900 − 26.780 = 68.930 .
161

10 First feedforward transconductance g mf1 471 μS
11 First feedforward transconductance ratio k1 0.941 −
12 Second feedforward transconductance g mf2 2.355 mS
13 Second feedforward transconductance ratio k2 1.884 −
14 Compensation capacitor to first stage CC 1.6 pF
15 Compensation capacitor to second stage CD 1.6 pF

1 First pole fp1 142 Hz


162
163
164
A study of Eqs. (6-21), (6-31), (12-18) and (12-23) suggests the performances of this
amplifier with various R L and CL values are on par with those of the amplifier in Chapter 6.
However, there are differences and some of those are highlighted below.
Eq. (12-12) shows this amplifier has a single pair complex poles beyond ω0 while Eq. (6-11)
shows the one in Chapter 6 has several such poles including one pair of complex poles. That
implies, using g mf1 and g mf2 instead of R C and R D one can eliminate or re-locate zeros
without incurring any additional pole.
Eqs (12-1), (12-22), (12-25) and (12-26) show locating ωz at lower frequencies to achieve
higher phase margin figures requires large values for g mf2 to be realized. Interestingly, this
requirement does not affect the overall area/power consumption much since g mf1 (MN5) and,
most importantly, g mf2 (MN7) re-use part of the bias current of g m3 (MP7) and share area with
the output stage load transistor MN9 as shown in Fig. 12-1. However, it may be evident that
the condition in Eq. (12-10) will be difficult to satisfy and that will affect δp23 in turn.
From the first and sixth rows in Tab. A17-3 we see that this amplifier consumes smaller area
than the amplifier in Chapter 6. The reduction in area is primarily due a smaller value of CD
used, as shown in Tabs. 6-3 and 12-3. However, the advantage in area is at the expense of a
decent δp23 value as can be seen from Tabs. 6-4 and 12-4.
165
Chapter 13 Four-Stage Amplifier Double Nested Miller, Active FF
CHAPTER 13
Four-Stage Double Nested Miller Compensated Amplifier
amplifiers.
In this chapter we shall be discussing this compensation technique when applied to a four-
stage amplifier using two levels of nesting of the “basic module” as discussed in Section
11.1.
166
Circuit Diagram

7 Third stage transconductance (MN9 with MP7 = MP8) g m3
8 Net resistance loading third stage (node N3) ro3
9 Net capacitance loading third stage (node N3) cp3
10 Fourth stage transconductance (MP9) g m4
11 Net resistance loading fourth stage (node OUT) RL
12 Net capacitance loading fourth stage (node OUT) CL
13 First feedforward transconductance (MP1, MN1, MN3, MN4, MN5) g mf1
14 First feedforward transconductance ratio (g mf1 : g m1 ) k1
15 Second feedforward transconductance (MN7) g mf2
16 Second feedforward transconductance ratio (g mf2 : g m2 ) k2
17 Third feedforward transconductance (MN10) g mf3
18 Third feedforward transconductance ratio (g mf3 : g m3 ) k3
21 Compensation capacitance to third stage CE
Block Diagram
Referring to Fig. 13.1, Fig. 13.2 and Tab. 13.1, transistors MP1, MP2, MP3, MN1 and MN2
transconductance of either MP1 or MP2. Transistors MN6, MN8, MP5 and MP6 constitute the
MN6. Transistors MN9, MN11, MP7 and MP8 constitute the third stage represented by the block
167
marked g m3 where g m3 is the transconductance of MN9. Transistors MN12 and MP9 make up
the fourth stage represented by the block marked g m4 where g m4 is the transconductance of
MP9. The first feedforward path with transconductance g mf1 is provided through transistors
MP1, MN1, MN3, MP4, MN4 and MN5 and is represented by the block marked g mf1 . The second
feedforward path with transconductance g mf2 is provided through MN7 and is represented by
the block marked g mf2 . The third feedforward path with transconductance g mf3 is provided
through MN10 and is represented by the block marked g mf3 .

g g g
g mf1 = k1 g m1 where k1 = 2gmN1 gmN5 and g mf2 = k 2 g m2 where k 2 = gmN7
mN3 mN4 mN6
gmN10
and g mf3 = k 3 g m3 where k 3 = (13-1)
gmN9

168
For convenience, we shall consider admittances instead of impedances such as:

1 1 1 1
g o1 = r , g o2 = r , g o3 = r , GL = R (13-2)
o1 o2 o3 L
g m1 , g m2 , g m3 , g m4 ≫ g o1 , g o2 , g o3 , GL ; cp1 , cp2 , cp3 ≪ CC , CD , CE , CL and k1 , k 2 , k 3 < 10
(13-3)
Applying Laplace transforms and KCL to nodes N1, N2, N3 and OUT in Fig. 13-3:
(g 01 + scp1 + sCC )V1 − sCC Vo = g m1 Vi (13-4)
−g m2 V1 + (g o2 + scp2 + sCD )V2 − sCD Vo = 0 (13-5)
−g m3 V2 + (g o3 + scp3 + sCE )V2 − sCE Vo = 0 (13-6)
(g mf2 − sCC )V1 + (g mf3 − sCD )V2 + (g m4 − sCE )V3
+(GL + sCL + sCC + sCD + sCE )Vo = −g mf1 Vi (13-7)
We now define:
C1 = cp1 + CC , C2 = cp2 + CD , C3 = cp3 + CE , CT = CL + CC + CD + CE (13-8)
Eqs. (13-4) to (13-7) can be written in vector-matrix form using Eqs. (13-1) and (13-8) as:
g o1 + sC1 0 0 −sCC V1 g m1 Vi
−g m2 g o2 + sC2 0 −sCD V 0
[ ] [ 2] = [ ] (13-9)
0 −g m3 g o3 + sC3 −sCE V3 0
k 2 g m2 − sCC k 3 g m3 − sCD g m4 − sCE GL + sCT Vo −k1 g m1 Vi
Using Cramer’s rule to solve for Vo from (13-9):

go1 +sC1 0 0 gm1 Vi
−gm2 go2 +sC2 0 0
| |
0 −gm3 go3 +sC3 0
k2 gm2 −sCC k3 gm3 −sCD gm4 −sCE −k1 gm1 Vi
Vo = go1 +sC1 0 0 −sCC
−gm2 go2 +sC2 0 −sCD
| |
0 −gm3 go3 +sC3 −sCE
k2 gm2 −sCC k3 gm3 −sCD gm4 −sCE GL +sCT
Using cofactor expansion of the numerator determinant along its fourth column:
−gm2 go2 +sC2 0 go1 +sC1 0 0
−gm1 Vi | 0 −gm3 go3 +sC3 |−k1 gm1 Vi | −gm2 go2 +sC2 0 |
k2 gm2 −sCC k3 gm3 −sCD gm4 −sCE 0 −gm3 go3 +sC3
Vo = go1 +sC1 0 0 −sCC
| |
169
Whence we find the transfer function as:

−gm2 go2 +sC2 0 go1 +sC1 0 0
−gm1 | 0 −gm3 go3 +sC3 |−k1 gm1 | −gm2 go2 +sC2 0 |
Vo (s) k2 gm2 −sCC k3 gm3 −sCD gm4 −sCE 0 −gm3 go3 +sC3
Av (s) = = go1 +sC1 0 0 −sCC
Vi (s)
| |
We replace the second column of both the numerator determinants by the sum of the
respective first and second columns to arrive at:
−gm2 go2 +sC2 −gm2 0 go1 +sC1 go1 +sC1 0
−gm1 | 0 −gm3 go3 +sC3 |−k1 gm1 | −gm2 go2 +sC2 −gm2 0 |
k2 gm2 −sCC k2 gm2 +k3 gm3 −sCD −sCC gm4 −sCE 0 −gm3 go3 +sC3
Av = go1 +sC1 0 0 −sCC
| |
Using Eqs. (13-3) and (13-8) the transfer function approximates and simplifies to:
−gm2 sC2 −gm2 0 go1 +sC1 go1 +sC1 0
−gm1 | 0 −gm3 go3 +sC3 |−k1 gm1 | −gm2 sC2 −gm2 0 |
k2 gm2 −sCC k2 gm2 +k3 gm3 −sCD −sCC gm4 −sCE 0 −gm3 go3 +sC3
̃ v (s) =
A go1 +sC1 0 0 −sCC
| |
Now, we replace the third column of both the numerator determinants by the sum of the
respective second and third columns. At the same time, we replace the fourth column of the
denominator determinant by the sum of its first, second, third and fourth columns to arrive at:
−gm2 sC2 −gm2 sC2 −gm2
−gm1 | 0 −gm3 go3 +sC3 −gm3 |
k2 gm2 −sCC k2 gm2 +k3 gm3 −sCD −sCC k2 gm2 +k3 gm3 +gm4 −sCE −sCD −sCC
go1 +sC1 go1 +sC1 go1 +sC1
−k1 gm1 | −gm2 sC2 −gm2 sC2 −gm2 |
̃V = 0 −gm3 go3 +sC3 −gm3
A go1 +sC1 0 0 go1 +sC1 −sCC
−gm2 go2 +sC2 0 go2 +sC2 −gm2 −sCD
| |
0 −gm3 go3 +sC3 go3 +sC3 −gm3 −sCE
k2 gm2 −sCC k3 gm3 −sCD gm4 −sCE k2 gm2 +k3 gm3 +gm4 +GL +sCT −sCC −sCD −sCE
Using Eq. (13-3) to further approximate the numerator and Eq. (13-8) to simplify the
denominator:
−gm2 sC2 −gm2 sC2 −gm2
−gm1 | 0 −gm3 sC3 −gm3 |
k2 gm2 −sCC k2 gm2 +k3 gm3 −sCD −sCC k2 gm2 +k3 gm3 +gm4 −sCE −sCD −sCC
go1 +sC1 go1 +sC1 go1 +sC1
−k1 gm1 | −gm2 sC2 −gm2 sC2 −gm2 |
̃ v (s) = 0 −gm3 sC3 −gm3
A go1 +sC1 0 0 go1 +scp1
−gm2 go2 +sC2 0 go2 +scp2 −gm2
|| ||
0 −gm3 go3 +sC3 go3 +scp3 −gm3
k2 gm2 −sCC k3 gm3 −sCD gm4 −sCE k2 gm2 +k3 gm3 +gm4 +GL +sCL
Expanding the numerator determinants and re-arranging:

170
s3 (CC C2 C3 −k1 C1 C2 C3 )+s2 (CD C3 gm2 −k2 C2 C3 gm2 −k1 C2 C3 go1 )

gm1 [ ]
̃ v (s) = +s(CE gm2 gm3 −k3 C3 gm2 gm3 )−gm2 gm3 gm4
|| ||
Using Eq. (13-3) for another round of approximations the numerator simplifies to:
s3 (CC C2 C3 −k1 C1 C2 C3 )+s2 (CD C3 gm2 −k2 C2 C3 gm2 )
gm1 [ ]
̃ v (s) = +s(CE gm2 gm3 −k3 C3 gm2 gm3 )−gm2 gm3 gm4
|| ||
Now we can eliminate (remove to infinity) two of the zeros by choosing:

CC CD
k1 = and k 2 = (13-10)
C1 C2
We use Eq, (13-10) to further simplify the numerator. Then, factor out g o1 , g o2 , g o3 and GL
from the first, second and third columns respectively of the denominator determinant to arrive
at:
k C −C
−gm1 gm2 gm3 gm4 (s 3 3 E +1)
̃ v (s) =
A C
gm4
go1 cp1
1+s 1 0 0 +s
go1 GL GL
| g C go2 cp2 gm2 |
− m2 1+s 2 0 +s −
go1 go2 GL GL GL
go1 go2 go3 GL gm3 C go3 cp3 gm3
0 − 1+s 3 +s −
go2 go3 GL GL GL
| |
g C gm3 C gm4 C CL gm2 g g
k2 m2 −s C k3 −s D −s E 1+s +k2 +k3 m3 + m4
go1 go1 go2 go2 go3 go3 GL GL GL GL
Using (13-2) to replace the conductances:

k C −C
−gm1 gm2 gm3 gm4 ro1 ro2 ro3 RL (s 3 3 E +1)
̃ v (s) =
A
gm4
RL
1+sC1 ro1 0 0 +scp1 RL
ro1
| RL |
−gm2 ro1 1+sC2 ro2 0 +scp2 RL −gm2 RL
ro2
RL
| 0 −gm3 ro2 1+sC3 ro3 +scp3 RL −gm3 RL |
ro3
k2 gm2 ro1 −sCC ro1 k3 gm3 ro2 −sCD ro2 gm4 ro3 −sCE ro3 1+sCL RL +k2 gm2 RL +k3 gm3 RL +gm4 RL
We fully expand the denominator determinant, simplify using Eqs. (13-8) and (13-10) and re-
arrange. The total number of terms in the denominator being prohibitively large (72 in
number), we refrain from presenting the complete transfer function. Instead, we further
approximate it for the next step using (13-3) to select the dominant terms in the coefficient of
each power of ‘s’ and arrive at the transfer function in its final form as:
k C −C
̃ v (s) = 4
A 3C
gm4
2
s C 2 CC CE CL ro1 ro2 ro3 RL +s 1 C2 CE gm4 ro1 ro2 ro3 RL +s C1 CD gm3 gm4 ro1 ro2 ro3 RL
+sCC gm2 gm3 gm4 ro1 ro2 ro3 RL +1
171
g C g
provided k 3 ≪ 1 + gm4 and k 3 ≪ 1 + CDg m4 (13-11)
m3 3 m2
Factorization

k C −C
̃ v (s) =
A C2 CE CL
gm4
C2 CE CD (13-12)
(sCC gm2 gm3 gm4 ro1 ro2 ro3 RL +1)(s3 + s2 +s +1)
gm2 gm3 gm4 k1 gm2 gm3 k1gm2
The cubic polynomial in the denominator of Eq. (13-12) cannot be factorised using any of the
methods described in section 2.2. Therefore, we must leave it unfactorized. Its poles will be
located using PZL parameters as described in Section 2.4.3.
Poles and Zeros

−A0 (sτz +1)
̃ v (s) =
A 2 2
(13-13)
(sτ p1 +1)(sτp2 +1)(s τp34 +2sτp34 δp34 +1)
1 1
ωp1 = τ =C (13-14)
p1 C gm2 gm3 gm4 r01 r02 r03 RL
and the zero is given by:

1 gm4
ωz = τ = k (13-15)
z 3 C3 −CE
A0 = g m1 g m2 g m3 g m4 ro1 ro2 ro3 R L (13-16)
We decide ωp1 to be the dominant pole. Then, using Eqs, (2-63), (13-14) and (13-16) the
gm1
ω0 = (13-17)
CC
We do not define a PZL parameter for locating ωp1 noting that it is a low-frequency far-away
pole. However, it can be expressed in terms of ω0 by re-writing Eq. (2-63) as:
172
ω0
ωp1 = (13-18)
A0
We define PZL parameters σ, μ and λ for ωp2 , ωp34 and ωz such that:
1
ωp2 = τ = σω0 (13-19)
p2
1
ωp34 = τ = μωp2 = σμω0 (13-20)
p34
ωz = λω0 (13-21)
Substituting Eqs. (13-19) and (13-20) into the last two factors in the denominator of Eq. (13-
13) and multiplying those, we arrive at the cubic polynomial:
1 2δp34
1 2δp34 + 1+
3 2 μ μ
s +s +s +1
σ3 μ2 ω30 σ2 μω20 σω0
Equating the above with the cubic polynomial (the second factor) in the denominator of Eq.
(13-12) we find:
1 C2 CE CL
=g (13-22)
σ3 μ2 ω30 m2 gm3 gm4
1
2δp34 + C2 CE
μ
=k (13-23)
σ2 μω20 1 gm2 gm3
2δp34
1+ CD
μ
=k (13-24)
σω0 1 gm2

gm4 C
= σ(2μδp34 + 1) (CL ) (13-25)
gm1 1
gm3 σμ(μ+2δp34 ) CE
= (k ) (13-26)
gm1 2μδp34 +1 2 CC
Combining (13-10) and (13-24):

gm2 σμ CD
= μ+2δ (k ) (13-27)
gm1 p34 1 CC
Combining (13-15), (13-17) and (13-21):

CE g C
k3 = + gm4 (λCC ) (13-28)
C3 m1 3
173
2ω0 δp34 τp34

ϕm = 1800 + tan−1(ω0 τz ) − tan−1 (ω0 τp1 ) − tan−1(ω0 τp2 ) − tan−1 ( )
1−ω20 τ2p34
Substituting Eqs. (13-17), (13-18) and (13-19) in the above:

1 1 2σμ
ϕm = 1800 + tan−1 (λ) − tan−1(A0 ) − tan−1 (σ) − tan−1 [(σ2μ2 −1) δp34 ] (13-29)


7 10
We decide on σ = 2 , μ = and λ = 10, locating ωp34 with σμ = 5 and ωz ahead of ωp2 in
7
frequency. Using these values of σ, μ and λ in Eq. (13-29) and assuming A0 to be a large
̃ m = 68.00.
number, the estimated phase margin is ϕ
We use CD = CE = 1.6pF , cp1 = 100fF, cp2 = 200fF and cp3 = 400fF.
Then, C1 = 1.7pF, C2 = 1.8pF and C3 = 2.0pF from Eq. (13-7) and, thus, k1 = 0.941 and
k 2 = 0.889 from (13-10).
Let us choose δp34 = 0.5. Then, using Eqs. (13-25), (13-26) and (13-27) we find:
g m2 = 1.1mS, g m3 = 2.8mS and g m4 = 15mS.
Using (13-28) we find k 3 = 3.2. Subsequently, using Eq. (13-1) we find:
g mf1 = 471μS, g mf2 = 978μS and g mf3 = 8.96mS.
It may be observed that the condition in Eq. (13-11) is satisfied to some extent.
174
Using ro1 = 200kΩ, ro2 = 40kΩ and ro3 = 20kΩ, we find the DC gain to be:
A0 = 3,696,000 ≈ 131.36dB from Eq. (13-16).
ϕm = 1800 + 5.710 − 900 − 15.950 − 11.770 = 68.00 .

8 Third stage resistive load ro3 20 kΩ
9 Third stage capacitive load cp3 400 fF
10 Fourth stage transconductance g m4 15 mS
11 Fourth stage resistive load RL 1 kΩ
12 Fourth stage capacitive load CL 6 pF
13 First feedforward transconductance g mf1 471 μS
14 First feedforward transconductance ratio k1 0.941 −
15 Second feedforward transconductance g mf2 978 μS
16 Second feedforward transconductance ratio k2 0.889 −
17 Third feedforward transconductance g mf3 8.96 mS
18 Third feedforward transconductance ratio k3 3.2 −
19 Compensation capacitor to first stage CC 1.6 pF
20 Compensation capacitor to second stage CD 1.6 pF
21 Compensation capacitor to second stage CE 1.6 pF
Table 13.4 Design values for frequency parameters

4 Third/fourth pole fp34 (δp34 ) 248.7 (0.5) MHz (−)

175

3 Phase margin ϕm 68 68 > 60 degrees
176
177
178
A study of Eqs. (6-31), (12-23) and (13-25) suggests this amplifier behaves similarly as those
in Chapters 11 and 12 with varying CL values. However, Eqs. (6-21), (12-18) and (13-16)
show that this amplifier can comfortably drive lower R L values compared to the others. In
terms of figures, it can drive R L as small as 1kΩ while maintaining an overall DC gain as
large as 131dB, as can be seen from Tab. 13-6.
For this amplifier, k1 and k 2 were chosen to eliminate two zeros while k 3 was chosen to re-
locate the remaining zero ωz at lower frequencies to achieve better phase margin results.
However, according to Eqs. (13-1), (13-21), (13-28) and (13-29) that requires larger values
for g mf3 to be realized. Like the amplifier in Chapter 12, this requirement does not affect the
overall area/power consumption much since g mf1 (MN5), g mf2 (MN7) and, most importantly,
g mf3 (MN10) re-use part of the bias current of g m4 (MP9) and share area with the output stage
load transistor MN11 as shown in Fig. 13-1. However, it may be evident that the condition in
Eq. (13-11) will be difficult to satisfy and that will affect δp34 in turn.
Comparing Tabs. 12-5 and 13-5 we see that this amplifier consumes more area/power than
the amplifier in Chapter 12. The ability of this amplifier to drive low R L values as mentioned
in the first paragraph of this section justifies the increase.
179
Chapter 14 Two-Stage Amplifier Non-Miller, Active FF
CHAPTER 14
Two-Stage Amplifier with Non-Miller
Active Feedforward Compensation
We dealt with variants of the Miller compensation technique, requiring at least one Miller
capacitor in Chapters 4 to 13. The maximum number of such capacitors being one less than
the number of stages.
In a radical shift from the above idea of compensation, a 2003 publication [R1-8] described a
technique for compensating multistage amplifiers without any Miller capacitor(s). It proposed
insertion of zeros using active feedforward to counter the poles of the amplifier, the number
of zeros being one less than the number of poles or stages. However, the bandwidth of the
individual stages had to be limited for the feedforward path(s) to operate effectively.
Therefore, a total removal of capacitors was not quite possible. Like the amplifiers in
Chapters 11 to 13, this idea too can be easy generalised to build multistage amplifiers.
In this chapter we shall be discussing this compensation technique when applied to a two-
stage amplifier. Three-stage and four-stage amplifiers building on this amplifier will be
discussed in Chapters 15 and 16.
Like the amplifier in Chapter 11, this two-stage amplifier too has rarely been used in practice
till now, thanks to the popularity of the amplifier in Chapter 4.
180
Circuit Diagram

1 First stage transconductance (MP1 or MP2 or MP4 or MP5) g m1
4 Bandwidth limiting capacitance for first stage (node N1) CB1
8 Feedforward transconductance to second stage (MP4, MN3, MN5) g mf2
Block Diagram
Fig. 14.2. Block diagram for the amplifier.
We refer to Figs 14.1 and 14.2 and Table 14.1. Transistors MP1, MP2, MP3, MN1, MN2 and MP4,
MP5, MP6, MN3, MN4 constitute the first stage represented by the block marked g m1 where g m1
is the transconductance of any one of MP1, MP2, MP4 or MP5. Transistors MN6 and MP7
constitute the second stage represented by the block marked g m2 where g m2 is the
181
transconductance of MN6. The feedforward path with transconductance g mf2 is provided

through transistors MP4, MN3 and MN5 and is represented by the block marked g mf2 where
g mf2 is a function of the transconductances of the constituent transistors given by:
g
g mf2 = k 2 g m1 where k 2 = 2gmN5 (14-1)
mN3
simplified in Fig. 14-3 as per discussions in Section 3.5. Parasitic capacitance associated with
g mf2 has been neglected too.

1 1
g o1 = r , GL = R (14-2)
o1 L
We define:
C1 = cp1 + CB1 (14-3)
g m1 , g m2 ≫ g o1 , GL ; cp1 ≪ CB1 , CL and k 2 < 10 (14-4)
Applying Laplace transforms and KCL to nodes N1 and OUT in Fig. 14-3 and using Eqs. (14-
2) and (14-3):
(g o1 + sC1 )V1 = g m1 Vi (14-5)
g m2 V1 + ( GL + sCL )Vo = −g mf2 Vi (14-6)
Eqs. (14-5) and (14-6) can be written in vector-matrix form using Eq. (14-1) as:
g o1 + sC1 0 V g V
[ ] [ 1 ] = [ m1 i ] (14-7)
g m2 GL + sCL Vo −k 2 g m1 Vi
182

g +sC1 gm1 Vi
| o1 |
gm2 −k2 gm1 Vi
Vo = g +sC1 0
| o1 |
gm2 GL +sCL
Expanding the numerator and denominator determinants:

−gm1 gm2 Vi −k2 gm1 go1 Vi −sk2 C1 gm1 Vi
Vo = (g01 +sC1 )( GL +sCL )
Whence we can find the transfer function to be:

Vo (s) −gm1 gm2 −k2 gm1 go1 −sk2 C1 gm1
Av (s) = =
Vi (s) (g01 +sC1 )( GL +sCL )
Approximating the transfer function using Eq. (14-4):
̃ v (s) = −gm1gm2 −sk2C1gm1

A (g +sC )( G +sC )
01 1 L L
Factoring out g o1 and GL in the denominator and rearranging the numerator:

k C
−gm1 gm2 (s 2 1 + 1)
̃ v (s) =
A C
gm2
C
go1 GL (s 1 + 1)(s L + 1)
go1 GL
Replacing the conductances using Eq. (14-2) and rearranging we arrive at the transfer
k C
−gm1 gm2 ro1 RL (s 2 1 +1)
̃ v (s) =
A
gm2
(14-8)
(sC1 ro1 +1)(sCL RL +1)
Writing (14-8) in terms of its poles and zero:

A0 (sτz +1)
̃ v (s) =
A (14-9)
(sτ +1)(sτ +1)
p1 p2
Comparing (14-8) and (14-9) the two poles are given by:
1 1
ωp1 = τ =C (14-10)
p1 1 ro1
and
1 1
ωp2 = τ =C (14-11)
p2 L RL

1 g
ωz = τ = k m2 (14-12)
z C 2 1
183
A0 = g m1 g m2 ro1 R L (14-13)
We decide to use phase-lead compensation with ωp1 , ωp2 and ωz below the unity-gain
frequency ω0 . Therefore, using Eqs. (2-66), (14-1) and (14-10) to (14-13) we find:
k2 gm1 gmf2
ω0 = = (14-14)
CL CL
We do not define any PZL parameter for ωp1 and ωp2 noting those to be low-frequency far-
away poles. However, we can express those in terms of ω0 combining Eqs. (14-1), (14-10)
and (14-11) with Eqs. (14-13) and (10-14) such as:
ω C C
ωp1 = A 0 where A01 = k 2 g m1 ro1 (C1 ) = g mf2 ro1 (C1 ) (14-15)
01 L L
and
ω
ωp2 = A 0 where A02 = k 2 g m1 R L = g mf2 R L (14-16)
02
We define PZL parameter σ for ωz such that:
ωz = σω0 (14-17)
Substituting (14-12) and (14-14) into (14-17) we find:
gm2 k22 σC1

= (14-18)
gm1 CL
ϕm = 1800 + tan−1(ω0 τz ) − tan−1(ω0 τp1 ) − tan−1(ω0 τp2 )

1
ϕm = 1800 + tan−1 (σ) − tan−1(A01 ) − tan−1(A02 ) (14-19)
184

2 Unity gain frequency f0 > 50 MHz

1
We decide on σ = locating ωz below ω0 in frequency. Using this value of σ in Eq. (14-19)
2
̃ m = 63.440 .
and assuming A01 , A02 to be large numbers, the estimated phase margin is ϕ
Using g mf2 = 2mS, so that f0 = 53.05MHz from Eq. (14-14).
Using C1 = 3pf and cp1 = 150fF, CB1 = 2.85pF from Eq. (14-3).
Using k 2 = 4 we find g m1 = 500μS from Eq. (14-1) and g m2 = 2mS from Eq. (14-18).
Using ro1 = 200kΩ, A01 = 200 from Eq. (14-15), A02 = 20 from Eq. (14-16) and A0 =
2000 ≈ 66.02dB from Eq. (14-13).
ϕm = 1800 + 63.440 − 89.710 − 87.130 = 66.600 .

4 Bandwidth limiting capacitance for first stage CB1 2.85 pF
8 Feedforward transconductance g mf2 2 mS
9 Feedforward transconductance ratio k2 4 −
185


14.4.3. Design evaluation

2 Unity gain frequency f0 /fc 53.05 53 > 50 MHz
5 Gain margin Gm − NA − dB
186
187
Tab. A14-7. Data listing for loop-gain response plots in Figs. 14-4 and 14-5.
188
A study of Tabs. 4-3, 4-6, 11-3, 11-6, 14-3 and 14-6 shows that this amplifier has a lower DC
gain compared to those in Chapters 4 and 11 for the same R L value. This happens because of
a relatively low g m2 value for this amplifier. The performances with various CL values are
very different and some of those are highlighted below.
Eqs. (4-18), (11-17) and (14-14) show that ω0 , for this amplifier, is inversely proportional to
CL instead of CC for the others. This means it is not suitable for variable load applications.
However, comparing Figs. 4-4, 11-4 and 14-4 we see, for nearly equal unity-gain bandwidth,
this amplifier has higher 3-dB bandwidth (265kHz against 10kHz) and larger gain at 1MHz
(54dB against 34dB) despite its DC gain being lower (66dB against 74dB). This
characteristic is typical of non-Miller phase-lead compensated amplifiers because none of the
poles are pushed back to very low frequencies by Miller multiplication of capacitor(s).
Therefore, this compensation is better for high-frequency designs.
From Tab. A17-2 we can see that this amplifier consumes the lowest power but largest area
among all the two-stage amplifiers. The size of CB1 in this amplifier is largely responsible for
the increase in area.
189
Chapter 15 Three-Stage Amplifier Non-Miller, Active FF
CHAPTER 15
Three-Stage Amplifier with Non-Miller
In Section 14.5 we noted that the bandwidth limiting capacitor CB1 is larger than a normal
Miller capacitor used in Chapter 4 or 11 thereby increasing area consumption. In a 2006
publication [R1-10], this problem was overcome using Miller multiplication of small
capacitors to realize bandwidth limiting capacitors.
In this chapter we shall be discussing this compensation technique when applied to a three-
stage amplifier. However, we shall stick to the non-Miller version of the compensation.
190
Circuit Diagram


4 Bandwidth limiting capacitor for first stage (node N1) CB1
7 Parasitic capacitance loading second stage (node N2) cp2
8 Bandwidth limiting capacitor for second stage (node N2) CB2
14 Feedforward transconductance to third stage (M P5, MN4, MN7) g mf3
Block Diagram
191
Referring to Figs. 15-1 and 15-2 and Table 15-1, transistors MP1, MP2, MP3, MN1, MN2 and
MP4, MP5, MP6, MN3, MN4 constitute the first stage represented by the block marked g m1
where g m1 is the transconductance of any one of MP1, MP2, MP4 or MP5. Transistors MN5 and
MP7 constitute the second stage represented by the block marked g m2 where g m2 is the
transconductance of MN5. Transistors MP8 and MN7 constitute the third stage represented by
the block marked g m3 where g m3 is the transconductance of MP8. The feedforward path with
transconductance g mf2 is provided through transistors MP4, MN3 and MN6 and is represented
by the block marked g mf2 . The feedforward path with transconductance g mf3 is provided
through transistors MP5, MN4 and MN7 and is represented by the block marked g mf3 where
g mf2 and g mf3 are functions of the transconductances of the constituent transistors given by:
gmN6 gmN7
g mf2 = k 2 g m1 where k 2 = and g mf3 = k 3 g m1 where k 3 = (15-1)
2gmN3 2gmN4
simplified in Fig. 15-3 as per discussions in Section 3.5. Parasitic capacitances associated
with g mf2 and g mf3 have been neglected too.

1 1 1
g o1 = r , g o2 = r , GL = R (15-2)
o1 o1 L
We define:
C1 = cp1 + CB1 and C2 = cp2 + CB2 (15-3)
g m1 , g m2 , g m3 ≫ g o1 , g o2 , GL ; cp2 , cp2 ≪ CB1 , CB2 , CL and k 2 , k 3 < 10 (15-4)
Applying Laplace transforms and KCL to nodes N1, N2 and OUT in Fig. (15-3) and using
Eqs. (15-2) and (15-3):
(g o1 + sC1 )V1 = g m1 Vi (15-5)

192
g m2 V1 + (g o2 + sC2 )V2 = −g mf2 Vi (15-6)
g m3 V2 + ( GL + sCL )Vo = g mf3 Vi (15-7)
g o1 + sC1 0 0 V1 g m1 Vi
[ g m2 g o2 + sC2 0 ] [V2 ] = [−k 2 g m1 Vi ] (15-8)
0 g m3 GL + sCL Vo k 3 g m1 Vi
Applying Cramer’s rule to solve for Vo from (15-8):

go1 +sC1 0 gm1 Vi
| gm2 go2 +sC2 −k2 gm1 Vi |
0 gm3 k3 gm1 Vi
Vo = go1 +sC1 0 0
| gm2 go2 +sC2 0 |
0 gm3 GL +sCL
Using cofactor expansion of the numerator determinant along its third column and expanding
the denominator determinant in full:
g go2 +sC2 g +sC1 0 g +sC1 0
gm1 Vi | m2 |+k2 gm1 Vi | o1 |+k3 gm1 Vi | o1 |
0 gm3 0 gm3 gm2 go2 +sC2
Vo = (go1 +sC1 )(go2 +sC2 )( GL +sCL )

g go2 +sC2 g +sC1 0 g +sC1 0
Vo (s) gm1 | m2 |+k2 gm1 | o1 |+k3 gm1 | o1 |
0 gm3 0 gm3 gm2 go2 +sC2
Av (s) = =
Vi (s) (go1 +sC1 )(go2 +sC2 )( GL +sCL )
Expanding the numerator determinants and rearranging:
gm1 [s2 k3 C1 C2 +s(k2 C1 gm3 +k3 C2 go1 +k3 C1 go2 )+gm2 gm3 +k2 gm3 go1 +k3 go1 go2 ]
Av (s) = (go1 +sC1 )(go2 +sC2 )( GL +sCL )

2k
̃ v (s) = gm1 (s
A 3 C1 C2 + sk2 C1 gm3 + gm2 gm3 )
(g 01 +sC1 )(g02 +sC2 )( GL +sCL )
Factoring out g o1 , g o2 and GL in the denominator and rearranging the numerator:

k C C k C
gm1 gm2 gm3 (s2 3 1 2 + s 2 1 + 1)
gm2 gm3 gm2
̃ v (s) =
A C C C
go1 go2 GL (s 1 + 1)(s 2 + 1)(s L + 1)
go1 go2 GL
Replacing the conductances using Eq. (15-2) and rearranging we arrive at the transfer
k C C k C
gm1 gm2 gm3 ro1 ro2 RL (s2 3 1 2 + s 2 1 + 1)
gm2 gm3 gm2
̃ v (s) =
A (15-9)
(sC1 ro1 +1)(sC2 ro2 +1)(sCL RL +1)
193
Factorization
We leave the numerator of Eq. (15-9) un-factorised so that we may locate its zeros with PZL
parameters at a later stage using the method described in Section 2.4.3.
Poles and Zeros
Writing (15-9) in terms of its poles and zeros:
̃ v = A0(sτz1+1)(sτz2+1)
A (15-10)
(sτ +1)(sτ +1)(sτ +1)
p1 p2 p3
Comparing Eqs. (15-9) and (15-10), the three poles are given by:
1 1
ωp1 = τ =C (15-11)
p1 1 ro1
1 1
ωp2 = = (15-12)
τp2 C2 ro2
and
1 1
ωp3 = τ =C (15-13)
p3 L RL
Using Eq. (2-24) in addition to the above equations:

1 gm2 gm3
ωz1 ωz2 = τ = (15-14)
z1 τz2 k3 C 1 C 2
A0 = g m1 g m2 g m3 ro1 ro2 R L (15-15)
We decide to use phase-lead compensation with ωp1 , ωp2 , ωp3 , ωz1 and ωz2 below the
unity-gain frequency ω0 . Therefore, using Eqs. (2-66) and (15-11) to (15-15) we find:
k3 gm1 gmf3
ω0 = = (15-16)
CL CL
We do not define any PZL parameter for ωp1 , ωp2 and ωp3 noting those to be low-frequency
far-away poles. However, we can express those in terms of ω0 combining Eqs. (15-11) to
(15-13) with Eqs. (15-15) and (15-16) such as:
ω C C
01 L L
194
ω C C
02 L L
and
ω
03
We define PZL parameters σ and μ for ωz1 and ωz2 such that:
ωz2 = σω0 (15-20)
and
ωz1 = μωz2 = σμω0 (15-21)
Substituting Eqs. (15-20) and (15-21) into the two factors in the numerator of Eq. (15-10) and
multiplying those we arrive at the quadratic polynomial:
1 1+μ
s 2 σ2 μω2 + s σμω + 1
0 0
Equating the above with the quadratic polynomial in the numerator of Eq. (15-9) we find:
1 k C1 C2
= g3 (15-22)
σ2 μω20 m2 gm3
and
1+μ k2 C 1
= (15-23)
σμω0 gm2
gm3 k23 σ(1+μ) C2

= (C ) (15-24)
gm1 k2 L

gm2 k2 k3 σμ C1
= (C ) (15-25)
gm1 1+μ L
ϕm = 1800 + tan−1 (ω0 τz1 ) + tan−1 (ω0 τz2 ) − tan−1 (ω0 τp1 ) − tan−1 (ω0 τp2 )
−tan−1 (ω0 τp3 )
195
1 1
ϕm = 1800 + tan−1 (σμ) + tan−1 (σ) − tan−1 (A01 ) − tan−1 (A02 ) − tan−1 (A03 ) (15-26)
Tab. 15-2. Amplifier specifications


1 1
We decide on σ = 4 and μ = 1 with σμ = 4, locating the ωz1 and ωz2 on top of each other
and below ω0 in frequency. Using these values of σ and μ in Eq. (15-26) and assuming
̃ m = 61.920 .
A01 , A02 and A03 to be large numbers, the estimated phase margin is ϕ
Using g mf3 = 2mS, f0 = 53.05MHz from Eq. (15-16).
We use C1 = C2 = 3pF, cp1 = 100fF and cp2 = 200fF. Then CB1 = 2.9pF and CB2 = 2.8pF
from Eq. (15-3).
Using k 2 = 2 and k 3 = 4, we find g m1 = 500μS and g mf2 = 1mS from Eq. (15-1), g m2 =
250μS from Eq. (15-25) and g m3 = 1mS from Eq. (15-24).
Using ro1 = 200kΩ, ro2 = 200kΩ we find A01 = 200 from Eq. (15-17), A02 = 200 from
Eq. (15-18), A03 = 20 from Eq. (15-19) and A0 = 50,000 ≈ 93.98dB from Eq. (15-15).
ϕm = 1800 + 75.960 + 75.960 − 89.710 − 89.710 − 87.140 = 65.360 .
196

4 Bandwidth limiting capacitor first stage CB1 2.9 pF
8 Bandwidth limiting capacitor second stage CB2 2.8 pF
9 Third stage transconductance g m3 1 mS
12 Feedforward transconductance to second stage g mf2 1 mS
13 Feedforward transconductance ratio second stage k2 2 −
14 Feedforward transconductance to third stage g mf3 2 mS
15 Feedforward transconductance ratio third stage k3 4 −

3 Third pole fp3 2.6525 MHz
4 First Zero fz1 13.2625 MHz

197

3 Phase margin (unity-feedback factor) ϕm 65.36 64.7 > 60 degrees
4 Phase crossover frequency fπ − 1.5, 9 − MHz
5 Gain Margin (unity-feedback factor) Gm − NA > 10 dB
6 Range of unstable closed-loop gain A̅ cl0 − 24 to 60 − dB
198
199
200
A study of Tabs. 6-3, 6-6, 12-3, 12-6, 15-3 and 15-6 shows that this amplifier has a lower DC
gain compared to those in Chapters 6 and 12 for the same R L value. This happens because of
relatively low g m2 and g m3 values for this amplifier. The performances with various CL
values are very different and some of those are highlighted below.
Eqs. (6-22), (12-19) and (15-16) show that ω0 , for this amplifier, is inversely proportional to
CL instead of CC for the others. This means it is not suitable for variable load applications.
However, comparing Figs. 6-4, 12-4 and 15-4 we see, for nearly equal unity-gain bandwidth,
this amplifier has higher 3-dB bandwidth (200kHz against 100Hz) and larger gain at 1MHz
(70dB against 35dB) despite its DC gain being lower (94dB against 113dB). This
characteristic is typical of non-Miller phase-lead compensated amplifiers because none of the
poles are pushed back to very low frequencies by Miller multiplication of capacitor(s).
Therefore, this compensation is better for high-frequency designs.
From Fig. 15-5 and Tabs 15-4, 15-6 we see that the phase of the loop-gain dips below 0dB
between 1.5MHz and 9MHz. Therefore, there are two phase-crossover frequencies below fc .
However, the phase margin at unity feedback factor meets specifications, indicating the
amplifier is conditionally stable as discussed in Section 2.4.6. It should be possible to come
up with an unconditionally stable amplifier locating ωz1 and ωz2 at lower frequencies
adjusting PZL and circuit parameters, especially CB1 and CB2 , as Eqs. (15-24) and (15-25)
suggest.
From Tab. A17-3 we can see that this amplifier consumes the second lowest power but
largest area among all the three-stage amplifiers. The sizes of CB1 and CB2 in this amplifier
are largely responsible for the area increase.
201
Chapter 16 Four-Stage Amplifier Non-Miller, Active FF
CHAPTER 16
Four-Stage Amplifier with Non-Miller
In Section 15.5 we noted that the bandwidth limiting capacitors CB1 and CB2 are larger than
normal Miller capacitors used in Chapter 6 or 12 thereby increasing area consumption. In a
2006 publication [R1-10], this problem was overcome using Miller multiplication of small
capacitors to realize bandwidth limiting capacitors.
In this chapter we shall be discussing this compensation technique when applied to a four-
stage amplifier. However, we shall stick to the non-Miller version of the compensation.
202
Circuit Diagram

4 Bandwidth limiting capacitor for first stage CB1
7 Parasitic capacitance loading second stage (node N2) cp2
8 Bandwidth limiting capacitor for second stage CB2
10 Net resistance loading third stage (node N3) ro3
11 Parasitic capacitance loading third stage (node N3) cp3
12 Bandwidth limiting capacitor for third stage CB3
13 Fourth stage transconductance (MP9) g m4
14 Net resistance loading fourth stage (node OUT) RL
15 Net capacitance loading fourth stage (node OUT) CL
18 Feedforward transconductance to third stage (M P5, MN4, MN7) g mf3
20 Feedforward transconductance to fourth stage (M P4, MN3, MN8) g mf4
203
Block Diagram
Referring to Figs. 16-1 and 16-2 and Table 16-1, transistors MP1, MP2, MP3, MN1, MN2 and
MP4, MP5, MP6, MN3, MN4 constitute the first stage represented by the block marked g m1
where g m1 is the transconductance of any one of MP1, MP2, MP4 or MP5. Transistors MN5 and
MP7 constitute the second stage represented by the block marked g m2 where g m2 is the
transconductance of MN5. Transistors MP8 and MN7 constitute the third stage represented by
the block marked g m3 where g m3 is the transconductance of MP8. Transistors MP9 and MN8
constitute the fourth stage represented by the block marked g m4 where g m4 is the
transconductance of MP9. The feedforward path with transconductance g mf2 is provided
through transistors MP4, MN3 and MN6 and is represented by the block marked g mf2 . The
feedforward path with transconductance g mf3 is provided through transistors MP5, MN4 and
MN7 and is represented by the block marked g mf3 . The feedforward path with
transconductance g mf4 is provided through transistors MP4, MN3 and MN8 and is represented
by the block marked g mf4 . The transconductances g mf2 , g mf3 and g mf3 are given by:
g g
g mf2 = k 2 g m1 where k 2 = 2gmN6 and g mf3 = k 3 g m1 where k 3 = 2gmN7
mN3 mN4
g
and g mf4 = k 4 g m1 where k 4 = 2gmN8 (16-1)
mN3
204
simplified in Fig. 16-3 as per discussions in Section 3.5. Parasitic capacitances associated
with g mf2 , g mf3 and g mf4 have been neglected too.

1 1 1 1
g o1 = r , g o2 = r , g o3 = r , GL = R (16-2)
o1 o2 o3 L
We define:
C1 = cp1 + CB1 , C2 = cp2 + CB2 , C3 = cp3 + CB3 (16-3)
g m1 , g m2 , g m3 , g m4 ≫ g o1 , g o2 , g o3 , GL ; cp2 , cp2 , cp3 ≪ CB1 , CB2 , CB3 , CL
and k 2 , k 3 , k 4 < 10 (16-4)
Applying Laplace transforms and KCL to nodes N1, N2, N3 and OUT in Fig. (16-3) and using
Eqs. (16-2) and (16-3):
(g o1 + sC1 )V1 = g m1 Vi (16-5)
g m2 V1 + (g o2 + sC2 )V2 = −g mf2 Vi (16-6)
g m3 V2 + (g o3 + sC3 )V3 = g mf3 Vi (16-7)
g m4 V3 + (GL + sCL )Vo = −g mf4 Vi (16-8)
g o1 + sC1 0 0 0 V1 g m1 Vi
g m2 g o2 + sC2 0 0 V −k g V
[ ] [ 2 ] = [ 2 m1 i ] (16-9)
0 g m3 g o3 + sC3 0 V3 k 3 g m1 Vi
0 0 g m4 GL + sCL Vo −k 4 g m1 Vi
Using Cramer’s rule to solve for Vo from Eq. (16-9):

go1 +sC1 0 0 gm1 Vi
gm2 go2 +sC2 0 −k2 gm1 Vi
| |
0 gm3 go3 +sC3 k3 gm1 Vi
0 0 gm4 −k4 gm1 Vi
Vo = go1 +sC1 0 0 0
gm2 go2 +sC2 0 0
| |
0 gm3 go3 +sC3 0
0 0 gm4 GL +sCL
Using cofactor expansion of the numerator determinant along its third column and expanding
the denominator determinant in full:
205
gm2 go2 +sC2 0 go1 +sC1 0 0

−gm1 Vi | 0 gm3 go3 +sC3 |−k2 gm1 Vi | 0 gm3 go3 +sC3 |
0 0 gm4 0 0 gm4
go1 +sC1 0 0 go1 +sC1 0 0
−k3 gm1 Vi | gm2 go2 +sC2 0 |−k4 gm1 Vi | gm2 go2 +sC2 0 |
0 0 gm4 0 gm3 go3 +sC3
Vo = (go1 +sC1 )(go2 +sC2 )(go3 +sC3 )( GL +sCL )

gm2 go2 +sC2 0 go1 +sC1 0 0
−gm1 | 0 gm3 go3 +sC3 |−k2 gm1 | 0 gm3 go3 +sC3 |
0 0 gm4 0 0 gm4
go1 +sC1 0 0 go1 +sC1 0 0
−k3 gm1 | gm2 go2 +sC2 0 |−k4 gm1 | gm2 go2 +sC2 0 |
Vo (s) 0 0 gm4 0 gm3 go3 +sC3
Av (s) = = (go1 +sC1 )(go2 +sC2 )(go3 +sC3 )( GL +sCL )
Vi (s)
Expanding the numerator determinants fully and rearranging:
s3 k4 C1 C2 C3 +s2 (k3 C1 C2 gm4 +k4 C1 C2 go3 +k4 C1 C3 go2 +k4 C2 C3 go1 )

−gm1 [+s(k2 C1 gm3 gm4 +k3 C1 gm4 go2 +k3 C2 gm4 go1 +k4 C1 go2 go3 +k4 C2 go1 go3 +k4 C3 go1 go2 )]
+(gm2 gm3 gm4 +k2 gm3 gm4 go1 +k3 gm4 go1 go2 +k4 go1 go2 go3 )
Av (s) = (sC1 +go1 )(sC2 +go2 )(sC3 +go3 )(sCL +GL )

3k 2k
̃ v (s) = −gm1(s
A 4 C1 C2 C3 +s 3 C1 C2 gm4 +sk2 C1 gm3 gm4 +gm2 gm3 gm4 )
(sC1 +go1 )(sC2 +go2 )(sC3 +go3 )(sCL +GL )
Factoring out g o1 , g o2 , g o3 and GL in the denominator and rearranging the numerator:

k4 C1 C2 C3 k C C k C
−gm1 gm2 gm3 gm4 (s3 +s2 3 1 2 +s 2 1 +1)
̃ v (s) =
A C C C C
go1 go2 go3 GL (s 1 + 1)(s 2 + 1)(s 3 + 1)(s L + 1)
go1 go2 go3 GL
Replacing the conductances using Eq. (16-2) and rearranging, we arrive at the transfer
k4 C1 C2 C3 k C C k C
−gm1 gm2 gm3 gm4 ro1 ro2 ro3 RL (s3 +s2 3 1 2 +s 2 1 +1)
̃ v (s) =
A (16-10)
(sC1 ro1 +1)(sC2 ro2 +1)(sC3 ro3 +1)(sCL RL +1)
Factorization
We leave the numerator of Eq. (16-10) un-factorised so that we may locate its zeros with PZL
parameters at a later stage using the method described in Section 2.4.3.
Poles and Zeros
Writing (16-10) in terms of its poles and zeros:

A0 (sτz1 +1)(sτz2 +1)(sτz3 +1)
̃ v (s) =
A (16-11)
(sτ +1)(sτ +1)(sτ +1)(sτ +1)
p1 p2 p3 p4
206
Comparing (16-10) and (16-11) the four poles are given by:
1 1
ωp1 = τ =C (16-12)
p1 1 ro1
1 1
ωp2 = τ =C (16-13)
p2 2 ro2
1 1
ωp3 = τ =C (16-14)
p3 3 ro3
and
1 1
ωp4 = τ =C (16-15)
p4 L RL
Using Eq. (2-30) in addition to the above equations:

1 gm2 gm3 gm4
ωz1 ωz2 ωz3 = τ = (16-16)
z1 τz2 τz3 k3 C 1 C 2 C 3
16.4. Design to meet specifications
DC gain and Unity-Gain Frequency
A0 = g m1 g m2 g m3 g m4 ro1 ro2 ro3 R L (16-17)
We decide to use phase-lead compensation with ωp1 , ωp2 , ωp3 , ωp4 , ωz1 , ωz2 and ωz3
below the unity-gain frequency ω0 . Therefore, using Eqs. (2-66) and (16-12) to (16-17) we
find:
k4 gm1 gmf4
ω0 = = (16-18)
CL CL
We do not define any PZL parameter for ωp1 , ωp2 , ωp3 and ωp4 noting those to be low-
frequency far-away poles. However, we can express those in terms of ω0 combining Eqs.
(16-12) to (16-15) with Eqs. (16-17) and (16-18) such as:
ω C C
01 L L
ω C C
02 L L
ω C C
03 L L
and
ω
04
207
We define PZL parameters σ and μ for ωz1 , ωz2 and ωz3 such that:
ωz3 = σω0 (16-23)
ωz2 = μωz3 = σμω0 (16-24)
and
ωz1 = μωz2 = σμ2 ω0 (16-25)
Substituting Eqs. (16-23) to (16-25) into the three factors in the numerator of Eq. (16-11) and
multiplying those we arrive at the cubic polynomial:
1 1+μ+μ2 1+μ+μ2
s 3 σ3 μ3ω3 + s2 σ2μ3 ω2 + s +1
0 0 σμ2 ω0
Equating the above with the cubic polynomial in the numerator of Eq. (16-10) we find:
1 k4 C 1 C 2 C 3
=g (16-26)
σ3 μ3 ω30 m2 gm3 gm4
1+μ+μ2 k C1 C2
= g3 (16-27)
σ2 μ3 ω20 m2 gm3
and
1+μ+μ2 k2 C 1
= (16-28)
σμ2 ω 0 gm2
gm4 k24 σ(1+μ+μ2 ) C3

gm1
= k3
(C ) (16-29)
L
Combining (16-18), (16-27) and (16-28):

gm3 k3 k4 σμ C2
= (C ) (16-30)
gm1 k2 L

gm2 k2 k4 σμ2 C1
= (C ) (16-31)
gm1 1+μ+μ2 L
ϕm = 1800 + tan−1 (ω0 τz3 ) + tan−1 (ω0 τz2 ) + tan−1 (ω0 τz1 )
−tan−1 (ω0 τp1 ) − tan−1 (ω0 τp2 ) − tan−1 (ω0 τp3 ) − tan−1 (ω0 τp4 )
208
Substituting (16-19) to (16-25) in above we arrive at:

1 1 1
ϕm = 1800 + tan−1 (σ) + tan−1 (σμ) + tan−1 (σμ2 )
−tan−1 (A01 ) − tan−1 (A02 ) − tan−1 (A03 ) − tan−1 (A04 ) (16-32)


1 1
We decide on σ = 6 and μ = 1 with σμ = 6, locating the ωz1 , ωz2 and ωz3 on top of each
other and below ω0 in frequency. Using these values of σ and μ in Eq. (16-32) and assuming
̃ m = 61.620 .
A01 , A02 , A03 and A04 to be large numbers, the estimated phase margin is ϕ
Using g mf4 = 2mS, f0 = 53.05MHz from Eq. (16-18).
We use C1 = C2 = C3 = 3pF, cp1 = cp2 = 100fF and cp3 = 200fF. Then, CB1 = CB2 =
2.9pF and CB3 = 2.8pF from Eq. (16-3).
Using k 2 = k 3 = k 4 = 4 we find g m1 = 500μS and g mf2 = g mf3 = g mf4 = 2mS from Eq.
(16-1), g m2 = 222μS from Eq. (16-31), g m3 = 167μS from Eq. (16-30) and g m4 = 500μS
using Eq. (16-29).
Choosing ro1 = ro2 = ro3 = 200kΩ, we find A01 = A02 = A03 = 200 and A01 = 20 using
Eqs. (16-19) to (16-22) and A0 = 741480 ≈ 117.40dB using Eq. (16-17).
ϕm = 1800 + 80.540 + 80.540 + 80.540
−89.710 − 89.710 − 89.710 − 87.140 = 65.350 .
209

7 Third stage transconductance g m3 167 μS
8 Third stage resistive load ro3 200 kΩ
9 Third stage capacitive load cp3 200 fF
10 Fourth stage transconductance g m4 500 μS
11 Fourth stage resistive load RL 10 kΩ
12 Fourth stage capacitive load CL 6 pF
13 Feedforward transconductance to 2nd stage g mf2 2 mS
14 Feedforward transconductance ratio 2nd stage k2 4 −
15 Feedforward transconductance to 3rd stage g mf3 2 mS
16 Feedforward transconductance ratio 3rd stage k3 4 −
17 Feedforward transconductance to 4th stage g mf4 2 mS
18 Feedforward transconductance ratio 4th stage k4 4 −
19 Bandwidth limiting capacitor 1st stage CB1 2.9 pF
20 Bandwidth limiting capacitor 2nd stage CB2 2.9 pF
21 Bandwidth limiting capacitor 3rd stage CB3 2.8 pF

3 Third pole fp3 265.25 kHz
4 Fourth pole fp4 2.6525 MHz
5 First Zero fz1 8.8417 MHz
7 Third zero fz3 8.8417 MHz

16.4.3 Design Evaluation
210

3 Phase margin (unity feedback factor) ϕm 65.35 64.7 > 60 degrees
4 Phase crossover frequency fπ − 0.45, 13 − MHz
5 Gain margin (unity feedback factor) Gm − NA > 10 dB
6 Range of unstable closed-loop gain A̅ cl0 − 16 to 100 − dB
211
Fig. 16.4. Unity feedback factor loop-gain magnitude response for the amplifier.
Fig. 16.5. Unity feedback factor loop-gain phase response for the amplifier.
212
213
A study of Tabs. 13-3, 13-6, 16-3 and 16-6 shows that this amplifier has a lower DC gain
compared to the amplifier in Chapter 13 for a higher R L value. This happens because of
relatively low g m2 , g m3 and g m4 values for this amplifier. The performances with various CL
values are very different and some of those are highlighted below.
Eqs. (13-17) and (16-18) show that ω0 , for this amplifier, is inversely proportional to CL
instead of CC for the other one. This means it is not suitable for variable load applications.
However, comparing Figs. 13-4 and 16-4 we see, for nearly equal unity-gain bandwidth, this
amplifier has higher 3-dB bandwidth (200kHz against 12Hz) and larger gain at 1MHz (80dB
against 35dB) despite its DC gain being lower (112dB against 132dB). This characteristic is
typical of non-Miller phase-lead compensated amplifiers because none of the poles is pushed
back to very low frequencies by Miller multiplication of capacitor(s). Therefore, this
compensation is better for high-frequency designs.
From Fig. 16-5 and Tabs 16-4, 16-6 we see that the phase of the loop-gain dips below 0dB
between 450kHz and 13MHz. Therefore, there are two phase-crossover frequencies below fc .
However, the phase margin at unity feedback factor meets specifications, indicating the
amplifier is conditionally stable as discussed in Section 2.4.6. It should be possible to come
up with an unconditionally stable amplifier locating ωz1 , ωz2 and ωz3 at lower frequencies
adjusting PZL and circuit parameters, especially CB1 , CB2 and CB3 , as Eqs. (16-29) to (15-31)
suggest.
From Tab. A17-4 we can see that this amplifier consumes lower power, but larger area
compared to the one in Chapter 13. The sizes of CB1 , CB2 and CB3 in this amplifier are largely
responsible for this.
Additionally, we may take note of a trend emerging on the dependence of ω0 on CC and CL

among the amplifiers discussed in this book. For amplifiers using dominant pole
compensation with Miller (floating) capacitors as in Chapters 4 to 13 except 10, ω0 is
inversely proportional to CC and independent of CL . For the ones using phase-lead
compensation with Miller capacitors as in Chapter 10, ω0 is inversely proportional to the
square root of the CL CC product. For the ones using phase-lead compensation with non-Miller
(grounded) capacitors as in Chapters 14 to 16, ω0 is inversely proportional to CL only. The
above opposing trends seem to merge for the amplifier in Chapter 3 which uses dominant
pole compensation with a non-Miller capacitor and ω0 is inversely proportional to CL which
also serves as CC .
In conclusion, we may say only the amplifiers in Chapters 4 to 9 and 11 to 13 are suitable for
working with varying CL values. On the other hand, the amplifiers in Chapters 14 to 16 are
quite different from the rest. They have low power consumption and good high-frequency
performance but consume large area and are suitable for operating with fixed CL values only.
214
Appendix 1 Symbols and Notations
Appendix 1
Symbols and Notations
Tab. A1-1. Mathematical notations.
No. Notation Description Example

1 𝐴 Matrix 𝑎 𝑏
𝐴=[ ]
𝑐 𝑑
2 det⁡(𝐴) Determinant of matrix 𝐴 𝑎 𝑏
det(𝐴) = | |
𝑐 𝑑
3 𝑣⃗ Vector 𝑣1
𝑣⃗ = [𝑣 ]
2
4 𝑎𝑝𝑞 An element of matrix 𝐴 𝑎13 is the element in the first row and third
or det⁡(𝐴) column
5 𝑓(𝑥) A function of the variable 𝑥 𝑓(𝑥) = 𝑎𝑥 2 + 𝑏𝑥 + 𝑐
6 𝑃(𝑥) Polynomial function of the variable 𝑥 𝑃(𝑥) = 𝑎𝑛 𝑥 𝑛 + 𝑎𝑛−1 𝑥 𝑛−1 + ⋯ + 𝑎1 𝑥 + 𝑎0
7 𝑓(𝑥, 𝑦) A function of the variables 𝑥 and 𝑦 𝑓(𝑥, 𝑦) = 𝑎𝑥 2 + 𝑏𝑦 2
8 𝑗 √−1 Complex number 𝑧 = 𝑎 + 𝑗𝑏
9 |𝑧| Magnitude of complex number 𝑧 |𝑧| = √𝑎2 + 𝑏 2
10 〈𝑧〉 Phase angle of complex number 𝑧 𝑏
〈𝑧〉 = tan−1 ( )
𝑎
11 ≫ Much larger than 𝑎 ≫𝑏+𝑐

12 ≪ Much less than 𝑎 ≪𝑏−𝑐
13 ≈ Approximate value of a variable 𝑏
𝑎≈
𝑐
14 ≅ Approximate equation 𝐹(𝑥) ≅ (𝑥 + 𝑎)(𝑥 + 𝑏)
15 ! Factorial sign 𝑛! = 1.2.3.4 … (𝑛 − 2)(𝑛 − 1)𝑛
16 ~ More or less 𝑎⁡~⁡1
17 NN Does not exist −
18 NA Not available −
Tab. A1-2. Frequency and related parameters/variables.
No. Symbol Description Units

1 ω Angular frequency rad./sec.
2 f = ω/2π Frequency Hz
3 τ, ζ = 1/ω Time-constant sec.
4 ω0 Ideal gain crossover or unity-gain angular frequency (β = 1) rad./sec.
5 f0 = ω0 /2π Ideal gain crossover or unity-gain frequency (β = 1) Hz
6 ωc Actual gain crossover or unity-gain angular frequency (β = 1) rad./sec.
7 fc = ωc /2π Actual gain crossover or unity-gain frequency (β = 1) Hz
8 ωπ Phase crossover angular frequency rad./sec.
9 fπ = ωπ /2π Phase crossover frequency Hz
10 ωpx Real pole frequency (negated): x = 1, 2, 3, … in increasing order rad./sec.
11 fpx = ωpx /2π Real pole frequency (negated): x = 1, 2, 3, … in increasing order Hz
12 τpx = 1/ωpx Time-constant corresponding to ωpx sec
13 ωpxx Complex pole (magnitude): xx = consecutive numbers to go with ωpx rad./sec.
14 fpxx = ωpxx /2π Complex pole (magnitude): xx = consecutive numbers to go with fpx Hz
15 τpxx = 1/ωpxx Time-constant corresponding to ωpxx sec.
16 ωzx Real zero frequency (negated): x = 1, 2, 3, … in increasing order rad./sec.
17 fzx = ωzx /2π Real zero frequency (negated): x = 1, 2, 3, … in increasing order Hz
18 τzx = 1/ωzx Time-constant corresponding to ωzx sec.
215
Tab. A1-3. Circuit parameters and signal voltages.
No. Symbol Description

1 g mx Gain stage transconductance: x = stage number
2 g mfx Feedforward transconductance: x = to or from stage number
3 rox Net resistance loading output of gain stage: x = stage number
4 g ox = 1/rox Net conductance loading output of gain stage: x = stage number
5 cpx Net parasitic capacitance loading output of gain stage: x = stage number
6 RL Net resistance loading output stage
7 GL = 1/R L Net conductance loading output stage
8 CL Net capacitance loading output stage
9 R L1 Externally applied resistive load
10 CL1 Externally applied capacitive load
11 RX Internal resistance used for compensation or as defined in text: X = capital letter
12 CX Internal capacitance used for compensation or as defined in text: X = capital letter
13 YX Internal admittance used for compensation or as defined in text: X = capital letter
14 vx Signal voltage level at node number x
15 vi Signal input source voltage level
16 vo Signal voltage level at output
Tab. A1-4. Performance parameters.
No. Symbol Description Units

1 A0 Magnitude of DC gain dB
2 Acl0 Magnitude of DC closed-loop gain dB
3 β ≈ 1/A cl0 Feedback factor (frequency independent) −
4 ̅ cl0
A Range of unstable DC closed-loop gains dB
5 Av Transfer function −
6 ̃v
A Approximate transfer function −
7 AvdB Magnitude of transfer function dB
8 Φv Phase of transfer function deg.
9 ϕm Phase margin deg.
10 ϕ̃m First estimate of phase margin deg.
11 Gm Gain margin dB
12 Acell Amplifier cell area μm2
13 Pcell Amplifier cell power consumption μW
Tab. A1-5. PZL and other parameters/variables.

1 σ PZL parameter
2 μ PZL parameter
3 λ PZL parameter
4 ρ PZL parameter
5 δpxx Damping factor for complex pole ωpxx
6 κ Parameter related to quadratic equation
7 ε Amount of magnitude response peaking due to complex pole
8 k, m, n, p, q Integers or circuit parameters as defined in text.
9 s Laplace Transform variable
10 kx Ratio of g mfx : g m1
216
Tab. A1-6. Circuit symbols/notations.
1 Resistor R X
2 Capacitor CX
3
N-Channel MOS Transistor MNx
4
P-Channel MOS Transistor MPx
5
NPN Bipolar Transistor Q Nx
6 Block representing gain-stage g mx or ⁡g mfx
7 Block representing current conveyor g mx
3 Controlled current source g mx1 vx2
8 Signal voltage source vi
9 Signal ground (reference)
10 VDD Positive power supply voltage input terminal

11 VSS Negative power supply voltage input terminal
12 OUT Amplifier output terminal
13 INM Amplifier inverting input terminal
14 INP Amplifier non-inverting input terminal
15 VBNX Bias voltage input terminal for N-Channel MOS transistors: x = 1, 2
16 VBPX Bias voltage input terminal for P-Channel MOS transistors: x = 1, 2
217
Appendix 2 Useful Results, Magnitude Response
Appendix 2
Useful Results Pertaining to Magnitude Response
A2.1. Deviation of 𝛚𝐜 from 𝛚𝟎 due to Close-In Poles/Zeros
Assuming the slope of the magnitude curve to be −20dB/decade at ωc and ω0 :
̃ vdB (ω0 ) = −20 log (ωc )

̃ vdB (ωc ) − A
A ω 0
̃ vdB (ωc ) = 0dB, we have from the above:

Since A
̃ vdB (ω0 ) = 20 log (ωc )

A (A2-1)
ω 0
A2.1.1 Close-In Simple Zero in Dominant Pole Compensation
In this case we consider the dominant pole ωp1 and the zero ωz1 just above ω0 only,
neglecting all other poles/zeros. Then the transfer function is given by:
̃ v (s) = A0 (sτz1+1)
A (A2-2)
sτ +1p1
Setting s = jω in Eq. (A2-1) and applying ω0 ≫ ωp1 so that sτp1 ≫ 1:
̃ v (jω) = A0(1+jωτz1)
A jωτ p1
We now find ωc by setting ω = ωc in the above and equate its magnitude with unity to
obtain:
A0 √1+ω2c τ2z1
1= ωc τp1
Whence, we arrive at:
ω2c (τ2p1 − A20 τ2z1 ) − A20 = 0
Using Eq. (2-63) and defining ωz1 = σω0 with PZL parameter σ in the above:
ω2c
(σ2 − 1) − σ2 = 0 (A2-3)
ω20
The results of the analysis for Eq. (A2-2) were computed using Eqs. (A2-1) and (A2-3) and
summarised in the table below:
218
Tab. A2-1. Results of proximity analysis for Eq. (A2-2).
𝛚𝐜 : 𝛚𝟎 ̃ 𝐯𝐝𝐁 (𝛚𝟎 )
𝐀 𝛔
Actual to ideal ratio of gain crossover freq. dB Magnitude at 𝛚𝟎 PZL parameter
1.15 (15% deviation) 1.21 2.03
1.10 (10% deviation) 0.83 2.40
1.05 (5% deviation) 0.42 3.28
A2.1.2 Close-In Simple Pole in Dominant Pole Compensation
In this case we consider the dominant pole ωp1 and the pole ωp2 just above ω0 only,
neglecting all other poles/zeros. Then the transfer function is given by:
A0
̃ v (s) =
A (A2-4)
(sτ p1 +1)(sτp2 +1)

A0 A0
̃ v (jω) =
A = −ω2τ
jωτ p1 (1+jωτp2 ) p1 τp2 +jωτp1
obtain:
A0
1=
√ω4c τ2p1 τ2p2 +ω2c τ2p1
ω4c τ2p1 τ2p2 + ω2c τ2p1 − A20 = 0
Using Eq. (2-63) and defining ωp2 = σω0 with PZL parameter σ in the above:
ω4c ω2
+ σ2 ωc2 − σ2 = 0 (A2-5)
ω4
0 0
𝛚𝐜 : 𝛚𝟎 ̃ 𝐯𝐝𝐁 (𝛚𝟎 )
𝐀 𝛔
0.85 (–15% deviation) –1.41 1.37
0.90 (–10% deviation) –0.92 1.86
0.95 (–5% deviation) –0.45 2.89
219
A2.1.3. Close-In Complex Pole Pair in Dominant Pole Compensation
In this case we consider the dominant pole ωp1 and the complex pole pair ωp23 just above
ω0 only, neglecting all other poles/zeros. Then the transfer function is given by:
A0
̃ v (s) =
A 2 2
(A2-6)
(sτ p1 +1)(s τp23 +2sτp23 δp23 +1)

A0 A0
̃ v (jω) =
A 2 2 = −2ω2τ 2 2
jωτ p1 (1−ω τp23 +j2ωτp23 δp23 ) p1 τp23 δp23 +jωτp1 (1−ω τp23 )
obtain:
A0
1= 2
√4ω4c τ2p1 τ2p23 δ2p23 +ω2c τ2p1 (1−ω2c τ2p23 )
ω6c τ2p1 τ2p23 + 2ω4c (2δ2p23 − 1)τ2p1 τ2p23 + ω2c τ2p1 − A20 = 0
Using Eq. (2-63) and defining ωp23 = σω0 with PZL parameter σ in the above:
ω6c ω4 ω2
+ 2σ2 (2δ2p23 − 1) ωc4 + σ4 ωc2 − σ4 = 0 (A2-7)
ω60 0 0
summarised in the tables below:
Tab. A2-3. Results of proximity analysis for Eq. (A2-6) with δp23 = 0.8.
𝛚𝐜 : 𝛚𝟎 ̃ 𝐯𝐝𝐁 (𝛚𝟎 )
𝐀 𝛔
0.85 (–15% deviation) –1.41 1.34
0.90 (–10% deviation) –0.92 1.70
0.95 (–5% deviation) –0.45 2.44
𝛚𝐜 : 𝛚𝟎 ̃ 𝐯𝐝𝐁 (𝛚𝟎 )
𝐀 𝛔
0.85 (–15% deviation) –1.41 1.08
0.90 (–10% deviation) –0.92 1.29
0.95 (–5% deviation) –0.45 1.66
220
𝛚𝐜 : 𝛚𝟎 ̃ 𝐯𝐝𝐁 (𝛚𝟎 )
𝐀 𝛔
0.85 (–15% deviation) –1.41 0.87
0.90 (–10% deviation) –0.92 0.98
0.95 (–5% deviation) –0.45 1.13
𝛚𝐜 : 𝛚𝟎 ̃ 𝐯𝐝𝐁 (𝛚𝟎 )
𝐀 𝛔
0.85 (–15% deviation) –1.41 0.75
0.90 (–10% deviation) –0.92 0.82
0.95 (–5% deviation) –0.45 0.91
A2.1.4. Close-In Zero in Phase-Lead Compensation
In this case we consider two low-frequency far-away poles ωp1 and ωp2 and one zero ωz1
just below ω0 only, neglecting all other poles/zeros. Then the transfer function is given by:
̃ v (s) = A0(sτz1+1)
A (A2-8)
(sτ +1)(sτ +1)
p1 p2
Setting s = jω in Eq. (A2-8) and applying ω0 ≫ ωp1 , ωp2 so that sτp1 , sτp2 ≫ 1:
̃ v (jω) = A0 (1+jωτz1) = A0 (1+jωτ

A z1 )
(jωτ )(jωτ )p1 −ω2 τ τ
p2 p1 p2
obtain:
A0 √1+ω2c τ2z1
1= ω2c τp1 τp2
ω4c τ2p1 τ2p2 − ω2c A20 τ2z1 − A20 = 0
Using Eq. (2-66) and defining ωz1 = σω0 with PZL parameter σ in the above:
ω4c ω2
− ωc2 − σ2 = 0 (A2-9)
ω40 0
221
𝛚𝐜 : 𝛚𝟎 ̃ 𝐯𝐝𝐁 (𝛚𝟎 )
𝐀 𝛔
1.15 (15% deviation) 1.21 0.65
1.10 (10% deviation) 0.83 0.50
1.05 (5% deviation) 0.42 0.34
A2.2. Magnitude Response Peaking due to Damping Factor of Complex Pole Pair
In this case, we consider a single complex pole pair. The transfer function is given by:
A0
̃ v (s) = 2 2
A (A2-10)
s τ p23 +2sτp23 δp23 +1
Setting s = jω in Eq. (A2-10):

A0
̃ v (jω) =
A 1−ω2 τ2 p23 +j2ωτp23 δp23
The magnitude squared of the above can be found to be:
A20 A20
̃ v (ω)|2 =
|A 2 = ω4τ4 2 τ2 (2δ2 −1)+1 (A2-11)
(1−ω2 τ2p23 ) +4ω2 τ2p23 δ2p23 p23 +2ω p23 p23
The value ω = ωm at which Eq. (2-11) has a maximum can be found by setting the
derivative of with respect to ω of the denominator to zero such that:
4ω3m τ4p23 + 4ωm τ2p23 (2δ2p23 − 1) = 0
Whence we find:
1−2δ2p23
ω2m = (A2-12)
τ2p23
Substituting (A2-12) for ω into (A2-11) we find the maximum value of (A2-11) to be:
A20
̃ v (ω)|2 =
|A (A2-13)
max 4δp23 (1−δ2p23 )
2
The amount of peaking ε can be found from (A2-11) with ω = 0 and (A2-13) as:
̃ v (ω)|
|A 1
max
ε= ̃ v (0)|
|A
= (A2-14)
2δp23 √1−δ2p23
Amounts of peaking for various values of damping factors were computed and listed in the
table below:
222
Tab. A2-8. Amount of magnitude response peaking with damping factor for Eq. (A2-10).
No. Damping factor 𝛅𝐩𝟐𝟑 Amount of peaking 𝛆 in dB

1 0.7 0.002
2 0.6 0.355
3 0.5 1.250
4 0.4 2.695
5 0.3 4.847
6 0.2 8.136
7 0.1 14.023
223
Appendix 3 Plot Formulae for Chapter 3
Appendix 3
Formulae for Plots in Chapter 3
A3.1. Frequency Response from the Transfer Function
We substitute s = jω in Eq. (3-5) and re-arrange to obtain:

cp
−gm1 ro1 (1+jω )
2gmm
Av (jω) = cp (A3-1)
(1+jωCC ro1 )(1+jω )
gmm
We define:
A0 = g m1 ro1 (A3-2)
NC1 = ωCC ro1 (A3-3)

ωcp
Npm = g (A3-4)
mm
We can re-write Eq. (A3-1) using Eqs. (A3-2) to (A3-4) as:

1
−A0 (1+j Npm )
2
Av (jω) = (1+jN (A3-5)
C1 )(1+jNpm )
A3.2. Plotting the Unity Feedback Factor Loop-Gain Responses
We can find the magnitude AvdB (ω) in dB and the phase Φv (ω) in degrees of the loop-gain
with unity feedback factor (Section 2.4.6) from Eq. (A3-5) as:
2 1 2 2
AvdB (ω) = 20log(A0 ) + 10log (1 + 4 Npm ) − 10log(1 + NC1 ) − 10log(1 + Npm ) (A3-6)
1
Φv (ω) = 1800 + tan−1 (2 Npm ) − tan−1(NC1 ) − tan−1(Npm ) (A3-7)
The loop-gain magnitude and phase responses for Eq. (3-5) can now be plotted using Eqs.
(A3-2) to (A3-4), (A3-6), (A3-7) and circuit parameter values in Tab. 3-3.
224
Appendix 4

1
gm1 gm2 ro1 RL [1+jωCc (RC − )]
̃ v (jω) =
A
gm2
(A4-1)
1−ω2 [c 3
p1 (CC +CL )+CC CL ]ro1 RL +j(ωCC gm2 ro1 RL −ω cp1 CC CL ro1 RC RL )
We define:
A0 = g m1 g m2 ro1 R L (A4-2)
NC0 = ωCC g m2 ro1 R L (A4-3)
N11 = ωcp1 ro1 (A4-4)
NCC = ωCC R C (A4-5)
NCL = ωCC R L (A4-6)
NLL = ωCL R L (A4-7)

1
NCZ = ωCc (R C − g ) (A4-9)
m2
We can re-write Eq. (A4-1) using Eqs. (A4-2) to (A4-9) as:

A0 (1+jNCZ )
̃ v (jω) =
A 1−N 11 NCL −N11 NLL −NC1 NLL +j(NC0 −N11 NCC NLL )
Further defining:
XD = 1 − N11 NCL − N11 NLL − NC1 NLL (A4-10)
YD = NC0 − N11 NCC NLL (A4-11)
We arrive at:
̃ v (jω) = A0(1+jNCZ)
A (A4-12)
X +jY
D D
225
2 2
AvdB (ω) = 20log(A0 ) + 10log(1 + NCZ ) − 10log(XD + YD2 ) (A4-13)
Y
Φv (ω) = 1800 + tan−1 (NCZ ) − tan−1 (XD ) (A4-14)
D
226
Appendix 5
We substitute s = jω in Eqs. (5-15) and (5-16) and re-arrange to obtain:

C
gm1 gm2 ro1 RL (1+jω C )
̃ v1 (jω) =
A CL
gmc
cp1 CC CL ro1 RL (A5-1)
1− ω (1+ )cp1 CC ro1 RL +j(ωCC gm2 ro1 RL −ω3
2 )
CC gmc
and
Cp1 CC C
gm1 gm2 r01 RL (1+ω2 +jω C )
2gm2 gmc 2gmc
̃ v2 (jω) =
A C cp1 CC CL ro1 RL (A5-2)
1− ω2 (1+ L )cp1 CC ro1 RL +j(ωCC gm2 ro1 RL −ω3 )
CC gmc
We define:
A0 = g m1 g m2 ro1 R L (A5-3)
C
A1 = 1 + CL (A5-4)
C
NC0 = ωCC g m2 ro1 R L (A5-5)
N11 = ωcp1 ro1 (A5-6)

ωCC
NCC = (A5-9)
gmc
ωcp1
N12 = (A5-10)
gm2
We can re-write Eq. (A5-1) and Eq. (A5-2) using Eqs. (A5-3) to (A5-10) as:
A0 (1+jNCC )
̃ v1 (jω) =
A 1−A 1 N11 NCL +j(NC0 −N11 NCC NLL )
and,
1 1
A0 (1+ N12 NCC +j NCC )
̃ v2 (jω) =
A 2 2
1−A 1 N11 NCL +j(NC0 −N11 NCC NLL )
Further defining:
227
XD = 1 − A1 N11 NCL (A5-11)
YD = NC0 − N11 NCC NLL (A5-12)

1
XN2 = 1 + 2 N12 NCC (A5-13)
1
YN2 = 2 NCC (A5-14)
We arrive at:
̃ v1 (jω) = A0(1+jNCC)
A (A5-15)
X +jY
D D
and
̃ v2 (jω) = A0(XN2+jYN2)
A (A5-16)
X +jY
D D
with unity feedback factor (Section 2.4.6) from Eqs. (A5-15) and (A5-16) as:
2 2
Av1dB (ω) = 20log(A0 ) + 10log(1 + NCC ) − 10log(XD + YD2 ) (A5-17)
Y
Φv1 (ω) = 1800 + tan−1(NCC ) − tan−1 (XD ) (A5-18)
D
2 2 ) 2
Av2dB (ω) = 20log(A0 ) + 10log(XN2 + YN2 − 10log(XD + YD2 ) (A5-19)
Y Y
Φv2 (ω) = 1800 + tan−1 (XN2) − tan−1 (XD ) (A5-20)
N2 D
The loop-gain magnitude and phase responses for Eqs. (5-15) and (5-16) can now be plotted
using Eqs. (A5-3) to (A5-14), (A5-17) to (A5-20) and circuit parameter values in Tab. 5-4.
228
Appendix 6

2ω3 cp2 CC CD ωCC ωCD
gm1 gm2 gm3 ro1 ro2 RL [1 + j( + + )]
gm2 g2 gm2 gm3
̃ v (jω) =
A cp1 2cp2
m3
(A6-1)
1+ω4 ( + )CC CD CL ro1 ro2 RL −ω2 CC CD (gm2 +gm3 )ro1 ro2 RL
gm2 gm3
2ω5 cp1 cp2 CC CD CL ro1 ro2 RL
+ j( −ω3 CC CD CL ro1 ro2 RL +ωCC gm2 gm3 ro1 ro2 RL )
gm2 gm3
We define:
A0 = g m1 g m2 g m3 ro1 ro2 R L (A6-2)
A1 = (g m2 + g m3 )R L (A6-3)
ND2 = ωCD ro2 (A6-5)

ωCC
NC0 = (A6-7)
gm1
ωCC
NC2 = (A6-8)
gm2
ωCD
ND3 = (A6-9)
gm3
ωcp1
N12 = (A6-10)
gm2
2ωcp2
N23 = (A6-11)
gm3
Using (A6-2) to (A6-11) we can write (A6-1) as:

A0 [1 + j(N23 NC2 ND3 +NC2 +ND3 )]
̃ v (jω) =
A 1+(N 12 +N23 )NC1 ND2 NLL −A1 NC1 ND2 +j(N12 N23 NC1 ND2 NLL −NC1 ND2 NLL +A0 NC0 )
Further defining:
XD = 1 + (N12 + N23 )NC1 ND2 NLL − A1 NC1 ND2 (A6-12)
YD = N12 N23 NC1 ND2 NLL − NC1 ND2 NLL + A0 NC0 (A6-13)
229
YN = N23 NC2 ND3 + NC2 + ND3 (A6-14)
We arrive at:
̃ v (jω) = A0(1+jYN )
A (A6-15)
X +jY
D D
AvdB (ω) = 20log(A0 ) + 10log(1 + YN2 ) − 10log(XD

2
+ YD2 ) (A6-16)
Y
Φv (ω) = 1800 + tan−1 (YN ) − tan−1 (XD ) (A6-17)
D
230
Appendix 7
A7.1 Frequency Response from the Transfer Function

ωpCC ωCF
gm1 gm2 gm3 ro1 ro2 RL [1+ j( + )]
gm3 gm2
̃ v (jω) =
A pcp1 CC C2 CL ro1 ro2 RL
1− ω2 CC CF gm3 ro1 ro2 RL + ω4 + j(ωCC gm2 gm3 ro1 ro2 RL − ω3 CC C2 CL ro1 ro2 RL )
gm3
(A7-1)
We define:
A0 = g m1 g m2 g m3 r01 ro2 R L (A7-2)
A1 = g m3 R L (A7-3)
NC1 = ωCC r01 (A7-4)
NF1 = ωCF r02 (A7-5)

ωCC
NC0 = (A7-7)
gm1
ωpCC
NC3 = (A7-8)
gm3
ωCF
NF2 = (A7-9)
gm2
ωpcp1
N13 = (A7-10)
gm3
Using (A7-2) to (A7-10) we can write (A7-1) as:

A0 [1+ j(NC3 +NF2 ) ]
̃ v (jω) =
A
1−A1 NC1 NF1 +pN13 NC1 NF1 NLL + j(A0 NC0 −pNC1 NF1 NLL )
Further defining:
XD = 1 − A1 NC1 NF1 + pN13 NC1 NF1 NLL (A7-11)
YD = A0 NC0 − pNC1 NF1 NLL (A7-12)
YN = NC3 + NF2 (A7-13)
231
We arrive at:
̃ v (jω) = A0(1+jYN )
A (A7-14)
X +jY
D D
AvdB (ω) = 20log(A0 ) + 10log(1 + YN2 ) − 10log(XD

2
+ YD2 ) (A7-15)
Y
Φv (ω) = 1800 + tan−1 (YN ) − tan−1 (XD ) (A7-16)
D
232
Appendix 8
A8.1. Frequency Responses from the Transfer Function

cp2 CC CD RD C C R C C C
gm1 gm2 gm3 ro1 ro2 RL [1 − ω2 ( − F D D ) + j(ω 2 C + ωCD RD + ω F )]
gm3 CF gm2 gm3CF gm2
̃ v (jω) =
A (A8-1)
1 + ω4 [C 2
2 CC CL +(cp1 +cp2 )CF (CC +CL )]CD RD ro1 ro2 RL − ω CC CD gm2 gm3 RD ro1 ro2 RL
(cp1 +cp2 )C2 CC CL CD RD ro1 ro2 RL g
+ j[ω5 − ω3 (CL + m3 CF )CC CD gm2 RD ro1 ro2 RL
gm3 gm2
+ ωCC gm2 gm3 ro1 ro2 RL ]
We define:
A0 = g m1 g m2 g m3 ro1 ro2 R L (A8-2)
A1 = g m2 ro2 (A8-3)
A2 = g m3 R L (A8-4)
C
A3 = CC (A8-5)
F
gm3
A4 = (A8-6)
gm2
ωCC
NC0 = (A8-7)
gm1
NFL = ωCF R L (A8-10)
NFr = ωCF ro2 (A8-11)

ωCF
NFg = (A8-12)
gm2
NDD = ωCD R D (A8-14)
N22 = ωC2 ro2 (A8-15)

ωC2
N23 = (A8-16)
gm3
233
Npr = ω(cp1 + cp2 )ro1 (A8-17)
ω(cp1 +cp2 )
Npg = (A8-18)
gm3
ωcp2
Np3 = (A8-19)
gm3
Using Eqs. (A8-2) to (A8-19) we can write Eq. (A8-1) as:
̃ v (jω) = 1+N N AN0[1−A

A
3 Np3 NDD −NFg NDD + j(A3 N23 +NDD +NFg ) ]
C1 22 LL NDD +Npr NFr NCL NDD +Npr NFr NLL NDD −A1 A2 NC1 NDD
+j(Npg NC1 N22 NLL NDD −A1 NC1 NLL NDD −A1 A4 NC1 NFL NDD +A0 NC0 )
Further defining:
XD = 1 + NC1 N22 NLL NDD + Npr NFr NCL NDD + Npr NFr NLL NDD − A1 A2 NC1 NDD (A8-20)
YD = Npg NC1 N22 NLL NDD − A1 NC1 NLL NDD − A1 A4 NC1 NFL NDD + A0 NC0 (A8-21)
XN = 1 − A3 Np3 NDD − NFg NDD (A8-22)
YN = A3 N23 + NDD + NFg (A8-23)
We arrive at:
̃ v (jω) = A0(XN +jYN )

A (A8-24)
X +jY
D D
2
AvdB (ω) = 20log(A0 ) + 10log(XN + YN2 ) − 10log(XD
2
+ YD2 ) (A8-25)
Y Y
Φv (ω) = 1800 + tan−1 (XN ) − tan−1 (XD ) (A8-26)
N D
234
Appendix 9

cp2 CF CC CD RD
gm1 gm2 gm3 ro1 ro2 RL [1−ω4
gm2 gmc gm3
C C 1 1 C C C C R 1 1 C C R
−ω2 { F C ( + )+ 1 C + C D D ( + )+ F D D }
C C C R 1 1 C 1 1 C
+j[−ω3 { F C D D ( + )}+ω{ C ( + )+ F +CD RD }]]
2gm2 gmc gm3 2 gmc gm3 gm2
̃ v (jω) =
A g
1+ω4 [cp1 CC CL m2 +(cp1 +cp2 )CF (CC +CL )]CD ro1 ro2 RD RL −ω2 CC CD gm2 gm3 ro1 ro2 RD RL
gmc
(cp1 +cp2 )CF CC CL CD ro1 ro2 RD RL
+j[ω5 −ω3 CF CC CD gm3 ro1 ro2 RD RL +ωCC gm2 gm3 ro1 ro2 RL ]
gmc
(A9-1)
We define:
A0 = g m1 g m2 g m3 ro1 ro2 R L (A9-2)
A1 = g m2 ro2 (A9-3)
A2 = g m3 R L (A9-4)
g
A3 = gm2 (A9-5)
mc
ωCC
NC0 = (A9-6)
gm1

ωCC 1 1
NC2 = (g +g ) (A9-8)
2 mc m3
ωCC
NC3 = (A9-9)
gm3
NFr = ωCF ro2 (A9-11)

ωCF
NFg = (A9-12)
gm2
ωC1
N1c = 2g (A9-13)
mc

235
NDD = ωCD R D (A9-15)
Np1 = ω(cp1 + cp2 )ro1 (A9-16)
Np2 = ωcp1 ro2 (A9-17)
ω(cp1 +cp2 )
Npa = (A9-18)
gmc
ωcp2
Npb = (A9-19)
gmc
̃ v (jω) = A0[1−Npb NFg1+A

A
NC3 NDD −NC2 NFg −NC2 NDD −NFg NDD −N1c NC3 + j(−NC2 NFg NDD +NC2 +NFg +NDD ) ]
3 Np2 NC1 NLL NDD +Np1 NFr NCL NDD +Np1 NFr NLL NDD −A1 A2 NC1 NDD
+j(Npa NC1 NFr NLL NDD −A2 NC1 NFr NDD +A0 NC0 )
Further defining:
XD = 1 + A3 Np2 NC1 NLL NDD + Np1 NFr NCL NDD + Np1 NFr NLL NDD − A1 A2 NC1 NDD (A9-20)
YD = Npa NC1 NFr NLL NDD − A2 NC1 NFr NDD + A0 NC0 (A9-21)
XN = 1 − Npb NFg NC3 NDD − NC2 NFg − NC2 NDD − NFg NDD − N1c NC3 (A9-22)
YN = −NC2 NFg NDD + NC2 + NFg + NDD (A9-23)
We arrive at:
̃ v (jω) = A0(XN +jYN )

A (A9-24)
X +jY
D D
2
AvdB (ω) = 20log(A0 ) + 10log(XN + YN2 ) − 10log(XD
2
+ YD2 ) (A9-25)
Y Y
Φv (ω) = 1800 + tan−1 (XN ) − tan−1 (XD ) (A9-26)
N D
236
Appendix 10

1
−gm1 gm2 gm3 r01 ro2 RL [1+ jωCC (RC − )]
̃ v (jω) =
A cp1 cp2
gm2
(1+jωCL RL )[1−ω2 (cp1 +cp2 + )CC ro1 ro2 +j(ωCc gm2 ro1 ro2 −ω3 cp1 cp2 CC r01 ro2 RC )]
CC
(A10-1)
We define:
A0 = g m1 g m2 g m3 ro1 ro2 R L (A10-2)
A12 = g m1 g m2 ro1 ro2 (A10-3)
N11 = ωcp1 ro1 (A10-4)
N22 = ωcp2 ro2 (A10-5)

cp1 cp2
N12 = ω (cp1 + cp2 + ) ro2 (A10-6)
CC
ωCC
NC0 = (A10-7)
gm1
NC1 = ωCC r01 (A10-8)
NCC = ωCC R C (A10-9)

1
NCZ = ωCC (R C − g ) (A10-11)
m2

−A0 (1 + jNCZ )
̃ v (jω) =
A (1 +jN LL )[1− N12 NC1 + j(A12 NC0 − N11 N22 NCC )]
Further defining:
XD = 1 − N12 NC1 (A10-12)
YD = A12 NC0 − N11 N22 NCC (A10-13)
237
We arrive at:
̃ v (jω) = −A0(1 + jNCZ)

A (A10-14)
(1 + jN )(X + jY
LL D D)
2 2 ) 2
AvdB (ω) = 20log(A0 ) + 10log(1 + NCZ ) − 10log(1 + NLL − 10log(XD + YD2 ) (A10-15)
and
Y
Φv (ω) = 1800 + tan−1 (NCZ ) − tan−1(NLL ) − tan−1 (XD ) (A10-16)
D
238
Appendix 11

k C −C
−gm1 gm2 r01 RL (jω 1 1 C + 1)
̃ v (jω) =
A
gm2
(A11-1)
1−ω2 (c p1 CT +CC CL )r01 RL + jωCC gm2 r01 RL
We define:
A0 = g m1 g m2 ro1 R L (A11-2)
N11 = ωcp1 ro1 (A11-3)
NC1 = ωCC r01 (A11-4)
NTL = ωCT R L (A11-6)

C
NC0 = ω g C (A11-7)
m1
k1 C 1 − C C
Nz1 = ω (A11-8)
gm2

−A0 (1+jNz1 )
̃ v (jω) =
A 1−N 11 NTL −NC1 NLL + jA0 NC0
Further defining:
XD = 1 − N11 NTL − NC1 NLL (A11-9)
YD = A0 NC0 (A11-10)
We arrive at:
̃ v (jω) = −A0(1+jNz1 )
A (A11-11)
X + jY
D D
239
2
2 )
AvdB (ω) = 20log(A0 ) + 10log(1 + Nz1 − 10log(XD + YD2 ) (A11-12)
and
Y
Φv (ω) = 1800 + tan−1 (Nz1 ) − tan−1 (XD ) (A11-13)
D
240
Appendix 12

k C −C
−gm1 gm2 gm3 ro1 ro2 RL (1+jω 2 2 D )
gm3
̃v =
A (A12-1)
1−ω2 C1 CD gm3 ro1 ro2 RL +j(ωCC gm2 gm3 ro1 ro2 RL −ω3 C1 C2 CL ro1 ro2 RL )
We define:
A0 = g m1 g m2 g m3 ro1 ro2 R L (A12-2)
A1 = g m3 R L (A12-3)
N11 = ωC1 ro1 (A12-4)
N22 = ωC2 ro2 (A12-5)
ND2 = ωCD ro2 (A12-6)

C
NC0 = ω g C (A12-8)
m1
k2 C2 −CD
Nz2 = ω (A12-9)
gm3

−A0 (1+jNz2 )
̃ v (jω) =
A 1− A 1 N11 ND2 + j(A0 NC0 − N11 N22 NLL )
Further defining:
XD = 1 − A1 N11 ND2 (A12-10)
YD = A0 NC0 − N11 N22 NLL (A12-11)
We arrive at:
̃ v (jω) = −A0(1+jNz2 )
A (A12-12)
X + jY
D D
241
We can find the magnitude AvdB (ω) in dB and phase Φv (ω) in degrees of the loop-gain with
unity feedback factor (Section 2.4.6) from Eq. (A12-12) as:
2
2 )
and
Y
Φv (ω) = 1800 + tan−1 (Nz2 ) − tan−1 (XD ) (A12-14)
D
242
Appendix 13

k C −C
−gm1 gm2 gm3 gm4 ro1 ro2 ro3 RL (1+jω 3 3 E )
̃v =
A
gm4
(A13-1)
1+ω4 C 2 CC CE CL ro1 ro2 ro3 RL −ω
2C
1 CD gm3 gm4 ro1 ro2 ro3 RL+j(ωCC gm2 gm3 gm4 ro1 ro2 ro3 RL
−ω3 C1 C2 CE gm4 ro1 ro2 ro3 RL )
We define:
A0 = g m1 g m2 g m3 g m4 ro1 ro2 ro3 R L (A13-2)
A1 = g m3 ro3 (A13-3)
A2 = g m4 R L (A13-4)
N11 = ωC1 ro1 (A13-5)
NC1 = ωCC ro1 (A13-6)
N22 = ωC2 ro2 (A13-5)
ND2 = ωCD ro2 (A13-7)
NE3 = ωCE ro3 (A13-8)

C
NC0 = ω g C (A13-10)
m1
k3 C3 −CE
Nz3 = ω (A13-11)
gm4

−A0 (1+jNz3 )
̃ v (jω) =
A 1+N C1 N22 NE3 NLL − A1 A2 N11 ND2 + j(A0 NC0 − A2 N11 N22 NE3 )
Further defining:
XD = 1 + NC1 N22 NE3 NLL − A1 A2 N11 ND2 (A13-12)
YD = A0 NC0 − A2 N11 N22 NE3 (A13-13)
We arrive at:
243
̃ v (jω) = −A0(1+jNz3)
A (A13-14)
X + jY
D D
A13.2 Plotting the Unity Feedback Factor Loop-Gain Responses
We can find the magnitude AvdB (ω) in dB and the phase Φv (ω) in degrees of the loop gain
2
2 )
and
Y
Φv (ω) = 1800 + tan−1 (Nz3 ) − tan−1 (XD ) (A13-16)
D
244
Appendix 14
We Substitute s = jω in Eq. (14-8) and re-arrange to obtain:

k C
−gm1 gm2 ro1 RL (1+jω 2 1 )
̃v =
A
gm2
(A14-1)
(1+jωC1 ro1 )(1+jωCL RL )
We define:
A0 = g m1 g m2 ro1 R L (A14-2)
N11 = ωC1 ro1 (A14-3)

k C1
Nz1 = ω g2 (A14-5)
m2
̃ v = −A0(1+jNz1 )
A (A14-6)
(1+jN )(1+jN
11 LL )
2 ) 2 ) 2 )
AvdB (ω) = 20log(A0 ) + 10log(1 + Nz1 − 10log(1 + N11 − 10log(1 + NLL (A14-7)
and
Φv (ω) = 1800 + tan−1 (Nz1 ) − tan−1(N11 ) − tan−1(NLL ) (A14-8)
245
Appendix 15

k C C k C
gm1 gm2 gm3 ro1 ro2 RL (1−ω2 3 1 2 +jω 2 1 )
gm2 gm3 gm2
̃v =
A (A15-1)
(1+jωC1 ro1 )(1+jωC2 ro2 )(1+jωCL RL )
We define:
A0 = g m1 g m2 g m3 ro1 ro2 R L (A15-2)
N11 = ωC1 ro1 (A15-3)
N22 = ωC2 ro2 (A15-4)

k C1
Nz1 = ω g2 (A15-6)
m2
k C2
Nz2 = ω k 3g (A15-7)
2 m3
̃ v = −A0(1−Nz1Nz2 +jNz1 )
A (1+jN )(1+jN )(1+jN
11 22 LL )
We further define:
XN = 1 − Nz1 Nz2 (A15-8)
YN = Nz1 (A15-9)
Then we have:
−A0 (XN +jYN )
̃v =
A (A15-10)
(1+jN )(1+jN )(1+jN
11 22 LL )
246
2
AvdB (ω) = 20log(A0 ) + 10log(XN + YN2 ) − 10log(1 + N11
2 ) 2 )
− 10log(1 + N22
2 )
−10log(1 + NLL (A15-11)
and
Y
Φv (ω) = 1800 + tan−1 (XN ) − tan−1(N11 ) − tan−1(N22 ) − tan−1(NLL ) (A15-12)
N
247
Appendix 16
We substitute s = jω in (16-10) and re-arrange to obtain:

k C C k C k C C C
−gm1 gm2 gm3 gm4 r01 ro2 ro3 RL [1−ω2 3 1 2 +j(ω 2 1 −ω3 4 1 2 3 )]
̃v =
A (A16-1)
(1+jωC1 ro1 )(1+jωC2 ro2 )(1+jωC3 ro3 )(1+jωCL RL )
We define:
A0 = g m1 g m2 g m3 ro1 ro2 R L (A16-2)
N11 = ωC1 ro1 (A16-3)
N22 = ωC2 ro2 (A16-4)
N33 = ωC3 ro3 (A16-5)

k C1
Nz1 = ω g2 (A16-7)
m2
k C2
Nz2 = ω k 3g (A16-8)
2 m3
k C3
Nz3 = ω k 4g (A16-9)
3 m4
̃ v = −A0[1−Nz1Nz2 +j(Nz1−Nz1Nz2Nz3)]
A (1+jN )(1+jN )(1+jN )(1+jN )
11 22 33 LL
We further define:
XN = 1 − Nz1 Nz2 (A16-10)
YN = Nz1 − Nz1 Nz2 Nz3 (A16-11)
Then we have:
−A0 (XN +jYN )
̃v =
A (A16-12)
(1+jN 11 )(1+jN22 )(1+jN33 )(1+jNLL )
248
with unity feedback factor (Section 2.4.6) from (A16-12) as:
2
AvdB (ω) = 20log(A0 ) + 10log(XN + YN2 ) − 10log(1 + N11
2 ) 2 )
− 10log(1 + N22
2 ) 2 )
−10log(1 + N33 − 10log(1 + NLL (A16-13)
and
Y
Φv (ω) = 1800 + tan−1 (XN ) − tan−1(N11 ) − tan−1(N22 ) − tan−1(N33 ) − tan−1(NLL )
N
(A16-14)
The loop-gain magnitude and phase responses for Eq. (16-10) can now be plotted using
249
Appendix 17 Comparison of Amplifiers
Appendix 17
Categorized Comparison of Amplifiers
Tab. A17-1. Single-Stage amplifier.
Chapter Compensation 𝐀𝟎 𝐟𝐜 𝛟𝐦 𝐆𝐦 𝐀̅ 𝐜𝐥𝟎 𝐀𝐜𝐞𝐥𝐥 𝐏𝐜𝐞𝐥𝐥

No. Type (dB) (MHz) (deg.) (dB) (dB) (𝛍𝐦𝟐 ) (𝛍𝐖)
3 Dominant pole 40 50 86.1 NA NN 35 × 35 45
Tab. A17-2. Two-Stage amplifiers.

5 type I Dominant pole 72.2 55 82 NA NN 36 × 36 255
5 type 2 Dominant pole 72.2 52 72.5 14 NN 36 × 36 255
14 Phase-lead 66 53 66.1 NA NN 49 × 50 165
Tab. A17-3. Three-Stage amplifiers.
Chapter Compensation 𝐀𝟎 𝐟𝐜 𝛟𝐦 𝐆𝐦 ̅ 𝐜𝐥𝟎

𝐀 𝐀𝐜𝐞𝐥𝐥 𝐏𝐜𝐞𝐥𝐥
6 Dominant pole 112 50.5 75 20 NN 59 × 59 255
7 Dominant pole 112 65 85 33 NN 54 × 54 285
8 Dominant pole 112 55 65 32 NN 56 × 56 225
9 Dominant pole 112 70 88 22 NN 58 × 58 255
10 Phase-lead 111 50 66.1 17.5 NN 43 × 43 150
12 Dominant pole 111 50 68.7 15 NN 54 × 55 255
15 Phase-lead 94 53 64.7 NA 24 to 60 66 × 67 180
Tab. A17-4. Four-Stage amplifiers.

13 Dominant pole 131 50 68 12 NN 72 × 73 540
16 Phase-lead 117 53 64.7 NA 16 to 100 82 × 83 210
Rest of the space in this page is left intentionally blank
250
Appendix 18 Hypothetical Process Technology Data
Appendix 18
Hypothetical Process Technology ABC
Tab. A18-1. ABC CMOS process technology data.
No. Parameter Symbol Value Units

1 Minimum feature size Lmin 110 nm
2 No. of polysilicon layers xP x=1 −
3 No. of metal layers xM x=3 −
4 Mobility-Oxide thickness product NMOS μN COX 1.00 mA/V 2
5 Mobility-Oxide thickness product PMOS μP COX 333 μA/V 2
6 Resistor (P+ poly) constant R const 200 Ω/sq.
7 Capacitor (metal-metal) constant Cconst 2.00 fF/μm2
8 Rated operating power supply voltage Vopt 1.5 V
251
Appendix 19 Units and Prefixes
Appendix 19
Units and Prefixes
Tab. A19-1. Symbols/abbreviations for units and related information.
No. Unit symbol/abbreviation Description Unit of

1 A Amperes Current
2 V Volts Voltage
3 Ω Ohms Resistance
4 F Farads Capacitance
5 S Siemens Conductance/transconductance
6 W Watts Power
7 B Bells Ratio in logarithmic scale
8 m Metres Length
9 Hz Hertz Frequency
10 rad. Radians Angle in circular measure
11 deg. or 0 Degrees Angle in 1/360-th of a complete revolution
12 sec. Seconds Time
Tab. A19-2. Symbols for unit-prefixes and related information.
No. Unit-prefix symbol Description Numerical value

1 f Femto 10−15
2 p Pico 10−12
3 n Nano 10−9
4 μ Micro 10−6
5 m Milli 10−3
7 d Deci 10−1
8 k Kilo 103
9 M Mega 106
10 G Giga 109
252
Bibliography Papers, Books, Datasheets
Bibliography
R1. Papers
[R1-1] Paul R. Gray and Robert G. Meyer, “MOS Operational Amplifier Design –– A Tutorial Overview,”
IEEE Journal of Solid-State Circuits, pp. 969-982, Vol. SC-17, No. 6, December 1982.
[R1-2] Bhupendra K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational
Amplifiers,” IEEE Journal of Solid-State Circuits, pp. 629-633, Vol. 18, No. 6, December 1983.
[R1-3] David. B. Ribner and Miles A. Copeland, “Design Techniques for Cascoded CMOS Op Amps with
Improved PSRR and Common-Mode Input Range,” IEEE Journal of Solid-State Circuits, pp. 919-925, Vol. SC-
19, No. 6, December 1984.
[R1-4] Dennis M. Monticelli, “A Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing,” IEEE
Journal of Solid-State Circuits, pp. 1026-1034, Vol. SC-21, No. 6, December 1986.
[R1-5] Fan You, Sherif H. K. Embabi and Edgar Sanchez-Sinencio, “Multistage Amplifier Topologies with
Nested Gm-C Compensation,” IEEE Journal of Solid-State Circuits, pp. 2000-2011, Vol. 32, No. 12, December
1997.
[R1-6] Ka Nang Leung and Philip K. T. Mok, “Analysis of Multistage Amplifier–Frequency Compensation,”
IEEE Transactions on Circuits and Systems I, pp. 1041-1056, Vol. 48, No. 9, September 2001.
[R1-7] Gaetano Palumbo and Salvatore Pennisi, “Design Methodology and Advances in Nested-Miller
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[R1-8] Bharath K. Thandri and Jose Siva-Martinez, “A Robust Feedforward Compensation Scheme for
Multistage Operational Transconductance Amplifiers with No Miller Capacitors,” IEEE Journal of Solid-State
Circuits, pp. 237-243, Vol. 38, No. 2, February 2003.
[R1-9] Uday Dasgupta and Yong Ping Xu, “Effects of Resistive Loading on Unity Gain Frequency of Two-
Stage CMOS Operational Amplifiers,” Proceedings of the IEEE International Symposium on Circuits and
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[R1-10] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Romani, A. Melodia and V. Melini, “A
14b 20mW 640MHz CMOS CT ΣΔ ADC with 20MHz Signal Bandwidth and 12b ENOB,” IEEE ISSCC Digest
of Technical Papers, pp. 131-140, February 2006.
[R1-11] Jae-Seung Lee, Jun Hyun Bae, Ho-Young Kim, Ji-Yong Um, Jae-Yoon Sim, and Hong June Park, “A
Design Guide of 3-stage CMOS Operational Amplifier with Nested Gm-C Frequency Compensation,” Journal
of Semiconductor Technology and Science, pp. 20-27, Vol. 7, No. 1, March 2007.
[R1-12] V. Dhanasekaran, J. Silva-Martinez and E. Sanchez-Sinencio, “A 1.2mW 1.6Vpp-Swing Class AB

16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF,” IEEE ISSCC Digest of Technical
Papers, pp. 434-435, February 2008.
[R1-13] Uday Dasgupta, “Issues in “Ahuja” Frequency Compensation Technique,” Proceedings of the IEEE
International Symposium on Radio-Frequency Integration Technology, pp. 326-329, 2009.
[R1-14] Uday Dasgupta, G.T. Ong, J.M. Cao, S.L. Chew, “A Versatile Three-stage Operational Amplifier with
Second-stage Bypass Compensation,” Proceedings of the IEEE International Symposium on Integrated Circuits,
pp. 232-235, 2014.
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Bibliography Papers, Books, Datasheets
[R1-15] Uday Dasgupta, “Low Voltage 2-Stage and 3-Stage Push-Pull Output Amplifiers in 65-nm CMOS
Technology,” Proceedings of the IEEE International Symposium on Integrated Circuits, 2016.
R2. Books
[R2-1] Benjamin C. Kuo, “Automatic Control Systems, 2nd Edition,” Copyright © 1967 Prentice Hall, Inc.
[R2-2] Jacob Millman and Christos C. Halkias, “Integrated Electronics – Analog and Digital Circuits and
Systems, International Student Edition,” McGraw-Hill Kogakusha Ltd., Copyright © 1972 McGraw-Hill, Inc.,
Library of Congress Catalog Card Number 79-172657.
[R2-3] M. E. Van Valkenburg, “Network Analysis, 3rd Edition,” Copyright © 1974 Prentice-Hall Inc.
[R2-4] J. G. Chakravorty and P. R. Ghosh, “Advanced Higher Algebra,” Copyright © 1987 Authors, U. N. Dhur
& Sons Pvt. Ltd. ISBN 81-85624-17-8.
[R2-5] Erwin Kreyszig, “Advanced Engineering Mathematics, 8th Edition,” Copyright © 1999 John Wiley &
Sons, Inc., ISBN 0-471-15496-2.
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ISBN 0-13-035568-2.
[R2-7] E. B. Vinberg, “A Course in Algebra,” Copyright © 2003 The American Mathematical Society, ISBN 0-
8218-3413-4.
[R2-8] Jerald G. Graeme, Gene E. Tobey, and Lawrence P. Huelsman, “Operational Amplifiers – Design and
Applications, International Student Edition,” McGraw-Hill Kogakusha Ltd., Copyright © 1971 Burr-Brown
Research Corporation, ISBN 07-064917-0.
[R2-9] Satoshi Sakurai and Mohammed Ismail, “Low-Voltage CMOS Operational Amplifiers – Theory, Design
and Implementation,” Copyright © 1995 Kluwer Academic Publishers, ISBN 0-7923-9507-7.
[R2-10] Rudy G. H. Eschauzier and Johan H. Huijsing, “Frequency Compensation Techniques for Low-Power
Operational Amplifiers,” Copyright © 1995 Springer Science + Business Media Dordrecht, ISBN 978-1-4419-
5154-0.
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[R2-12] Walter G. Jung, “Op Amp Applications Handbook,” Copyright © 2005 Analog Devices,
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Dissertation, Nanyang Technological University, Singapore, April 2016.
R3. Datasheets
[R3-1] RENESAS “CA3130 Datasheet,” FN817 Rev. 6.00 Aug 1, 2005, Copyright © 1998-2005 Intersil
Americas LLC.
[R3-2] Texas Instruments “LM741 Datasheet,” SNOSC25D May 1998, Revised October 2015, Copyright ©
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[R3-4] Analog Devices “OP-07 Datasheet,” Copyright © 2002-2011 Analog Devices Inc.
254
Index List of Key Terms
Index
Admittance: 17, 20, 48, 49

Amplification DC: 18
Amplification, voltage: 14
Amplifier, CMOS: 14, 102, 116
Amplifier, compensated: 15
Amplifier, conditionally stable: 14, 34, 35, 201, 214
Amplifier, embedded: 14, 15
Amplifier, feedback: 14, 28, 33
Amplifier, four-stage: 16, 166, 202
Amplifier, multistage: 1, 180, 190, 202
Amplifier, operational: 13-15
Amplifier, operational transconductance: 36
Amplifier, single-stage: 16, 36
Amplifier, three-stage: 16, 17, 75, 89, 102, 116, 132, 154, 190
Amplifier, two-stage: 16, 46, 57, 132, 143, 180
Amplifier, uncompensated: 14
Amplifier, unconditionally stable: 34, 201, 214
Analog: 13, 14
Analysis: 15, 16
Analysis, circuit: 37, repeated in the same sections of Chapters 3 to 16.
Analysis, nodal: 17
Analysis, algebraic: 22
Analysis, mathematical: 15
Approximation: 31, 32
Approximate: 22-27, 32
Bandwidth: 102, 116

Bandwidth, 3-dB: 14, 189, 201, 214
Calculations, design: 40, repeated in the same sections of Chapters 3 to 16.

Capacitance: 28
Capacitor: 31, 75, 89, 102, 116, 180, 190, 202
Capacitor, compensation: 36, 38, 75, 143, 154, 166
Capacitor, non-Miller: 214
Capacitor, Miller: 46, 180, 190, 202, 214
Cascode: 14, 57-59, 61
Circuit, integrated: 13-15, 57
Circuit, monolithic integrated: 13
Circuit, small-signal equivalent: 17, 38, repeated in the same sections of Chapters 3 to 16.
Coefficient, polynomial: 19, 23, 25, 29
Compensation, “Ahuja”: 57
Compensation, frequency: 14
Compensation, Cascode-Miller: 16, 57, 116, 118
Compensation, centre-stage-Miller: 16
Compensation, dominant pole: 14, 15, 27, 28
Compensation, Double Nested Miller: 16
Compensation, Miller: 16, 48, 75, 102, 104, 132, 143, 180, 190, 202
255
Compensation, Nested Miller: 16

Compensation, non-Miller: 16, 180, 190, 202
Compensation, phase-lead: 14, 15, 27, 29
Compensation, phase-lag: 14
Conductance: 20, 38, 39, repeated in the same sections of Chapters 3 to 16.
Current Law, Kirchoff’s (KCL): 17, 38, repeated in the same sections of Chapters 3 to 16.
Determinant, expansion, pre-conditioning: 18-21, 38, 39, repeated in the same sections of Chapters 3 to 16.
Device, Bipolar: 13, 14, 89
Device, CMOS: 13, 14, 57
Device, MOS: 15
Diagram, block: 37, repeated in the same sections of Chapters 3 to 16.
Diagram, circuit: 37, repeated in the same sections of Chapters 3 to 16.
Digital: 13, 14
Distortion, harmonic: 75
Down-scaling: 13, 14, 15, 57, 75
Element, matrix, or determinant: 19

Element, main diagonal: 79, 93
Element, anti-diagonal: 79
Equations, design: 39, repeated in the same sections of Chapters 3 to 16.
Equations, network: 38, repeated in the same sections of Chapters 3 to 16.
Equations, nodal: 17, 18
Equation, stability: 28, 30-32, 40, repeated in the same sections of Chapters 3 to 16.
Evaluation, design: 32, 41, repeated in the same sections of Chapters 3 to 16.
Expansion, determinant, cofactor: 18, 19, 21
Factor, amplification: 14
Factor, damping: 22, 66, 81, 95
Factor, feedback: 16, 30, 32, 33
Feedback: 28, 30, 32-34
Feedback, negative: 14, 15
Feedforward: 16
Formula, Vieta: 24
Frequency, gain crossover: 31, 32, 33, 34, 35
Frequency, phase crossover: 33, 34
Frequency, unity-gain: 14, 16, 26, 30, 39, repeated in the same sections of Chapters 3 to 16.
Frequency, natural: 22, 66, 81, 95
Function, decreasing: 34
Gain, closed-loop: 14, 33, 35

Gain, open-loop: 14
Gain, DC: 18, 21, 27, 39, 132, repeated in the same sections of Chapters 3 to 16.
Impedance: 45
Integration: 14
Input: 13
256
Linear: 13-15
Load, capacitive: 38, 45
Load, high-impedance: 45, 75
Load, resistive: 45
Load, on-chip: 75
Loop-gain: 16, 41, repeated in the same sections of Chapters 3 to 16.
Low-frequency: 15
Magnitude: 16, 22, 24-27, 29

Margin, gain: 30, 33
Margin, phase: 26, 28, 30, 31, 33, 143
Matrix, coefficient: 64
Mixed-signal: 13, 14
Model, MOS device or transistor: 15, 38, repeated in the same sections of Chapters 3 to 16.
Model, small-signal: 15
Multiplication, Miller: 189, 190, 201, 202, 214
Nesting: 75, 143,

Network, RC, passive: 102, 116
Operation, elementary row/column: 19

Output: 13
Output resistance: 14
Parameter, circuit: 17, 28-30, 40-42, repeated in the same sections of Chapters 3 to 16.
Parameter, device: 15
Parameter, frequency: 41, 53
Parameter, performance: 14, 40-42, repeated in the same sections of Chapters 3 to 16.
Parameter, small-signal: 15
Parameter, PZL: 27-32, 40-42, repeated in the same sections of Chapters 3 to 16.
Plot, formulae: 16
Plot, magnitude: 26, 32, 33
Plot, phase: 32
Plot, loop-gain magnitude: 32-34, repeated in the same sections of Chapters 3 to 16.
Plot, loop-gain phase: 32-34, repeated in the same sections of Chapters 3 to 16.
Pole: 14, 15, 16, 39, 45, 180, 190, 202 repeated in the same sections of Chapters 3 to 16.
Pole, dominant: 15
Pole, high-frequency far-away: 29
Pole, low-frequency far away: 29
Polynomial: 19, 21
Polynomial, bi-quadratic: 25, 80
Polynomial, cubic: 23, 24
Polynomial, higher degree: 22
Polynomial, quadratic: 21-23, 50
Power supply rejection (PSRR): 57
257
Resistance: 28, repeated in the same sections of Chapters 3 to 16.

Resistance, output: 14
Resistor: 17, 31, 46, 75, 89
Resistor, nulling: 46, 143
Response, magnitude: 16, 33
Response, phase: 16, 33
Roots, polynomial: 21, 22, 24-26
Rule, Cramer’s: 18, 38
Semiconductor: 13, 14
Signal, input 30, 33
Simulation: 15
Size, feature: 13
Specifications, design: 39, 40, repeated in the same sections of Chapters 3 to 16.
Stability: 15, 26-28, 31, 32, 34
Stable: 14, 28, 34
Stage: 14, 17
Stage, input: 36
Stage, inverting: 132
Stage, output: 16
Statistics, cell: 41, repeated in the same sections of Chapters 3 to 16.
Symbol: 16, 20
Technology, CMOS process: 13, 14, 57, 89

Terminal, inverting input: 33
Terminal non-inverting input: 33
Time-constant: 19, 20, 26
Transconductance: 14, 28, 31, 37, 38, repeated in the same sections of Chapters 3 to 16.
Transfer function: 16, 17-22, 26, 29-33, 37-39, repeated in the same sections of Chapters 3 to 16.
Transform, Laplace: 17, 18, 38, repeated in the same sections of Chapters 3 to 16.
Transistor: 13, 28, 37, repeated in the same sections of Chapters 3 to 16.
Transistor, Bipolar, NPN: 89, 91, 102, 116
Transistor, MOS: 102, 116
Variable, Laplace Transform: 18

Vector-Matrix: 18, 38, repeated in the same sections of Chapters 3 to 16.
Zero: 14, 15, 16, 21, 26-29, 31, 32, 39, 45, 180, 190, 202 repeated in the same sections of Chapters 3 to 16.
Zero, high-frequency far-away: 68
Zero, left half s-plane: 67, 80, 94, 143
Zero, right half s-plane: 67, 80, 94, 143
258
Uday Dasgupta received his B.Tech. Degree in Electronics and Communication Engineering
from Indian Institute of Technology Kharagpur, India in 1976. Thereafter, he received his
M.Eng. Degree in Microelectronics and M.Sc. Degree in Mathematics from National
University of Singapore, Singapore in 2000 and 2008 respectively.
He had been in the Electronics and IC Design industry for 42 years – in India initially and
later in Singapore – and is currently retired. He worked on discrete Bipolar circuits and
CMOS/Bi-CMOS integrated circuits in seven nationally/internationally reputed companies.
He was awarded 41 US patents and published more than 10 papers in international journals
and conferences. His interest was in high speed and low-voltage, low-power Analog
Integrated Circuit design. His current interest is in authoring technical books based on his
work experience.
ISBN 978-981-18-4087-6

Multistage CMOS Amplifiers: Analytical Case Studies in Frequency Compensation

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Multistage CMOS Amplifiers

Analytical Case Studies in Frequency Compensation

National Library Board, Singapore Cataloguing in Publication Data

To the loving memory of my parents, especially my mother who always encouraged me to

To Kalyanbrata Chakraborty, D. Litt., Indologist who inspired and encouraged me to write,

Tan Khen Sang, PhD.

Director, Institute of Microelectronics (A-STAR), Singapore.

Senior Advisor Executive Office, MediaTek Singapore Pte. Ltd.

June 2022, Singapore.

(1) I am indebted to several of my ex-colleagues as technical interaction with them played an

1.1. Blitzkrieg of Integrated Circuit Process Technology 13

Chapter 2. Relevant Mathematical Methods and Concepts 17

2.1. Obtaining the Amplifier Transfer Function 17

Chapter 3. Single-Stage Amplifier 36

3.1. Introductory Notes 36

Chapter 4. Two-Stage Amplifier with Miller Compensation 46

4.1. Introductory Notes 46

Chapter 5. Two-Stage Amplifier with Cascode-Miller Compensation 57

5.1. Introductory Notes 57

Chapter 6. Three-Stage Amplifier with Nested Miller Compensation 75

6.1. Introductory Notes 75

Chapter 7. Three-Stage Miller Compensated Amplifier with Active Feedforward

7.1. Introductory Notes 89

Chapter 8. Three-Stage Miller Compensated Amplifier with Passive Feedforward

8.1. Introductory Notes 102

Chapter 9. Three-Stage Cascode-Miller Compensated Amplifier with Passive

9.1. Introductory Notes 116

Chapter 10. Three-Stage Amplifier with Centre-Stage Miller Compensation 132

10.1. Introductory Notes 132

11.1. Introductory Notes 143

Chapter 12. Three-Stage Nested Miller Compensated Amplifier with Active

12.1. Introductory Notes 154

13.1. Introductory Notes 166

Chapter 14. Two-Stage Amplifier with Non-Miller Active Feedforward

14.1. Introductory Notes 180

Chapter 15. Three-Stage Amplifier with Non-Miller Active Feedforward

15.1. Introductory Notes 190

Chapter 16. Four-Stage Amplifier with Non-Miller Active Feedforward

16.1. Introductory Notes 202

Appendix 1. Symbols and Notations 215

A1-1. Mathematical notations 215

Appendix 2. Useful Results Pertaining to Magnitude Response 218

Appendix 3. Formulae for Plots in Chapter 3 224

A3.1. Frequency Response from the Transfer Function 224

Appendix 4. Formulae for Plots in Chapter 4 225

A4.1. Frequency Response from the Transfer Function 225

Appendix 5. Formulae for Plots in Chapter 5 227

A5.1. Frequency Response from the Transfer Function 227

Appendix 6. Formulae for Plots in Chapter 6 229

Appendix 7. Formulae for Plots in Chapter 7 231

A7.1. Frequency Response from the Transfer Function 231

Appendix 8. Formulae for Plots in Chapter 8 233

A8.1. Frequency Response from the Transfer Function 233

Appendix 9. Formulae for Plots in Chapter 9 235

A9.1. Frequency Response from the Transfer Function 235

Appendix 10. Formulae for Plots in Chapter 10 237

A10.1. Frequency Response from the Transfer Function 237

Appendix 11. Formulae for Plots in Chapter 11 239

A11.1. Frequency Response from the Transfer Function 239

Appendix 12. Formulae for Plots in Chapter 12 241

A12.1. Frequency Response from the Transfer Function 241

Appendix 13. Formulae for Plots in Chapter 13 243

A13.1. Frequency Response from the Transfer Function 243