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Ce 2766
Ce 2766
DESCRIPTION
The CE2766 is a mixed signal CMOS monolithic audio digital to analog converter. It contains six multi-bit sigma delta DAC. The system consists of 128-time interpolation filters, 4th order modulators, switch capacitors and analog www.DataSheet4U.com reconstruction filters. The one bit converter offers superior differential linearity, with no distortion due to component mis-match. high tolerance to clock jitter. The CE2766 support data conversion from 32K to 192KHz. The chip is operated at 3.3 volt to simplify the power requirement. The CE2766 is ideal for DVD player, AV receiver and set-top box application. The CE2766 support 32, 24, 20 and 16-bit input data. It also support multiple sampling frequency data. Each DAC has its own individual volume control.
CE2766
Applications
Digital Surround Sound For Home Theatre DVD Car Audio.
XCK
PLL
CE2766
Mod.
INTERPOLATION FILTER
D/A D/A D/A D/A D/A D/A
AR1 AL1 AR2 AL2 AR3 AL3
80 80 77
Mod. Mod.
LRCK BCK
77 78
Control
Interface
15
15
SDA
SCL
RST
VCM
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CE2766
DAC Performance
Item
1 2 3 4
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PERFORMANCE SPECIFICATIONS
Audio Output Level Audio Bandwidth 20Hz - 20 KHz SNR (A-weight) THD + NOISE (A-weight, 0 dB input) Dynamic Range Channel Separation Nonlinear Distortion Channel Gain Error
Spec.
1 Vrms +/- 0.1 dB >101 dB < -82 dB 90 dB < -90 dB < 0.25 dB < 0.1 dB
5 6 7 8
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CE2766
XCK REQUIREMENT
The CE2766 supports 384 and 256 times sampling clock for 32, 44.1, 48, 96 and 192K audio; 192 or 128 times for the 96 K audio.; and 96 and 64 times for the 192K audio.
XCK Requirement
Sampling Rate XCK Freq. CREG1[5:4]=[0 0] Normal XCK fs
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384*fs 12.288 MHz 16.934 Mhz 18.432 MHz 18.432 MHz 18.432 Mhz
256*fs 8.192 MHz 11.29 Mhz. 12.288 Mhz. 12.288 Mhz. 12.288 Mhz.
32 K 44.1 48 K 96 K 192 K
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CE2766
PIN ASSIGNMENT
1 2 3 4 5
28 27 26 25 24
AVDD AR1 GR1 AL1 AGND AR2 GR2 AL2 AGND AR3 GR3 AL3 VCM AVDD
CE2766
6 7 8 9 10 11 12 13 14
23 22 21 20 19 18 17 16 15
PIN DESCRIPTION
Pin Name DIGITAL DVDD XCK BCK LRCk DIN1 DIN2 DIN3 TST RSTZ N/C DGND 1 2 3 4 5 6 7 8 9 10 11 GND +3.3V I I I I I I I I/O Digital power supply, 3.3 Volt. External Master Clock Input. Audio Serial Data Clock Input. Left/Right Channel Clock pin. Please refer to Figure 1, Input data format for its definition Channel 1 or TDM Serial Audio Data Input. Channel 2 Serial Audio Data Input. Channel 3 Serial Audio Data Input. Test pin. This pin should be connected to ground. Active Low Reset Pin. Not used. can connected to ground. Digital ground Pin # Type Description
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CE2766
PIN DESCRIPTION (Continued)
Pin Name TSTOUT SDA Pin # 12 13 Type T I/O Description Tri-state output pin, This pin can be connected to ground or leave open I2C data bus. Open drain output. Externally this pin should tie to a 680 ohm pull up resistor. I2C clock input.
SCL Analog
www.DataSheet4U.com AVDD
14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Analog circuits power supply.Should be Connected to a 100 uF capacitor in parallel with a 1 uF. Analog right channel 1 output Analog circuits ground Analog left channel 1 output Analog circuits ground Analog right channel 2 output Analog circuits ground Analog left channel 2 output Analog circuits ground Analog right channel 3 output Analog circuits ground Analog right channel 3 output Common voltage De-coupling Pin Should be Connected to a 20 uF capacitor in parallel with a 1 uF. Analog circuits power supply.Should be Connected to a a 100 uF. in parallel with a 1 uF.
AR1 GR0 AL1 AGND AR2 GR1 AL2 AGND AR3 GR2 AL3 VCM AVDD
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CE2766
DIGITAL AUDIO SERIAL INTERFACE
The digital serial interface consists of 3 serial input pins, DIN1, DIN2, DIN3, and one serial clock input pin, BCK, and one left/right indicator input pin, LRCK. The data are 2s complement MSB first numbers. The CE2766 supports four resolution, which are selected programming the control register CREG0[5:4] via the I2C serial control port. Table 1 describes these four resolution.
CREG0[5:4] 00 01 10 11
1 2 3
The DIN3, DIN2 and DIN1 can be either 24-bit or 32-bit per frame as well as left justified, right justified or I2S. The CE2766 counts the number of BCK per frame to determine whether the input is 24 or 32 bits format.
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CE2766
Figure 1. Audio Serial Input Data Format
right channel
DIN[1:3] www.DataSheet4U.com
right channel
DIN[1:3]
right channel
LSB
DIN[1:3]
I S Input Format
LRCK BCK
MSB LSB MSB LSB MSB LSB
DIN[1]
3 Channel 1
data = 0
Channel 0
Last Channel
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CE2766
INFINITE ZERO DETECTION
The CE2766 has an Infinite Zero Detection circuit which detects zero in the Audio Serial Port that lasts for approximately 0.1 sec. By default, the zero detection circuit is on.
first byte
Start CA6 CA0 R/W ACK A7
second byte
A0 ACK D7
third byte
D0 ACK Stop
SDA
1 1 1 1
SCL
Example Set channel 1L volume to 30H: first byte: [CA R/W] = 6AH
( Note: Chip adrress: CA<6:0> = 35H, R/W =0.)
second byte: register address: A<7:0> = 02H third byte: data D<7:0> = 30H
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CE2766
SERIAL PORT CONTROL REGISTER ASSIGNMENT
There are 8 registers dedicated to the CE2766 for chip functional programming, The register addresses assignments are
Address (decimal) 0 1
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Default Value 80 80 80 80 80 80 80 80
Register Function Data input format, de-emphasis filter selection Input format and PLL output frequency selection Volume control for channel 1, left Volume control for channel 1, right Volume control for channel 2, left Volume control for channel 2, right Volume control for channel 3, left Volume control for channel 3, right
2 3 4 5 6 7
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CE2766
CONTROL REGISTERS DESCRIPTION Control Register 0(ADRS=hex00, default=hex80)
CREG0[7:0] ADDR[3:0] BIT 7 Hex 00 Default Value I2S 1 BIT 6 LF 0 0 BIT 5 BIT 4 BIT 3 AMUTE 0 0 BIT 2 DEEMP 0 0 BIT 1 BIT 0
NBIT[1:0]
FSMPL[1:0] 0
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[I2S, LF] Digital Serial Bus Format Select 00: - Normal or Right Justified Format. 01: -Left Justified Format. 10: - I2S Format.(default) 11: - TDM, Multi-channel Time Division Multiplexed Format NBIT[1:0]: - These two bits define the serial audio input resolution for right justified and TDM mode 00: - 16-bit resolution. (default) 01: - 20-bit resolution. 10: - 24-bit resolution. 11: - 32-bit resolution. AMUTE: - Auto-mute detection enable. 0: - Auto-mute enabled. (default) 1: - No auto-mute. DEEMP: - Enable de-emphasis 0: - Normal. (default) 1: - enable de-emphasis. FSMPL: - Interpolation filter selection. These two bits are recognized only when AUTODET bit of the CREG1 is set to 0. 00: - 44.1 or 48K sampling.(default) 01: - 44.1 or 48K sampling. 10: - 96K sampling. 11: - 192K sampling.
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CE2766
Control Register 1 (ADRS=hex01, default=hex80)
CREG1[7:0] ADDR[3:0] BIT 7 Hex 01 Default Value
AUTODET
BIT 6 FS384 0
BIT 5 CKDIV4 0
BIT 4 CKDIV2 0
BIT 3 CKdet 0
BIT 2 MUTE56 0
BIT 1 MUTE34 0
BIT 0 MUTE12 0
AUTODET Automatically detects the serial audio input data sampling rate clock frequency.
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0: - do not use auto-detect 1: - automatically detects the serial audio input data sampling rate and clock frequency.
FS384: 384 fs or 256 fs control for the PLL clock output. This bit is recognized only when AUTODET bit is set to 0
otherwise the input format is automatically detected. 0: the PLL takes the reference clock and multiplies it by 2 to generate a 512 bit clock 1: the PLL takes the reference clock and multiplies it by 4/3 to generate a 512 bit clock
CKDIV4: Clock divider enable control.This bit is recognized only when AUTODET bit is set to 0 otherwise the input
format is automatically detected. 0: do not enable input clock divided by 4 1: enable input clock divided by 4
CKDIV2: Clock divider enable control . This bit is recognized only when AUTODET bit is set to 0 otherwise the
input format is automatically detected. 0: do not enable input clock divided by 2 1: enable input clock divided by 2
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CE2766
Volume Registers for channel 1 to channel 3, (ADRS=hex02 - hex07, default=hex80)
Volume Registers ADDR[3:0] BIT 7 Hex 02 Hex 03 Hex 04 Hex 05 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Channel 1 left volume register, VOLREGL1[7:0] Channel 1 right volume register, VOLREGR1[7:0] Channel 2 left volume register, VOLREGL2[7:0] Channel 2 right volume register, VOLREGR2[7:0] Channel 3 left volume register, VOLREGL3[7:0] Channel 3 right volume register, VOLREGR3[7:0]
1 0 0 0 0 0 0 0
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Hex 07 Default Value
VOLREG:- Control the volume of the 6 DACs Volume is controlled in linear scale, with 80h corresponding to 0 dB and 01h to -42 dB. The following table showes the typical attenuation settings and their repective register values.
(dB) 0 -1 -2 -3 -4 -5 -6 -7
Attenuation
Reg. value 51 45 40 36 32 29 26 23
Attenuation
Reg. value 20 18 16 13 11 10 9 8
Attenuation
Reg. value 7 6 5 4 3 2 1 0
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CE2766
APPLICATION CONNECTION EXAMPLE:
100 uF
100 uF
5 6 7
+3.3 Volt 680 ohm I 2 C Serial Interface 13 14 8 9 RST DGND All Unmarked Capacitors have values of 0.1 uF 11 AGND 20 SDA SCL TST
CE2766
AL3 VCM
22 uF
Reset
24
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CE2766
SUGGESTED ANALOG RECONSTRUCTION FILTER
A second Sallen Key low pass reconstruction filter is recommend to remove the high frequency sigma delta modulator noise. The filters component values and characteristic are shown in the following figures.
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4.7 uF
2.7 K
10 K + 680 pF 10 K 10 K
100 K
LP F F requenc y Res pons e 5 0 -5 Amplitude (dB) -10 -15 -20 -25 -30 10
3
10
10 F req (H z .)
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CE2766
TIMING DIAGRAM Figure 3. Audio Serial Interface Timing Requirement
tbck tbck
BCK
H
tbck
tkd su
DIN[1-3]
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tkr su
LRCK
tkd hd
tkr hd
SDA, SCL
tF tR
tBF
tHD,sta
tHD,dat
tSU,dat
tSU,sta
tSU,stp
SDA
SCL
stop start start stop
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CE2766
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Vi Ai Vo
www.DataSheet4U.com Ao
Characteristics Power Supply Voltage (Measured to GND) Digital Input Applied Voltage2 Digital Input Forced Current3,4 Digital Output Applied Voltage2 Digital Output Forced Current3,4
Digital Short Circuit Duration (single output high state to Vss)
Max +7.0
Units V V
mA V mA Sec Sec
o o o o o
Analog Short Circuit Duration (single output to VSS1) Ambient Operating Temperature Range Junction Temperature (Plastic Package) Lead Soldering Temperature (10 sec., 1/4 from pin) Vapor Phase Soldering (1 minute) Storage Temperature -65 -25 -65
C C C C C
1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
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CE2766
ELECTRICAL CHARACTERISTICS
Characteristics
Min
Typ
Max
Units
Analog power supply voltage Digital power supply voltage Analog Current Digital Current
2.8 2.8
3.3 3.3 40 16
5.5 5.5
V V mA
18
mA
Audio DAC Characteristics Full Scale Output Voltage to a 10K load VVCM Reference voltage .98 1 VDD/2 1.02 Vrms V
Digital Characteristics VIH IOZH IOZL CI CO Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. Hi-Z Leakage Current, HIGH, VDD=Max, VIN=3.3 Volt Hi-Z Leakage Current, LOW, VDD=Max, VIN=VSS) Digital Input Capacitance (TA=25oC, f=1Mhz) Digital Output Capacitance (TA=25oC, f=1Mhz) 2.0 VDD 33 -10 8 10 V
A A
pF pF
BCK Cycle Time BCK Pulse Width, HIGH BCK Pulse Width, LOW Audio Data Setup Time With Respect To Rising Edge of BCK Audio Data Hold Time With Respect to Rising Edge of BCK Audio LRCK Setup Time With Respect To Rising Edge of BCK
80 30 30 10 15 10
ns ns ns ns ns ns
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CE2766
Parameter tkrhd
Characteristics Audio LRCK Hold Time With Respect To Rising Edge of BCK
Min 15
Typ
Max
Units ns
fSCL
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SCL Clock Frequency Start condition set up time Start condition hold time Stop condition set up time SCL Low time SCL High time SCL & SDA rise time SCL & SDA fall time Data set-up time Data hold time Bus Free time 250 0 4.7 4.7 4.0 4.0 4.7 4.0
100
kHz us us us us us
1.0 0.3
us us ns ns us
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CE2766
PACKAGING INFORMATION Dimensions
mm. min A A1 norm max min mm. norm max
2.13 0.05 0.22 0.09 9.90 10.20 0.3 0.25 0.38 0.20 10.50
E1 E2
5.0 7.4
5.6 8.2
b
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e
L
C
D
0.63
0.9
1.03
28-Pin (SSOP)
E1
E2
A1
e c L
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