ct © Finovex ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI AssignmontNo.2 a G1. Give difference balwoon absolula dacoding and pailiol decoding Explain advantages and disadvantages of each a > 1a Absolute dacodin Parlial decoding . b 1g uae absolute docoding all a0, |) an patlial decoding ,only the ddrass lines of $086 ara ulilized] required lings of 8086 a10 ullized in tha interfacing A in tha infarcing. > Tis also called as full decoding | 2) Itis also called as linear _| er exhauslive decoding decodin. Tee 3) Mote hardwore is required _|3)_ simple andless hardware is — Jo design daceding legic required fo design docding - OP wigher cost for docoding circuil | 6 Less cost or doreding circai 3) No multiple addrossos for 8) muliple addresses fer some “some location. 2m Aeilreney| location « Shadows «fect [6 Used in large systems ©) Usedin smal) systonis . | Absolule decoding! Advantages : a -) unique address cblainad for cach memory localion » ' ii) Enlira memory is wlilized by processor « id E “ii) Fuluro expansion can be made easily wilhoul disturbing exisling cicuilary ay Disadvantages a )) Sinco all address lines aie ulilized , decoding circuit has more hordwore , complex circuit, costing and chances of errorin hardwate connaction . ii) Foul Andingis tima consuming ii) Roquires oxla decoders and delay will be produced by Ihasa extra eNAGIRI oy. RATN © Finouex ACADEMY OF MANAGEMENT AND TECHNO! _Pailial decoding | a — Advanlages | el __\) sinco only few addioss lines ate ulilizad in decoding +« loss hardware , less complax circuit , choap and less chances ) Faull finding is easier ae Disadvantages bale gt ) multiple addioss oblaining for cach memory location => Wate Sf ioe i) Enlire memory is nol officialy ulilized by tho processor (Ail) Adding or interfacing Ic's wilh aloady oxisling circuntary iS @ dificult I 9.2. What is 60D and EVEN addioss range ofa 64 KB RAM mamery that isinlarfaced 40 808€ processor? Draw Mamery map = i —_Requited RAM momory = cuks Dividing i} into EVEN and ond bank . « RAM maomory is 32.k6 EVEN and 3a KB ODD . Hote assuming 32kKB mamory is availabla. Yo design 64 KB RAM - No.of RAM tc's required = 6UkB . o7c!s - | BDKB Arrangemon) of TC = row x col - ! odd BANK EVEN BANK | gake | 3aks ry eal RAM RAM Ai Ayan4 J FINOLEX ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI _Momory Map | fig Aig Ary Aic| oAiahaha AnMioAgha AvAcAsAy AshoAiAe| app JEVEN Suter oe os — em Ee @ 0 0 o|000 0 0000 0000 000 |h|oo00) [00000 ‘ ooo ofyy ayy ttt) it) 1) 00 fb forrer forrre pak p | 00D EVEN Bie ec Starling address | c000) | oo000 we Ending adcross | oferr | OFFFE as Wri) & _aconiro! word fo sof bil 6 of PorTc of 8255 - [the conliol word Frmal of bit sof /rosat moda is Shown as * | § 2 eb Dy De Ds Dy D3 Da D, De o| Rox ode b Ab Sle east Le bifsel fresot “BSR mode Pon'hcare pol Chil soloct 9 =raseh sab bib 6 of por C , tho bil palfarn will ba Dd) Ve Ds Bt D3 Da D Da CO Be ee A a ¢ 2 gi} salad =6 sek e = (0000 110) i = (00)y Mov AL, OD 7 auT 33,AL w as IF DMA isiniltalized in rotating priority mode and if channel ais in service , list the priority of channels fiom highest te lowest afler channel 9 sawice is complatad - ) 8257 has priority logic thal resclves simultaneous requests arriving fiom peripharals on CHo fe CH the priority logic can be programmed fo workin we modes , eilhor fixed or rotatingc LOGY. RATNAGIRI G FINotex ACADEMY OF MANAGEMENT AND TECHNO priorily mode z a : al has circular soquence » 3) Tn tolaling print iosilyof chann __3In tolaling priorily mode , priosilye r ca 3) In this, Dra channal which isjust servicad bocon fa chancafo be sarviced = ae % Thiskind of priory is useful Pall davices arch same prioslty and no davica is mora important or lass important 5) _Priotily allotment canba givenasfollows: \sl sorvice _andsenice _@rdsorvico ath service Highes. ° 2 ai— ° ) 3 ° 1 | 2 Co 1 2 G Lowest 3 an) La 3 * Thorafere, if DMA js iniliali zad in rotating pNctily moda and if chanal 2 is in service {hon tha priority of channels fan highas! fo lowest aflar channel 2 Service is completed is ~ “(nighest) CH-3 > CH-o —> cH) — > CH-2 (inwost) 6.) Whal is tha use of Tews of 8259 9 = |) 8259 programmable interrupt conlrol requires 1we types of cormmand words , Tniliglizahon command words (tow) and oparalional command werds (o¢W) 2) Tho 8959 PIC can bo initialized with 4 Tews . Arst4wo thal is ~qewl and TAN 2 are compulsory and cthor4wo thalis TON 5 and Tay are optional : TD Aon \ + Teonlains central bits foredge/\ aval iriggered mod ay i1 4 FINOLEX ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI singlo! cascade moda, call addross intarval and whothar Tey is toquited of nol ate WAG 2: Nis usad fo oblain INT lype no which is sont by 8259 ba 886 processor on tho artival of and interrupt acknowlodga pulse ha lypeno should ranga Gam 3210255 - lowar 3 bils of Tews tanging fom 000 10 11) toprosants INT no connedad lo taspactive JRo fo TRY inlorrupt + s)3ewa : as master 8259 : Il indicalos masfar fo which TRinpul, tha slave aise & connoced, I slava is connacled resp bits of Tews is sek slavo 8959 ' 31 providas abil idonlification note tha slav IW: Nis toquired if ry bil of Jew! was set « indicates wholhor g2Sg has lo opordle in SENF modo or FNM mada , uhather louse bulfored ot nan bulfaro. uso Automatic €0 o1 normal €or ) 82$9 programmabl roller is sad to expand _ hardware interrupt OF 8086 microprocessor oe ere 3) A singlo 8259 chip provides 8 hardwaro intarruplIRO -TR7, & ‘My 3) 1F tho inlowupls aia fo PEMETRMNG: Ma Sy can bo cascaded inte mastar slave configuralion using cascaded) lines, whore a slave 959 can be connactad to tad fo ach IR inpul oF mastor 4) Thus maximum 64 hardwat cascading g2S9 -— ee = k 5) As there are & alerigle Sees thare are 2 cascade linas (Aso ,CASI, casa C123: 8 a 6) Those aro oulpul & antaRtenndala sondaddioss ofslave _ on those lines . inlorrupls can be oblained by i.0, slave wads addrass on those D hose lines ara inpub for sta linas@.8 Pooket 7 gencrafion tha GOTR and upTR gives ihe starting add | What avo thavatious address gen neal mede Postot?, A v AGIRI ; ECHNOLOGY: RATN {J FINOLEX ACADEMY OF MANAGEMENT AND TECHNO! vailable i eration fochniques & 0386 processor 9 in go.age asoof tO _— Addtoss _ganeralion technique avail ciblé typos!) Segmentation , 8) Paging mochanism - Y Segmentation» Whon 80386 jatniprolaciad medal, 16 bit “sagmont ragislars aralealled as.solactors « Fer physical address doscriptar fable. « Tha upper ta bils ef solactors gives indax oFone__ of dostriplor fam desaiplor fable . tha 32 bit address fom Sal acted descriptor }s added 8 tit offsal giyan in instruction . This 3% bil physical address can bo any addross: wilhin range ofo 4 4B 3) Paging machanism : The addrass available in instruction Is called a linear address and this address is spliltad into uppor lo bits (aat—A22) @r salading lantry from" paga diractory lable” the middla to bits Cast=Als) are used to salact one of tho page Translation lable,tha lowar ja bils CAu- Ac) areused fe galect tho exact mamory location of one page fom & GB mamory - ag = eS How de wa make 80386 procagsar to anlar inla pratacled moda a i Whal foaluros ara available when 80386 is in prolactad mode? _ ) ) 20386 has 4 32 bil control togistars namad as CRO, CRI, cR2, CRB » 5) RI is tosorved ferfulura procoss , CRAA CRB ara used by ing mochanism 3) cre conlains bils That enablo and disable paging &prctedien and ils thal control the oparalionof Meating peink coprocessar 4)_oth bit or PE bil efero enables and disablas prolecled mode « Hence wacan make 36386 Procossor to enlerinte prolaced mede. by setting Lon PE bit of cro» (PE=1) Fealuras available in protactod moda! ) Complete capabililios of 80386 are unlockod whon procossor oparalas in Prolacted moda - a7 J FINOLEX ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIP 3) Prolectod modo vasily incroases the tincat addross space to 448 and allows tuning of virtual memory pragiams ofalmesh unlimilod sizo (6478) 8) Anaddilion, proloclod mode allows 80986 lo run all the existing Boe And Borgc solwaros , whilo providing sophisticalad . memory managomont and prolocion mechanism : a) Profectod modo allows tho usa ofaddilional inshuctions espao4. oplimized for suppoiling mullitasking oporaling systems Wal informahion ie stored in solacters and dascviplors of 803862 How many salectors and doscriplors ara available for 86386 processor ) 16 bid segmon! rogislors ara callad as _salaclors _Salectors 9 Gh point lo fhe base of descriplor fable s 2 esi) ©) Soloclors Tr | REL Uppor 12. bils of selaclors give dasciiplor number from dasctiplor lable « TE Cable identity) selects the descriptor fable (@DT LOT romaining bils a sod fo pass on a requested piiviledga 5) In 30386, th @So: Hrogisters, (3,SS, PS,ES, Fs 2 aS 3) ‘In 80386, hero ara ESegmant tagisters, (3,85, PS, ES, Fs & 4 “hence 8386 have 6 Soloctors 2) Pescriplors provida staring address of sagmant (Base linear adkhoss) Jt also provides and addioss of sagmant memory (limit addross is longthof sagmen}) and segment access wrilas . Each doscriplor is 8 bytes in length Bi: al foxy 8050 ond 4 TP Jo [eT tov ue] Accoss Rights pag Basa. iw eval (RPL) ly br Base Bo} us Linn to W) Those are 8192 desaiplasin Idesciplorfable suchas their is local doscriplor table &glabal doscriptor fable . tharafere, thare aie fla! te 980 dasciphahs’ auallebleiniages eam{9 rnouex ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI SMA $0gKE isin protodod modo fhon which bil decidos maximum size of physical momory thal can be interfaced to 86386 and howmuch P Gee Serre bal Nemony 7 \MB Gy Desig > Ado ise, a How much maximum memory 18 required f ‘ 1 Paging machanism 2 =>) The address available in instruction is called dlinear address and this address is spliled info upper to biks (A3I-A3) fox” Selecting lonhy from page directory fable middle lo sed fo Select one of page translalion lable and | ___ae used lo select exac memory localion of | pag 3) There ave (024 anhias in page directory fable has 32 bit information which givos address of pa fable. t * heiice Hence sizo of pagadiroctory table = 10 > Eachonty in page directory peinls te 01 honce there ate 1024 pagatranslalion tab! Page tranglalion table is of 32 biks. Hon table is 1oaq% 3abitGn. Hew many pipeline stages deos pantiu Jeny JAGIRI a J FINOLEX ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATN ~ Wana lll see page hensaion | 4) Henc3a mamory faquivad for paging cmayimium mamaji{ree aired (or pelgig Cea Mas aie ame . E mm procssor hava while performing intogar arithmatic ‘and list dhose stagos ¥ cqlar archifocure . Tt has dwo —> |) Pantium procossor have Supers: E 4 gstage pipeline fer on chip § slages inlagor pipalinas an Aloaling point unit 2 3) Ht has S stages pipalinas while performing inleg ar arithmatc as follows? PF, DI, D2, EX, WB 3) Those? pipalinas oranamed as U pipaling andY pipeline operates cninlagor data and has 5 opardlion happening al same ima Those S oporalions dra ! © PF (Proletch) = Fatchas instruction from U and V pipoline if they are simple, alse only fetches insluckon from eitha Yor V pipaline if'il is complax © 1 (vorode |)! Thasa slaga docadas tha opcoda using mictocode dochnique @ 2 (pecodos) 'Itis used to generale addresses of operands thal aro in mamety and naeds te be fetched « © © (Gacule) / Thoxecules the instruction © Wa(wiile back): Itstores exoculed results in internal rogistars ot store Ht into oxtarnal ragislers - Pipelines holp fo exacule inshudion in dneclock pulsa - _Whalis sizeand level of cache memory available in pantium processor 9 a= , RATNAGIRI © Finotex ACADEMY OF MANAGEMENT AND TECHNOLOGY, orks |) Pentium processor has 2 on chip (L) caches and also supp. | Level (13) cache 2) Thora avo 8 kB inshuction cache and sepaialod KB dala cache |___availablo on chip . They arocflavald . l © Beth caches ara two Sway sal assecalive with 128 cache lines - Size of cacheis 8ka - ca G)_Soth caches uses wrile back policy Sth ave friple ported fo | each of pipalines and ix | data by iwo inloger pi I MEST | Doser Hive f= allow simultanaous access from cep py of most fiequenlly used ipelinas and FPU - I Se a a Praw and axplain EFLAG tegisler of 80386 procasgor » __ EFLAG indicale the con dition of micro procassey Spe ils operation 3) The 086 fe 80286 hava FLAG togistarClsbit) , bub 3083 6 and Absve processors hava an EFLAG regislor ( 3 bit exdended FLAG Feacsinn) a1 3019 18 7 167 J FINOI LEX ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI fo suspond . 10 ___|_ most trusted and an opt of I js lowest ot least Husted LESH RRNA ack) Fah, a Ve ose ig aera eeN Nostod task flag anothar lask in prolacad mode operalion . This Magis sot bcc Kdusthare i SS, Seusing ere }OPL of 00 is tha highostor _ whon jog hak carent faskis nested wilhin ___task is nosted by soflware E _ 5) RF Cresumd! na Resumeflag is used wil of oxeculion affer next inshuction - 6) ym ( virtual mode) § ym Rag bil selects virtua) mode op systom. Avitual moda system allows multiple Dos momory | paililions thal are 1M byte in length to cwooxistin memory system Egsanfially, this allows system program Joexocute multiple ‘Dos programs M7 is usod fo simulate Dos in modarn windows environment |) Ac Calign mont check) « “his Mlag bit adivalosifa wordor doublaword ts addrassed on ¥ ___anenword or non doubloward boundary -Only SOu8SSX mp conlains AC bit Thal is primarily usad by ifs companion numeric , $0487 Sx for synchronization f Th dabugging fo contro) the rasumplion arafion in 4 profactad mode “coptocossar raalees IB VIF vir is copy of infarrupt Tag bil available fo the pentium (vidual o | _intowupt) pentium ~4 micro processor _- _}9)_vrP wee ~ Milwal vee providas information ‘about vistual mode interrupt for the inlerrupt pending «This is used in multitasking anvironmants “to provide operaling system with virtual intostupt lags and Inlorrupt pending information [esa Tree iftcalion) 2 Ip flags indicate that _pantium-pentium & supports cpurb inst! -3 ranourx ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI G3. Draw tha feimalot 90386 dascriplor and explain it « — > __}.4n proloctod modo, (6 bil sagmont rogislars ata called as Seloclors which salocle a dascriplor fiom a descriptor fable 3) Desuiplor canbe local descriptor or can bo global descripler €ach descriplor abl conlains gi92 doscuplars. thorarfore, there arelola) 16,384 dosctiplors « ach dasaiplor is g bylas Inlongth 1 0) Base (8. ye 10.83) ! ‘Me addross address portion of desciiplor indicates starting location _of memory sagmont- 1H dofinos addrossof sogmont within 4G8 ____physicaladdross spaca of 86386 procossol 5) Umit (Loto Lt) : A The segmont limi contains last offset addiass found inseg ment: _ Afis of 90 bils « i-a Siza of cach soqmen} is JMB - “6 Access tights : | 4 aroha 11 doterminas priviladga levels, road) write prolaction of s Accoss righ! bylo dascribes how sogmont ftinclions int Ih allows complala contro) over seqmant - ‘ DG Chranylarily bil) Soave Cis It datarminas Segment size, Segmants can! or paga granular » __3) > Cocfaull size op aralion) !~ It dolormines size of tagistors oie alse 3a biltagislers , 92 AY (available or nol, oe AY bil in 89386 aeq J FINOLEX A\ Choe OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI | syst oe Lo re ee esha Segment is available (av= Dor nF |_available Cav = 0). : j 0) hae 8 aa ; Draw only architochire of pentium pracossor grtel Tor Fo [Branch iB] codalsachy Vested ary o taste puffer # bytes L l Tass | halen] pra(ateh Buffer contol is z Tanwabeatedtar | tection deed -——A_ 8" clatabus and laigat address RI —— | sus control Unit unit rage] | he 2 ag bus cenit | | easel eae Foaling point Copiplind | (Wpipeling fe unit conhel 1 genta] 5 Trleqer register Mlle easly *, abit [oripeting | Crvrptine Lpaad] ) aalabis 64} Ba or - te =| ae | ER | aor {{ BE] talacche Pel] bo . raniliel E | LEF Shin sbyles a4 Tf ha Base address ofsogmont of 6386 procassor in protected moda js 440000001, Limif is OOFFOH -obtain thestading addross of |_-segment mamory iF 6 bite 0 and if Gbit=t- Given ! Base address = 44000000 H Umit = ooFFOH .oO FINOLEX ACADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI ) For Gbit zo - nae starting address = basa addross = 44000000 H | End address = base address tlimit 5 1 = 44000000 + ooRrO” I | 3) For Gbit=! |e Multiplying value of limit by Uk bytes. Cappending FFFH) . |__sstailing addiegs = base addrass | = 4yoo 0000 H . v a | End address = base address + limit ~ = 44000000 + CoFPOFER™ > GUFFOFFF H . GUOCOFFO 4 4 Draw the architecture diagram of $959 programmable int arruph controllor and only explain IRR andasR ragistar = A INT rN | 0-4 ANI dala bus $ N= boffer control Logie | 4 Read/ write} n priatl — [antonyp#] aes sowvicg reselvor tagistor] |] 5a dae ag cso = —>| cascade fini tas =) balfar iat Fegan wga tis modeis simple input oroulpul moda ef 8258 which allows the plogiamming of cach port aScithar inpuleraulpul mado . ii) AS Soon as 8285 racaives toad Pork A command from mp if immediately redds data fiom port A without checking whether the device (peripharal) connactod te portA has validdalate bo transferred or not this WScalled simple alo data transfer . iil) HY doos nol support handshaking or interrupt capability . iv) The inpul ports are buffered while cutpuls ava lalchad « 3) mode | ) Moda | of $258 supports handshaking with ports programmed as cither input or output port Handshaking signals are used fe Synchronize data ransfar belwean 4wo devicos that oparatos af different speed - ii) Hore port A port B can be Separataly configured asailhor input or output ports atatime . ii) Both porls ulilizes 8 linos of port C for handshqki ng signals. Rast 2 port Clines can operalaas both oifhor inpuborbealh as output pork - ‘i Nipleut! dy aa ce | wary iam lip lpa J FINOLEX A\ \CADEMY OF MANAGEMENT AND TECHNOLOGY, RATNAGIRI “y) $25 ; )_ 8955 suppoilsinlonuptiegieas well as palling loge er dala transfor - ; Y “The data al inpul oF oulpul porls are latched - | 4) mode a: In this mode, pails canbe ulilized(é1 bidiredional NowoF informalion withholp of handshaking signals - it) ‘the pins of group A con be piogammad fo acts as biditachiana dalabus and port ¢ uppor (pcy- Pca) aro used by handshaking signal. The ros! 4 lower portc bits aroulilized for 3/0 operations iil) _Peits can bo programmed in mode 0 or modal Inmode 1 tho lower bits of port c aro uséd for handshaking signals for dala hansfar by port iv) this mode is primarily usad in applicalionssuch as dalg jransfor belwoon {wo compulars or floppy disk conlrollor interface ‘ Tnlerfaco ona masta: $259 and one slayo 8259 fo 8086 processor in maximum moda using Jlo mappad_alo technique wilhan& bil even address - » 1 Mastey | slave = 28269 cascaded Ae Gi ot 8% 010 Mapped Slo as sip Ads tine 7M ies ty by W\ hol Gen Hegey 00 0.000 0/0) 00 2 Mame 954 6.0.0 ove Gail (NO; iops 0, 0 Of amma eel sla 899 o0 Joho Yo TMM gon mane = : chip selectte v a “J FINOLEX ACADEMY OF MANAGEM! y, RATNAGIRI ENT AND TECHNOLO 49, ee oor ant}