UNIT 2 COMPUTER ARTHEMATIC & DIGITAL LOGIC FUNDAMENTALS

Representation of Binary Numbers:

Binary numbers can be represented in signed and unsigned way. Unsigned binary numbers do
not have sign bit, whereas signed binary numbers uses signed bit as well or these can be
distinguishable between positive and negative numbers. A signed binary is a specific data
type of a signed variable.

1. Unsigned Numbers:
Unsigned numbers don’t have any sign, these can contain only magnitude of the number. So,
representations of unsigned binary numbers are all positive numbers only. For example,
representations of positive decimal numbers are positive by default. We always assume that
there is a positive sign symbol in front of every number.

Representation of Unsigned Binary Numbers:

Since there is no sign bit in this unsigned binary number, so N bit binary number represent its
magnitude only. Zero (0) is also unsigned number. This representation has only one zero (0),
which is always positive. Every number in unsigned number representation has only one
unique binary equivalent form, so this is unambiguous representation technique. The range of
unsigned binary number is from 0 to (2n-1).
Example-1: Represent decimal number 92 in unsigned binary number.
Simply convert it into Binary number, it contains only magnitude of the given number.
= (92)10

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= (1x26+0x25+1x24+1x23+1x22+0x21+0x20)10
= (1011100)2
It’s 7 bit binary magnitude of the decimal number 92.
Example-2: Find range of 5 bit unsigned binary numbers. Also, find minimum and
maximum value in this range.
Since, range of unsigned binary number is from 0 to (2n-1). Therefore, range of 5 bit
unsigned binary number is from 0 to (25-1) which is equal from minimum value 0 (i.e.,
00000) to maximum value 31 (i.e., 11111).
2. Signed Numbers:
Signed numbers contain sign flag, this representation distinguish positive and negative
numbers. This technique contains both sign bit and magnitude of a number. For example, in
representation of negative decimal numbers, we need to put negative symbol in front of given
decimal number.
Representation of Signed Binary Numbers:
There are three types of representations for signed binary numbers. Because of extra signed
bit, binary number zero has two representation, either positive (0) or negative (1), so
ambiguous representation. But 2’s complementation representation is unambiguous
representation because of there is no double representation of number 0. These are: Sign-
Magnitude form, 1’s complement form, and 2’s complement form which are explained as
following below.
2. (A) Sign-Magnitude form:
For n bit binary number, 1 bit is reserved for sign symbol. If the value of sign bit is 0, then
the given number will be positive, else if the value of sign bit is 1, then the given number will
be negative. Remaining (n-1) bits represent magnitude of the number. Since magnitude of
number zero (0) is always 0, so there can be two representation of number zero (0), positive
(+0) and negative (-0), which depends on value of sign bit. Hence these representations are
ambiguous generally because of two representation of number zero (0). Generally sign bit is a
most significant bit (MSB) of representation. The range of Sign-Magnitude form is from (2(n-
1)
-1) to (2(n-1)-1).
For example, range of 6 bit Sign-Magnitude form binary number is from (25-1) to (25-1)
which is equal from minimum value -31 (i.e., 1 11111) to maximum value +31 (i.e., 0
11111). And zero (0) has two representation, -0 (i.e., 1 00000) and +0 (i.e., 0 00000).
2. (B) 1’s complement form:
Since, 1’s complement of a number is obtained by inverting each bit of given number. So, we
represent positive numbers in binary form and negative numbers in 1’s complement form.
There is extra bit for sign representation. If value of sign bit is 0, then number is positive and
you can directly represent it in simple binary form, but if value of sign bit 1, then number is
negative and you have to take 1’s complement of given binary number. You can get negative
number by 1’s complement of a positive number and positive number by using 1’s
complement of a negative number. Therefore, in this representation, zero (0) can have two

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representations, that are why 1’s complement form is also ambiguous form. The range of 1’s
complement form is from (2(n-1)-1) to (2(n-1)-1) .
For example, range of 6 bit 1’s complement form binary number is from (25-1) to (25-1)
which is equal from minimum value -31 (i.e., 1 00000) to maximum value +31 (i.e., 0
11111). And zero (0) has two representation, -0 (i.e., 1 11111) and +0 (i.e., 0 00000).
2. (C) 2’s complement form:
Since, 2’s complement of a number is obtained by inverting each bit of given number plus 1
to least significant bit (LSB). So, we represent positive numbers in binary form and negative
numbers in 2’s complement form. There is extra bit for sign representation. If value of sign
bit is 0, then number is positive and you can directly represent it in simple binary form, but if
value of sign bit 1, then number is negative and you have to take 2’s complement of given
binary number. You can get negative number by 2’s complement of a positive number and
positive number by directly using simple binary representation. If value of most significant
bit (MSB) is 1, then take 2’s complement from, else not. Therefore, in this representation,
zero (0) has only one (unique) representation which is always positive. The range of 2’s
complement form is from (2(n-1)) to (2(n-1)-1).
For example, range of 6 bit 2’s complement form binary number is from (25) to (25-1) which
is equal from minimum value -32 (i.e., 1 00000) to maximum value +31 (i.e., 0 11111). And
zero (0) has two representation, -0 (i.e., 1 11111) and +0 (i.e., 0 00000).

9's Complement:
The 9's complement is used to find the subtraction of the decimal numbers. The 9's
complement of a number is calculated by subtracting each digit of the number by 9. For
example, suppose we have a number 1423, and we want to find the 9's complement of the
number. For this, we subtract each digit of the number 1423 by 9. So, the 9's complement of
the number 1423 is 9999-1423= 8576.

Subtraction using 9's complement:

With the help of the 9's complement, the process of subtraction is done in a much easier way.
Generally, we subtract the subtrahend from the minuend, but in a case when we perform
subtraction using 9's complement, there is no need to do the same. For subtracting two
numbers using 9's complement, we first have to find the 9's complement of the subtrahend
and then we will add this complement value with the minuend. There are two possible cases
when we subtract the numbers using 9's complement.ifference between JDK, JRE, and JVM

Case 1: When the subtrahend is smaller than the minuend.

For subtracting the smaller number from the larger number using 9's complement, we will
find the 9's complement of the subtrahend, and then we will add this complement value with
the minuend. By adding both these values, the result will come in the formation of carry. At
last, we will add this carry to the result obtained previously.

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Case 2: When the subtrahend is greater than the minuend:

In this case, when we add the complement value and the minuend, the result will not come in
the formation of carry. This indicates that the number is negative, and for finding the final
result, we need to find the 9's complement of the result.

10's Complement:
The 10's complement is also used to find the subtraction of the decimal numbers. The 10's
complement of a number is calculated by subtracting each digit by 9 and then adding 1 to the
result. Simply, by adding 1 to its 9's complement we can get its 10's complement value. For
example, suppose we have a number 1423, and we want to find the 10's complement of the
number. For this, we find the 9's complement of the number 1423 that is 9999-1423= 8576,
and now we will add 1 to the result. So the 10's complement of the number 1423 is
8576+1=8577.

Subtraction using 10's complement:

For subtracting two numbers using 10's complement, we first have to find the 10's
complement of the subtrahend, and then we will add this complement value with the
minuend. There are two possible cases when we subtract the numbers using 10's complement.

Case 1: When the subtrahend is smaller than the minuend.

For subtracting the smaller number from the larger number using 10's complement, we will
find the 10's complement of the subtrahend and then we will add this complement value with
the minuend. By adding both these values, the result will come in the formation of carry. We
ignore this carry and the remaining digits will be the answer.

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Case 2: When the subtrahend is greater than the minuend.

In this case, when we add the complement value and the minuend, the result will not come in
the formation of carry. This indicates that the number is negative and for finding the final
result, we need to find the 10's complement of the result obtained by adding complement
value of subtrahend and minuend.

Binary Coded Decimal, or BCD, is another process for converting decimal numbers into
their binary equivalents.
 It is a form of binary encoding where each digit in a decimal number is represented in
the form of bits.
 This encoding can be done in either 4-bit or 8-bit (usually 4-bit is preferred).
 It is a fast and efficient system that converts the decimal numbers into binary numbers
as compared to the existing binary system.
 These are generally used in digital displays where is the manipulation of data is quite a
task.
 Thus BCD plays an important role here because the manipulation is done treating each
digit as a separate single sub-circuit.
Many decimal values have an infinite place-value representation in binary but have a finite
place-value in binary-coded decimal. For example, 0.2 in binary is .001100… and in BCD
is 0.0010. It avoids fractional errors and is also used in huge financial calculations.
Consider the following truth table and focus on how these are represented.

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Truth Table for Binary Coded Decimal
DECIMAL NUMBER BCD

0 0000

1 0001

2 0010

3 0011 4 0100

5 0101 6 0110

7 0111

8 1000

9 1001

In the BCD numbering system, the given decimal number is segregated into chunks of
four bits for each decimal digit within the number. Each decimal digit is converted into its
direct binary form (usually represented in 4-bits).
For example:
1. Convert (123)10 in BCD
From the truth table above,
1 -> 0001
2 -> 0010
3 -> 0011
thus, BCD becomes -> 0001 0010 0011

Floating point representation

 In floating point representation, the computer must be able to represent the numbers
and can be operated on them in such a way that the position of the binary point is
variable and is automatically adjusted as computation proceeds, for the
accommodation of very large integers and very small fractions. In this case, the binary
point is said to be the float, and the numbers are called the floating point numbers.
 The floating point representation has three fields:
o Sign
o Significant digits and
o Exponents

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  Let us consider the number 1 1 1 1 0 1. 1 0 0 0 1 1 0 to be represent in the floating
point format.

 To represent the number in floating point format, the first binary point is shifted to the
right of the first bit and the number is multiplied by the correct scaling factor to get
the same value. The number is said to be in the normalized form.
 It is important to note that the base in the scaling factor is fixed 2.
 The string of the significant digits is commonly known as mantissa.
 In the above example, we can say that,

Sign = 0
Mantissa = 1 1 1 0 1 1 0 0 1 1 0
Exponent =5

 In floating point numbers, the bias value is added to the true exponent. This solves the
problem of representation of negative exponent.

IEEE 754 Floating-Point Standards:

Since the mantissa is always 1.xxxxxxxxx in the normalised form, no need to represent the
leading 1. So, effectively:

Precision: mantissa ===> 1 bit + 23 bits

Precision: mantissa ===> 1 bit + 52 bits

Since zero (0.0) has no leading 1, to distinguish it from others, it is given the reserved bit
pattern all 0s for the exponent so that hardware won't attach a leading 1 to it. Thus:

 Zero (0.0) = 0000...0000

 Other numbers = -1S × (1 + Mantissa) × 2E

If we number the mantissa bits from left to right m1, m2, m3,

Mantissa = m1 × 2-1 + m2 × 2-2 + m3 × 2-3 +..

Negative exponents could pose a problem in comparisons.

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For example (with two's complement):

Sign Exponent Mantissa

-1
1.0 × 2 0 11111111 0000000 00000000 00000000
1.0 × 2+1 0 00000001 0000000 00000000 00000000

With this representation, the first exponent shows a "larger" binary number, making direct
comparison more difficult.

To avoid this, Biased Notation is used for exponents.

If the real exponent of a number is X then it is represented as (X + bias)

IEEE single-precision uses a bias of 127. Therefore, an exponent of

-1 is represented as -1 + 127 = 126 = 011111102

0 is represented as 0 + 127 = 127 = 011111112
+1 is represented as +1 + 127 = 128 = 100000002
+5 is represented as +5 + 127 = 132 = 100001002

So the actual exponent is found by subtracting the bias from the stored exponent. Therefore,
given S, E, and M fields, an IEEE floating-point number has the value:

-1S × (1.0 + 0.M) × 2E-bias

(Remember: it is (1.0 + 0.M) because, with normalised form, only the fractional part of the
mantissa needs to be stored)

Digital Computers: A Digital computer can be considered as a digital system that performs
various computational tasks. The first electronic digital computer was developed in the late
1940s and was used primarily for numerical computations.
By convention, the digital computers use the binary number system, which has two digits: 0
and 1. A binary digit is called a bit.
A computer system is subdivided into two functional entities: Hardware and Software.
The hardware consists of all the electronic components and electromechanical devices that
comprise the physical entity of the device.
The software of the computer consists of the instructions and data that the computer
manipulates to perform various data-processing tasks.

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 o The Central Processing Unit (CPU) contains an arithmetic and logic unit for
manipulating data, a number of registers for storing data, and a control circuit for
fetching and executing instructions.
o The memory unit of a digital computer contains storage for instructions and data.
o The Random Access Memory (RAM) for real-time processing of the data.
o The Input-Output devices for generating inputs from the user and displaying the final
results to the user.
o The Input-Output devices connected to the computer include the keyboard, mouse,
terminals, magnetic disk drives, and other communication devices.
Logic Gates:
o The logic gates are the main structural part of a digital system.
o Logic Gates are a block of hardware that produces signals of binary 1 or 0 when input
logic requirements are satisfied.
o Each gate has a distinct graphic symbol, and its operation can be described by means
of algebraic expressions.
o The seven basic logic gates includes: AND, OR, XOR, NOT, NAND, NOR, and
XNOR.
o The relationship between the input-output binary variables for each gate can be
represented in tabular form by a truth table.
o Each gate has one or two binary input variables designated by A and B and one binary
output variable designated by x.

AND GATE:

The AND gate is an electronic circuit which gives a high output only if all its inputs are high.
The AND operation is represented by a dot (.) sign.

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OR GATE:

The OR gate is an electronic circuit which gives a high output if one or more of its inputs are
high. The operation performed by an OR gate is represented by a plus (+) sign.

NOT GATE:

The NOT gate is an electronic circuit which produces an inverted version of the input at its
output. It is also known as an Inverter.

NAND GATE:

The NOT-AND (NAND) gate which is equal to an AND gate followed by a NOT gate. The
NAND gate gives a high output if any of the inputs are low. The NAND gate is represented
by a AND gate with a small circle on the output. The small circle represents inversion.

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NOR GATE:

The NOT-OR (NOR) gate which is equal to an OR gate followed by a NOT gate. The NOR
gate gives a low output if any of the inputs are high. The NOR gate is represented by an OR
gate with a small circle on the output. The small circle represents inversion.

Exclusive-OR/ XOR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if one of its inputs is high
but not both of them. The XOR operation is represented by an encircled plus sign.

EXCLUSIVE-NOR/Equivalence GATE:

The 'Exclusive-NOR' gate is a circuit that does the inverse operation to the XOR gate. It will
give a low output if one of its inputs is high but not both of them. The small circle represents
inversion.

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Boolean algebra:

Boolean algebra can be considered as an algebra that deals with binary variables and logic
operations. Boolean algebraic variables are designated by letters such as A, B, x, and y. The
basic operations performed are AND, OR, and complement. The Boolean algebraic functions
are mostly expressed with binary variables, logic operation symbols, parentheses, and equal
sign. For a given value of variables, the Boolean function can be either 1 or 0. For instance,
consider the Boolean function:

F = x + y'z

The logic diagram for the Boolean function F = x + y'z can be represented as:
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o The Boolean function F = x + y'z is transformed from an algebraic expression into a

logic diagram composed of AND, OR, and inverter gates.
o Inverter at input 'y' generates its complement y'.

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 o There is an AND gate for the term y'z, and an OR gate is used to combine the two
terms (x and y'z).
o The variables of the function are taken to be the inputs of the circuit, and the variable
symbol of the function is taken as the output of the circuit.

The truth table for the Boolean function F = x + y'z can be represented as:

Examples of Boolean algebra simplifications using logic gates

In this section, we will look at some of the examples of Boolean algebra simplification using
Logic gates.

1. F1 = xyz'

2. F2 = x + y'z

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3. F3 = xy' + x'z
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4. F4 = x'y'z + x'yz + xy'

Truth tables for F1= xyz', F2= x+y'z, F3= xy'+x'z and F4= x'y'z+x'yz+xy'

x y z F1 F2 F3 F4

0 0 0 0 0 0 0

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0 0 1 0 1 1 1

0 1 0 0 0 0 0

0 1 1 0 0 1 1

1 0 0 0 1 1 1

1 0 1 0 1 1 1

1 1 0 1 1 0 0

1 1 1 0 1 0 0

Laws of Boolean algebra:

The basic Laws of Boolean Algebra can be stated as follows:

o Commutative Law states that the interchanging of the order of operands in a Boolean
equation does not change its result. For example:
1. OR operator → A + B = B + A
2. AND operator → A * B = B * A
o Associative Law of multiplication states that the AND operation are done on two or
more than two variables. For example:
A * (B * C) = (A * B) * C
o Distributive Law states that the multiplication of two variables and adding the result
with a variable will result in the same value as multiplication of addition of the
variable with individual variables. For example:
A + BC = (A + B) (A + C).
o Annulment law:
A.0 = 0
A+1=1
o Identity law:
A.1 = A
A+0=A
o Idempotent law:
A + A = A
A.A = A
o Complement law:
A + A' = 1
A.A'= 0
o Double negation law:
((A)')' = A
o Absorption law:
A.(A+B) = A
A + AB = A

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De Morgan's Law is also known as De Morgan's theorem, works depending on the concept of
Duality. Duality states that interchanging the operators and variables in a function, such as
replacing 0 with 1 and 1 with 0, AND operator with OR operator and OR operator with AND
operator.

De Morgan stated 2 theorems, which will help us in solving the algebraic problems in digital
electronics. The De Morgan's statements are:
1. "The negation of a conjunction is the disjunction of the negations", which means that
the complement of the product of 2 variables is equal to the sum of the compliments
of individual variables. For example, (A.B)' = A' + B'.
2. "The negation of disjunction is the conjunction of the negations", which means that
compliment of the sum of two variables is equal to the product of the complement of
each variable. For example, (A + B)' = A'B'.

Simplification using Boolean algebra

Let us consider an example of a Boolean function: AB+A (B+C) + B (B+C)

The logic diagram for the Boolean function AB+A (B+C) + B (B+C) can be represented as:

We will simplify this Boolean function on the basis of rules given by Boolean algebra.

AB + A (B+C) + B (B+C)

AB + AB + AC + BB + BC {Distributive law; A (B+C) = AB+AC, B (B+C) = BB+BC}

AB + AB + AC + B + BC {Idempotent law; BB = B}

AB + AC + B + BC {Idempotent law; AB+AB = AB}

AB + AC +B {Absorption law; B+BC = B}

B + AC {Absorption law; AB+B = B}

Hence, the simplified Boolean function will be B + AC.

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The logic diagram for Boolean function B + AC can be represented as:

Map Simplification:

The Map method involves a simple, straightforward procedure for simplifying Boolean
expressions.

Map simplification may be regarded as a pictorial arrangement of the truth table which allows
an easy interpretation for choosing the minimum number of terms needed to express the
function algebraically. The map method is also known as Karnaugh map or K-map.

Each combination of the variables in a truth table is called a mid-term.

There are four min-terms in a two variable map. Therefore, the map consists of four squares,
one for each min-term. The 0's and 1's marked for each row, and each column designates the
values of variable x and y, respectively.

Two-variable map:

Representation of functions in the two-variable map:

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Three variable map

There are eight min-terms in a three-variable map. Therefore, the map consists of eight
squares.

Three variable map:

o The map was drawn in part (b) in the above image is marked with numbers in each
row and each column to show the relationship between the squares and the three
variables.
o Any two adjacent squares in the map differ by only one variable, which is primed in
one square and unprimed in the other. For example, m5 and m7 lie in the two adjacent
squares. Variable y is primed in m5 and unprimed in m7, whereas the other two
variables are the same in both the squares.
o From the postulates of Boolean algebra, it follows that the sum of two min-terms in
adjacent squares can be simplified to a single AND term consisting of only two
literals. For example, consider the sum of two adjacent squares say m5 and m7:
m5+m7 = xy'z+xyz= xz(y'+y)= xz.
Examples of Boolean algebra simplifications using the map method

1. F(x,y,z) = Σ (2,3,4,5)

First, 1 is marked in each min-term that represents the function. Hence, 010, 011, 100, 101
are marked with 1's.

Subsequently, we have to find possible adjacent squares. These are indicated in the map by
two rectangles, each enclosing two 1's.

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The upper right rectangle represents the area enclosed by x'y.

The lower left rectangle represents the product term xy'.

The sum of these two terms gives the simplified expression:

F= x'y+ xy'

Algebraically verification:

m0+m2 = x'y'z'+ x'yz'= x'z'(y'+y) = x'z'

m4+m6 = xy'z' + xyz'= xz' + (y'+y) = xz'

2. F(x,y,z) = Σ(3,4,6,7)

As you can see, there are four squares marked with 1's, one for each min-term of the function.

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The other two adjacent squares are combined in the third column to give a two-literal term
yz.

The remaining two squares with 1's are shown in the above diagram with their values
enclosed in half rectangles. When these two half rectangles are combined, it yields two literal
term xz'.

The simplified function becomes F= yz+xz'.

Combinational Circuits:

A combinational circuit comprises of logic gates whose outputs at any time are determined
directly from the present combination of inputs without any regard to previous inputs. A
combinational circuit performs a specific information-processing operation fully specified
logically by a set of Boolean functions.

The basic components of a combinational circuit are: input variables, logic gates, and output
variables.

The 'n' input variables come from an external source whereas the 'm' output variables go to an
external destination. In many applications, the source or destinations are storage registers.

Design procedure of a Combinational Circuit

The design procedure of a combinational circuit involves the following steps:

1. The problem is stated.
2. The total number of available input variables and required output variables is
determined.
3. The input and output variables are allocated with letter symbols.
4. The exact truth table that defines the required relationships between inputs and
outputs is derived.
5. The simplified Boolean function is obtained from each output.
6. The logic diagram is drawn.

The combinational circuit that performs the addition of two bits is called a half adder and the
one that performs the addition of three bits (two significant bits and a previous carry) is a full
adder.
Half – Adder: A Half-adder circuit needs two binary inputs and two binary outputs. The
input variable shows the augend and addend bits whereas the output variable produces the

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sum and carry. We can understand the function of a half-adder by formulating a truth table.
The truth table for a half-adder is:

o 'x' and 'y' are the two inputs, and S (Sum) and C (Carry) are the two outputs.
o The Carry output is '0' unless both the inputs are 1.
o 'S' represents the least significant bit of the sum.

The simplified sum of products (SOP) expressions is:

S = x'y+xy', C = xy

The logic diagram for a half-adder circuit can be represented as:

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Full – Adder:

This circuit needs three binary inputs and two binary outputs. The truth table for a full-adder
is:

o Two of the input variable 'x' and 'y', represent the two significant bits to be added.
o The third input variable 'z', represents the carry from the previous lower significant
position.
o The outputs are designated by the symbol 'S' for sum and 'C' for carry.
o The eight rows under the input variables designate all possible combinations of 0's,
and 1's that these variables may have.
o The input-output logical relationship of the full-adder circuit may be expressed in two
Boolean functions, one for each output variable.
o Each output Boolean function can be simplified by using a unique map method.

Maps for a full-adder:

The logic diagram for a full-adder circuit can be represented as:

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Flip Flops:

Flip flops are an application of logic gates. A flip-flop circuit can remain in a binary state
indefinitely (as long as power is delivered to the circuit) until directed by an input signal to
switch states.

S-R Flip-flop/Basic Flip-Flop: S-R flip-flop stands for SET-RESET flip-flops. The SET-
RESET flip-flop neither consists of two NOR gates and also two NAND gates. These flip-
flops are also called S-R Latch. The design of these flip flops also includes two inputs, called
the SET [S] and RESET [R]. There are also two outputs, Q and Q'.

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Clocked S-R Flip-Flop
The operation of a basic flip-flop can be modified by providing an additional control input
that determines when the state of the circuit is to be changed. The limitation with a S-R flip-
flop using NOR and NAND gate is the invalid state. This problem can be overcome by using
a stable SR flip-flop that can change outputs when certain invalid states are met, regardless of
the condition of either the Set or the Reset inputs.

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A clock pulse is given to the inputs of the AND Gate. If the value of the clock pulse is '0', the
outputs of both the AND Gates remain '0'.
D Flip-Flop:

D flip-flop is a slight modification of clocked SR flip-flop.

From the above figure, you can see that the D input is connected to the S input and the
complement of the D input is connected to the R input.

When the value of CP is '1' (HIGH), the flip-flop moves to the SET state if it is '0' (LOW),
the flip-flop switches to the CLEAR state.
J-K Flip-Flop:

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J-K flip-flop can be considered as a modification of the S-R flip-flop.

The main difference is that the intermediate state is more refined and precise than that of an
S-R flip-flop.

The characteristics of inputs ‘J’ and ‘K’ are same as the 'S' and 'R' inputs of the S-R flip-flop.

J stands for SET, and 'K' stands for CLEAR. When both the inputs J and K have a HIGH
state, the flip-flop switches to the complement state, so, for a value of Q = 1, it switches to
Q=0, and for a value of Q = 0, it switches to Q=1.
T Flip-Flop: T flip-flop is a much simpler version of the J-K flip-flop.

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MCA Department
Both the J and K inputs are connected and are also called as a single input J-K Flip-flop.
Triggering of Flip-Flops. The state of the flip-flop is changed by a momentary change in the
input signal. This momentary change is known as Trigger, and the transition it causes is said
to triggering the flip-flop.

Pulses trigger clocked flip-flops:

A pulse start from the initial value of '0', goes momentarily to '1', and after a short while,
returns to its initial '0' value. A clock pulse is either positive or negative. A positive clock
source remains at '0' during the interval between pulses and goes to 1 during the occurrence
of a pulse. The pulse goes through two signal transition: from '0' to '1' and return from '1' to
'0'.

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MCA Department
Definition of clock pulse transition:

The positive transition is defined as a positive edge and the negative transition as a negative
edge.
Integrated Circuits: An integrated circuit (IC) is manufactured using silicon material and
mounted in a ceramic or plastic container (known as Chip). The basic components of an IC
consist of electronic circuits for the digital gates. The various gates are interconnected inside
an IC to form the required circuit.
Sequential Circuits:
Sequential Logic Circuits is a form of the binary circuit; its design employs one or more
inputs and one or more outputs, whose states are related to some definite rules that depend on
previous states. ... Examples of such circuits include clocks, flip-flops, bi-stables, counters,
memories, and registers.

Decoders: A Decoder can be described as a combinational circuit that converts binary

information from the 'n' coded inputs to a maximum of 2^n different outputs. The most
preferred or commonly used decoders are n-to-m decoders, where m<= 2^n. An n-to-m
decoder has n inputs and m outputs and is also referred to as an n * m decoder. The following
image shows a 3-to-8 line decoder with three input variables which are decoded into eight
outputs, each output representing one of the combinations of the three binary input variables.

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MCA Department
The three inverter gates provide the complement of the inputs corresponding to which the
eight AND gates at the output generates one binary combination for each input. The most
common application of this decoder is binary-to-octal conversion.

The truth table for a 3-to-8 line decoder can be represented as:

x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

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MCA Department
1 1 1 0 0 0 0 0 0 0 1

Let us consider an example of 2-to-4 line NAND Gate Decoder which uses NAND Gates
instead of AND gate in the central logic.

The following image shows a 2-to-4 line decoder with NAND gates.

The truth table for a 2-to-4 line decoder can be represented as:

E A1 A0 D0 D1 D2 D3

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

1 0 0 1 1 1 1

It is also possible to combine two or more decoders to form a large decoder whenever
needed. For instance, we can construct a 3 * 8 decoder by combining two 2 *4 decoders.

The following image shows a 3 * 8 decoder constructed with two 2 * 4 decoders.

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MCA Department
Encoders:

An encoder can also be described as a combinational circuit that performs the inverse
operation of a decoder. An encoder has a maximum of 2^n (or less) input lines and n output
lines. In an Encoder, the output lines generate the binary code corresponding to the input
value. The following image shows the block diagram of a 4 * 2 encoder with four input and
two output lines.

The truth table for a 4-to-2 line encoder can be represented as:

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MCA Department
A3 A2 A1 A0 D1 D0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From the truth table, we can write the Boolean function for each output as:

D1 = A3 + A2

D0 = A3 + A1

The circuit diagram for a 4-to-2 line encoder can be represented by using two input OR gates.

The most common application of an encoder is the Octal-to-Binary encoder. Octal to binary
encoder takes eight input lines and generates three output lines.

The following image shows the block diagram of an 8 * 3 line encoder.

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MCA Department
The truth table for an 8 * 3 line encoder can be represented as:

D7 D D D4 D3 D2 D1 D0 x y z
6 5

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From the truth table, we can write the Boolean function for each output as:

x = D4 + D5 + D6 + D7

y = D2 + D3 + D6 + D7

z = D1 + D3 + D5 + D7

The circuit diagram for an 8 * 3 line encoder can be represented by using two input OR gates.

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MCA Department
Multiplexers:

A Multiplexer (MUX) can be described as a combinational circuit that receives binary

information from one of the 2^n input data lines and directs it to a single output line. The
selection of a particular input data line for the output is decided on the basis of selection lines.
The multiplexer is often called as data selector since it selects only one of many data inputs.

The following image shows the block diagram of a 4 * 1 Multiplexer.

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MCA Department
Out of these four input data lines, a particular input data line will be connected to the output
based on the combination of inputs present at these two selection lines.

The function table for a 4 * 1 Multiplexer can be represented as:

S1 S0 y

0 0 I0

0 1 I1

1 0 I2

1 1 13

From the function table, we can write the Boolean function for the output (y) as:

y = S1'S0'I0 + S1' S0'I1 + S1S0'I2 + S1S0I3

The above equation for output 'y' can be implemented using inverters, three-input AND gates
and an OR gate.

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MCA Department
We can also implement higher order multiplexers using lower order multiplexers. For
instance, let us implement an 8 *1 multiplexer using two 4*1 multiplexers and a 2*1
multiplexer.

The two 4*1 multiplexers are required in the first stage to get the eight input data lines.

A 2*1 multiplexer is required in the second stage to converge the outputs generated at first
stage into a single output.

The following image shows the block diagram of an 8*1 multiplexer designed using two 4*1
multiplexers and a single 2*1 multiplexer.

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MCA Department
A set of common selection lines (S1 and S2) are applied to both of the 4*1 multiplexers.

The output generated by both of the 4*1 multiplexers is applied as inputs of the 2*1
multiplexer.

The function table for an 8*1 multiplexer can be represented as:

S2 S1 S0 y

0 0 0 10

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 17
De-Multiplexers:
A De-multiplexer (De-Mux) can be described as a combinational circuit that performs the
reverse operation of a Multiplexer.

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MCA Department
A De-multiplexer has a single input, 'n' selection lines and a maximum of 2^n outputs.

The following image shows the block diagram of a 1 * 4 De-multiplexer.

The function table for a 1 * 4 De - Multiplexer can be represented as:

S1 S0 y3 y2 y1 y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above function table, we can write the Boolean function for each output as:

y3 = S1S0 I, y2 = S1S0' I, y1 = S1' S0 I, y0 = S1'S0' I

The above equations can be implemented using inverters and three-input AND gates.

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MCA Department
We can also implement higher order De-multiplexers using lower order De-multiplexers. For
instance, let us implement a 1 * 8 De-multiplexer using 1 * 2 De-multiplexer in the first stage
followed by two 1 * 4 De-multiplexers in the second stage.

The function table for a 1 * 8 De-multiplexer can be represented as:

S2 S1 S y7 y6 y5 y4 y3 y2 y1 y0
0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0

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1 1 1 I 0 0 0 0 0 0 0

The block diagram for a 1 * 8 De-multiplexer can be represented as:

The Selection lines 'S1' and 'S0' are common for both of the 1 * 4 De-multiplexers.
Registers:
o A Register is a fast memory used to accept, store, and transfer data and instructions
that are being used immediately by the CPU.
o A Register can also be considered as a group of flip-flops with each flip-flop capable
of storing one bit of information.
o A register with n flip-flops is capable of storing binary information of n-bits.
o The flip-flops contain the binary information whereas the gates control the flow of
information, i.e. when and how the information’s are transferred into a register.
o Different types of registers are available commercially. A simple register consists of
only flip-flops with no external gates.
o The transfer of new data into a register is referred to as loading the register.

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MCA Department
 o The above figure shows a register constructed with four D-type flip-flops and a
common clock pulse-input.
o The clock pulse-input, CP, enables all flip-flops so that the information presently
available at the four inputs can be transferred into the four-bit register.
Shift – Registers:
Shift - Registers are capable of shifting their binary information in one or both directions. The
logical configuration of a Shift - Register consists of a series of flip-flops, with the output of
one flip-flop connected to the input of the next flip-flop. The following image shows the
block diagram of a Shift - Register and its configuration.

The basic configuration of a Shift - Register contains the following points:

o The most general Shift - Registers are often referred to as Bidirectional Shift
register with parallel load.
o A common clock is connected to each register in series to synchronize all operations.
o A serial input line is associated with the left-most register, and a serial output line is
associated with the right-most register.
o A control state is connected which leaves the information in the register unchanged
even though clock pulses are applied continuously.

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MCA Department