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Dtc115eka Dtc115esa Dtc115eua
Dtc115eka Dtc115esa Dtc115eua
Dtc115eka Dtc115esa Dtc115eua
circuit). R2
2) The bias resistors consist of thin-film resistors with complete GND
isolation to allow negative biasing of the input, and parasitic
IN OUT
effects are almost completely eliminated. GND
3) Only the on/off conditions need to be set for operation, making
device design easy.
4) Higher mounting densities can be achieved.
!Structure
NPN digital transistor (with built-in resistors)
0.4 0.4
0.55±0.1
1.2
0.8
(2)
(3)
(1)
(1) (2)
0.22
0.8±0.1
1.6±0.2
0.5
0~0.1
0.13
0~0.1
0.15Max. (3)
(1) IN (1) GND
0.1Min.
2.1±0.1
0~0.1
2.8±0.2
−0.1
1.6+0.2
0~0.1
(3)
(3)
0.1Min.
0.3+0.1
−0 0.15±0.05 +0.1
0.3Min.
3Min.
(15Min.)
0.45+0.15
−0.05
2.5 +0.4
−0.1 0.5 0.45 + 0.15
−0.05
5
(1) GND
ROHM : SPT (2) OUT
EIAJ : SC-72 (1) (2) (3)
(3) IN
DTC115EM / DTC115EE / DTC115EUA
Transistors DTC115EKA / DTC115ESA
!Absolute maximum ratings (Ta=25°C)
Parameter Symbol Limits Unit
Supply voltage VCC 50 V
Input voltage VI −10~+40 V
IO 20
Output current mA
IC(Max.) 100
DTC115EM / DTC115EE 150
Power DTC115EUA / DTC115EKA Pd 200 mW
dissipation
DTC115ESA 300
Junction temperature Tj 150 °C
Storage temperature Tstg −55~+150 °C