Madhav Institute of Technology and Science, Gwalior

A Govt. Aided UGC Autonomous & NAAC Accredited Institute

(Affiliated to R.G.P.V. Bhopal)

Department of Electronics Engineering

Lab Manual
VLSI Design Lab

(ELECTRONICS VII SEM / ELECTRONICS &

TELECOMMUNICATION VII SEM)
(140705/200705)
 VLSI Design Lab(140705/200705)

Course Objectives
To learn the fundamental principles of CMOS VLSI circuit design using SYMICA
EDA CAD tool.

List of Experiments:

Digital CMOS logic circuit design using SYMICA CAD tool:

1. Design and simulate the schematic of CMOS logic Gates: AND, OR, NOT.
2. Design and simulate the schematic of CMOS logic universal gates: NAND and
NOR.
3. Design and simulate the schematic of CMOS logic 2:1 MUX.
4. Design and simulate the schematic of CMOS logic 2 x 4 Decoder.
5. Design and simulate the schematic of CMOS logic Half-Adder and Full Adder.
6. Write and simulate a VHDL program for the following combinational designs:

a) 2 to 4 decoder
b) 8 to 1 multiplexer
c) 4 bit binary to gray converter

Value added experiment:

7. Write and simulate a VHDL code to describe the functions of a full adder using
three modeling styles.

Course Outcomes

After the completion of this course students will be able to:

CO1. Demonstrate a clear Understanding in hardware design language verilog and

SPICE.
CO2. Model a Combinational circuit using hardware description language verilog
and SPICE Netlist.
CO3. Model a Sequential circuit using hardware description language verilog and
SPICE Netlist.
CO4. Model a Computational circuit using hardware description language verilog
and SPICE Netlist.
CO5.Simulate and Validate the functionality of the CMOS VLSI circuits using CAD
tools.
 EXPERIMENT NO : 1

Objective: Design of basic Gates: AND, OR, NOT

AND Gate: A Boolean operatorwhich gives the value one if and only if all the operands are
one, and otherwise has a value of zero.
A circuit which produces an output signal only when signals are received simultaneously
through all input connections
Truth table:

Symbol Truth Table

B A Q

0 0 0

0 1 0

1 0 0
2-input AND Gate 1 1 1

Boolean Expression Q = A.B Read as A AND B gives Q

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of AND gate circuit click on simulation environment and do the setting according
to the fig.

We have to choose here 45nm CMOS model file for simulation.

 Result:

Symbol Generation: For making symbol of AND gate, we have to delete all the input sources from
the schematic.
 For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.

For future reference you can also save the future states.
OR Gate: a logical operation which gives the value one if at least one operand has the value
one, and otherwise gives a value of zero.
Denoting a gate circuit which produces an output if there is a signal on any of its inputs .

Symbol Truth Table

B A Q

0 0 0

0 1 1

1 0 1
2-input OR Gate
1 1 1

Boolean Expression Q = A+B Read as A OR B gives Q

Fill information in all instance according to the model that you want to use.

Simulation:
For simulation of AND gate circuit click on simulation environment and do the setting according
to the fig.

We have choose here 45nm cmos model file. For simulating OR gate circuit click on run button.
 Result:

Symbol: For making the symbol of OR gate we have to delete all input source instances from the
circuit.
For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.

For future reference you can also save the simulation states.
 NOT Gate: In digital logic, an inverteror NOT gate is a logic gate which implements logical negation.
The truth table is shown on the right.

Symbol Truth Table

A Q

0 1

1 0
Inverter or NOT Gate
Boolean Expression Q = not A or A Read as inverse of A gives Q

To design a NOT gate in Symica we have to make a new cell in the library. Procedure for this is as
follows
Library- new cell view-

Circuit Diagram:
 Fill information in all instance according to the model that you want to use.

Simulation:
For simulation of AND gate circuit click on simulation environment and do the setting according
to the fig.

We have choose here 45nm cmos model file. For simulating NOT gate circuit click on run
button.
Result:

Symbol: For making the symbol of OR gate we have to delete all input source instances from
the circuit.
For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.

For future reference you can also save the simulation states.

Viva Questions:
1. How many CMOS transistors are required to implement AND Gate?
2. What is difference between DC and Transient analysis?
3. What is pull-up and pull-up network in CMOS logic circuits?
4. State the advantages of implementing a CMOS based digital logic gate over
TTL and ECL logic gates.
 EXPERIMENT NO : 2

Objective: Design of universal gates.

NAND Gate: a Boolean operator which gives the value zero if and only if all the operands have a
value of one, and otherwise has a value of one (equivalent to NOT AND).
A circuit which produces an output signal unless there are signals on all of its inputs .

Symbol Truth Table

B A Q

0 0 1

0 1 1

1 0 1

2-input NAND Gate 1 1 0

Boolean Expression Q = A.B Read as A AND B gives NOT Q

To design a NAND gate in Symica we have to make a new cell in the library. Procedure for this is
as follows

Library- new cell view-

Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of NAND gate circuit click on simulation environment and do the setting
according to the fig.

We have choose here 45nm cmos model file. For simulating and gate circuit click on run button.
Result:

Symbol: For making the symbol of NAND gate we have to delete all input source instances from
the circuit.
For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.

For future reference you can also save the simulation states.
 NOR Gate: a Boolean operator which gives the value one if and only if all operands have a value
of zero and otherwise has a value of zero.
A circuit which produces an output signal only when there are no signals on any of the input
connections.

Symbol Truth Table

B A Q

0 0 1

0 1 0

1 0 0
2-input NOR Gate 1 1 0

Boolean Expression Q = A+B Read as A OR B gives NOT Q

To design a NOR gate in Symica we have to make a new cell in the library. Procedure for this is as
follows
Library- new cell view-
Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of NOR gate circuit click on simulation environment and do the setting according
to the fig.

We have choose here 45nm cmos model file. For simulating NOR gate circuit click on run
button.
Result:

Symbol: For making the symbol of NOR gate we have to delete all input source instances from
the circuit.
For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.

For future reference you can also save the simulation states.

Viva Questions:
1. How many CMOS transistors are required to implement NOR Gate?
2. What is difference between AC and .OP analysis?
3. How to make symbol library in Symica EDA tool?
4. What is SPICE simulation?
 EXPERIMENT NO : 3

Objective: Design of 2:1 Mux using other basic gates

Theory: Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds and as
such, the device we use to do just that is called a Multiplexer.
Symbol

To design a 2to1 MUX in Symica we have to make a new cell in the library. Procedure for this is
as follows

Library- new cell view-

Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of 2to1 Mux circuit click on simulation environment and do the setting according
to the fig.

We have choose here 45nm cmos model file. For simulating 2to1 Mux circuit click on run
button.
 Result:

Symbol: For making the symbol of 2to1 Mux we have to delete all input source instances from
the circuit

For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.

.
For future reference you can also save the simulation states.

Viva Questions:
1. How many CMOS transistors are required to implement 2:1 MUX?
2. How we can implement 8:1 MUX using 2:1 MUX symbol stored in the
SYMICA EDA Library?
3. What is the importance of CMOS 45nm model file used in this
experiment?
 EXPERIMENT NO : 4

Objective: Design of 2x4 Decoder using other basic gates

Theory: A decoder is a circuit that changes a code into a set of signals. It is called a decoder
because it does the reverse of encoding, but we will begin our study of encoders and decoders
with decoders because they are simpler to design.
Symbol

To design a 2to4 Decoder in Symica we have to make a new cell in the library. Procedure for
this is as follows
Library- new cell view-
Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of 2to4 Decoder circuit click on simulation environment and do the setting
according to the fig.

We have choose here 45nm cmos model file. For simulating 2to4 Decoder circuit click on run
button.

2
Result:

Symbol: For making the symbol of 2to4 Decoder we have to delete all input source instances
from the circuit.

3
For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.

For future reference you can also save the simulation states.

Viva Questions:
1. How many CMOS transistors are required to implement 2x4 Decoder?
2. How many AND and NOT gate are required to implement 2x4 Decoder?
3. How to set the environment variables in the symica EDA tool?
 EXPERIMENT NO : 5

Objective: Design of Half-Adder and Full Adder.

Half-Adder: The half adder is an example of a simple, functional digital circuit built from two
logic gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two
bits (S) and the carry (C). Note how the same two inputs are directed to two different gates.
Truth table:

To design a Half Adder in Symica we have to make a new cell in the library. Procedure for this is
as follows
Library- new cell view-
Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of Half Adder circuit click on simulation environment and do the setting
according to the fig.

We have choose here 45nm cmos model file. For simulating Half Adder circuit click on run
button.
Result:

Symbol: For making the symbol of Half Adder we have to delete all input source instances from
the circuit.

For saving it as a symbol right click on cell name schematic and choose new cell view from and
then save it.
For future reference you can also save the simulation states.
Full Adder: The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two
one-bit binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a
cascade of adders, which add 8, 16, 32, etc. binary numbers.

To design Full Adder in Symica we have to make a new cell in the library. Procedure for this is as
follows

Library- new cell view-

Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of Full Adder circuit click on simulation environment and do the setting
according to the fig.

We have choose here 45nm cmos model file. For simulating Full Adder circuit click on run
button.
Result:

For future reference you can also save the simulation states.
Viva Questions:
1. How many CMOS transistors are required to implement full adder?
2. How many logic gates are required to implement full adder?
3. How to implement full adder using two half adder symbols in SYMICA EDA?
 EXPERIMENT NO : 6

Objective: Design of Half-Substractor and Full Substractor.

Half Subtractor: The half Subtractor is a combinational circuit which is used to perform
subtraction of two bits. It has two inputs, the minuend and subtrahend and two outputs the
difference and borrow out.
Truth Table:

To design a Half Subtractor in Symica we have to make a new cell in the library. Procedure for
this is as follows

Library- new cell view-

Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of Half Subtractor circuit click on simulation environment and do the setting
according to the fig.

We have choose here 45nm cmos model file. For simulating Half Subtractor circuit click on run
button.
Result:

For future reference you can also save the simulation states.
Full Subtractor: The full Subtractor is a combinational circuit which is used to perform subtraction
of three input bits: the minuend, subtrahend, and borrow in. The full Subtractor generates two
output bits: the difference and borrow out is set when the previous digit borrowed from.
Truth Table:

To design a Full Subtractor in Symica we have to make a new cell in the library. Procedure for
this is as follows
Library- new cell view-
Circuit Diagram:

Fill information in all instance according to the model that you want to use.
Simulation:
For simulation of Full Subtractor circuit click on simulation environment and do the setting
according to the fig.

We have choose here 45nm cmos model file. For simulating Full Subtractor circuit click on run
button.
Result:

For future reference you can also save the simulation states.
Viva Questions:
1. How many CMOS transistors are required to implement full substractor?
2. How many logic gates are required to implement full substractor?
3. How to implement full substractor using two half substractor symbols in
SYMICA EDA?