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LAB MANUAL OF ELECTRONICS-1 LAB

Name-PRIYAM JAIN

Enroll.No-0901EC191088

Subject-ELECTRONICS 1 LAB

Submitted to – Shri Gajanan Pophli Sir

Session-july-dec 2020

Branch- EC II YR. III SEM

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SR. EXPERIMENTS DATE

NO
Implementation of Half wave rectifier and 1/12/20
1. calculation of
(i) DC Value
(ii) RMS Value
(iii) Percentage Conduction
Implementation of Full wave rectifier and 2/12/20
2. calculation of
(i)RMS Value (ii) DC Value
(iii)Percentage conduction

Implementation of Clipper & Clamper 2/12/20

3. Circuit on bread board & observation of
output on
CRO.
To Study the V-I Characteristics of PN 3/12/20
4. junction diode.

To Study the V-I Characteristics of Zener 4/12/20

5. diode.
To verify V-I Characteristics of BJT in CB, 4/12/20
6. CE, CC Configuration

To verify the V-I Characteristics of FET. 5/12/20

7.
To verify the V-I Characteristics of 6/12/20
8. enhancement / depletion mode MOSFET

To design LC Oscillator 6/12/20

9.
To design RC Oscillator 7/12/20
10.
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EXPERIMENT NO. 1
Aim: Implementation of Half wave rectifier and calculation of
(i) DC Value
(ii) RMS Value
(iii) Percentage Conduction

Component/Equipment Required:
Step down transformer (nearly 20:1), 2 Resistance of 1K, Diode 1N4007(SI), CRO/DSO,
BNC Cable, Power cord. Bread-board, connecting wires. Signal generator and Power supply:

Theory & Design:

A half wave rectifier makes use of single diode to carry out this conversion. It is named
so as the conversion occurs for half input signal cycle. During the positive half eycle, the
diode is forward biased and it conducts and hence a current flows through the load resistor.
During the negative half cycle, the diode is reverse biased and it is equivalent to an open
circuit, hetice the current through the load resistance is zero. Thus the diode conducts only for
one half cycle and results in a half wave rectified output.

Average-Value: X avg = 1/T integration 0-t x(t)dt

RMS Value X rms =1/T integration 0-t x^2(t)dt

Ripple Factor:
Ripple factor is defined as the ratio of the effective value of AC components to the
average DC value. It is denoted by the symbol y'. For HWR it has the value 0.48.
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Circuit Diagram:

Procedure:
1. Connect the circuit as shown in the figure

2. Connect the multimeter across the lond.

3. Measure the AC and DC voltages by setting multi-meter to ac and do mode respectively.

4 Now calculate the ripple factor using the following formula.

5. Connect the CRO channel-1 across input and channel-2 across output ie lead and
observe the input and output Waveforms.
6. Now calculate the peak voltage of input and output waveforms and also the frequency.

Waveform:

Observation: Input at secondary winding of Transformer

1.Peak value of Output Signal: 16.2 V
2. RMS: 8.1 V
 DC Average) Value: 5.15 V
4. Frequency of Output Signal: 49.2 Hz
5. Conduction Angle: 175,75
6. Conduction %- 175,75/360 -48.82 %

Conclusion:
(1) DC value improves from 0 to V
(2) Percentage conduction of diode is less than 50 %

Precautions:
(1) Always check to see that the power switch is OFF before plugging into the outlet.
Also, tum instrument or equipment OFF before unplugging from the outlet
(2) When disassembling a circuit, first remove the source of power.

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EXPERIMENT NO. 2
Aim: Implementation of Full wave rectifier and calculation of
(i)RMS Value (ii) DC Value (iii)Percentage conduction

Component/Equipment Required:
Centre tap step down transformer (nearly 10:1), 1 Resistance of IKA, 2 Diodes IN4007(Si).
CRO/DSO, BNC Cable, Power cord, Bread-board, connecting wires, Signal generator and
Power supply.

Theory & Design

A full wave rectifier makes use of a two diodes to carry out this conversion. It is named
so as the conversion occurs for complete input signal cycle. The full-wave rectifier consists
of a centre-tap transformer, which results in equal voltages above and below the centre-tap.
Duringthe positive half cycle, a positive voltage appears at the anode of D, while a negative
voltageappears at the anode of LED. Due to this diode D, is forward biased it results in a
current le through the load R. During the negative half cycle, a positive voltage appears at the
anode of Dand hence it is forward biased. Resulting in a current le through the load at the
same instant a negative voltage appears at the anode of D, thus reverse biasing it and hence it
doesn't conduct.

Average-Value: Xavg = 1/Tintegration 0-t x(t)dt

RMS Value Xrms =1/Tintegration 0-t x^2(t)dt

Ripple Factor: .

Ripple factor is defined as the ratio of the effective value of AC

components to theaverage DC value. It is denoted by the symbol y’’
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Circuit Diagram

Procedure:

1. Connect the circuit as shown in the figure,

2. Connect the multi-meter across the Ika load.

3. Measure the AC and DC voltages by setting multi-meter to ac and de mode respectively.

4. Now calculate the ripple factor using the following formula.

5. Connect the CRO channel-1 across input and channel-2 across output i.e load and

Observe the input and output Waveforms.

6. Now calculate the peak voltage of input and output waveforms and also the frequency

Waveform:
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Observation:
Input at secondary winding of Transformer
1. Peak value of Output Signal: 16.2 V
2. RMS: 11.45 V
3. DC(Average) Value: 10.31 V
4. Frequency of Output Signal: 98.4 Hz
5. Conduction Angle: 175.75
6. Conduction % = 175.75/ 180 -97.63 %

Conclusion:
(1) DC value improves from 0 to 2V.
(2) Percentage conduction of diode is improved compared to half wave rectifier.

Precautions:
1. Connections should be tight
2. Always check whether power switch is OFF before plugging into the outlet. Also,
turn instrument or equipment OFF before unplugging from the outlet,
3. When disassembling a circuit, first remove the source of power.
4. When testing a diode, ensure that the test voltage did not exceed the diode's maximum
allowable voltag

Experiment-3
Aim: Implementation of Clipper & Clamper Circuit on bread board & observation of output on
CRO.
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Components/Equipment Required

o Function generator
o Power supply
o Diode: IN4001
o Resistance: 1KA
o Capacitor: 10uF
o oscilloscope

Theory& Design:
A wave shaping circuit which controls the shape of out waveform by removing or
clipping a portion of the applied wave is known as clipping circuit. For a clipping circuit at least
two components of a diode(which acts as a closed switch when forward-biased and an open
circuit when reverse biased) and a resistor are required. Sometimes a de battery is also used to fix
the clipping level. The important diode clippers are:
1. Positive clipper
2. Negative clipper
3. Combination clipper
When observing the circuits, one can see the clipping function will occur. Clipping entails that
the ends of the waveform become cutoff "clipped". There are several different cases that are
explored in this experiment with respect to clipping. A case of clipping would occur in the
forward active region. For example, diode's voltage threshold value is 0.7V. If one were to apply
it across the diode, the clipping would occur at 0.7V since that is its threshold voltage. By adding
a battery, the threshold is raised. Adding a IV battery next to the diode will now create a total
threshold voltage of 1.7V. Applying anything greater than 1.7V as an input would cause a
clipping at 1.7 V.Anything less than that threshold value will pass right through, thus resulting in
no clipping occurring.

Procedure:
1. Check the components using multimeter
2. Setup the respective clipper circuit
3. Apply the sine wave input to the circuit
4. Simultaneously observe the input and output waveforms on CRO and measures the peak
voltage of the output waveform.
5. Repeat the above steps for all clipper circuits.
6. Plot the
waveforms.

Circuits & Waveform:

1. Positive Clipper:

The clipper which removes the positive half cycle of the input voltage is known as positive
clipper. As shown in the figure below, the diode is kept in series with the resistance. During the
positive half cycle of the input waveform, the diode 'D' is reverse biased, which maintains the
output voltage at 0 Volts. This causes the positive half cycle to be clipped off. During the
negative half cycle of the input, the diode is forward biased and so the negative half cycle
appears across the output. Therefore,

Fig. 1 Circuit arrangement, input waveform and output waveform

2. Biased Positive Clipper:

A biased positive clipper is used when it is desired to remove small portion of positive cycle of a
signal voltage
(a). In a biased clipper, when the input signal voltage is positive, the diode D is reverse biased.
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This causes it to act as an open-switch. Thus, the entire positive half cycle appears across the
load, as illustrated by output waveform.
(b). When the input signal voltage is negative but does not exceed battery the voltage V', the
diode D' remains reverse-biased and most of the input voltage appears across the output.
When during the negative half cycle of input signal, the signal voltage becomes more
than the battery voltage V, the diode D is forward biased and so conducts heavily. The output
voltage is equal to - V and stays at - V' as long as the magnitude of the input signal voltage is
greater than the magnitude of the battery voltage, V". Thus, a biased negative clipper removes
input voltage when the input signal voltage becomes greater than the battery voltage.
Vo = -V1… ............................... Vinput >= Vbattery
Vo = Vi ........................... otherwise

Fig.2 Circuit arrangement,input waveform and output waveform

3. Negative Clipper:
The clipper which removes the negative half cycle of the input voltage is known as negativeclipper. The negative
clipping circuit is almost the same as the positive clipping circuit, with only one difference. If the diode is
reconnected with reversed polarity. Therefore,
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Fig 3.Circuit arrangement, input waveform and output waveform

4. Biased Negative Clipper:

A biased clipper is used when it is desired to remove small portion of negative cycle of a signal
voltage.

Fig.4.Circuit arrangement. input waveform and output waveform

5. Combination Clipper:
A Combined circuit of biased positive and negative clipper is known as combination
clipper.
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Fig.5. Circuit arrangement, input waveform and output waveform

The action of the circuit is summarized below.
(a) For positive input voltage signal when input voltage exceeds battery voltage + V2.diode DI
conducts heavily while diode D2 is reversed biased and so voltage + V2' appears across the
output. This output voltage + V2'stays as long as the input signal voltage exceeds + V2'. The
output for the given case is shown in Fig 6

Vout = V2............... n>=V2

(b) For the negative input voltage signal, the diode DI' remains reverse biased and diode
D2 conducts heavily only when input voltage exceeds battery voltage V3' in magnitude. Thus,
during the negative half cycle the output stays at - V3'so long as the input signal voltage is
greater than -V3. The output for the given case is shown in Fig 7.
Vout = -V3..……Vin >= -V3

(c) For the input voltage is in between two battery voltages where input voltage is greater than
battery voltage V, and less than the battery voltage V, then, diode DI & D2 remains reverse
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biased therefore, the output voltage is equal to the input voltage. The output for the given case is
shown in fig.8
Vout = Vin ....... 3 <Vin<V2

Result:
The clipper circuit design output waveforms have been studied and the required parameters has
been compared

Precautions:
1. Check bread board whether the connections are shorted vertically or horizontally,
2. Check each and every component via multimeter.
3. Power supply, function generator and CRO should work properly before use.
4. Set the CRO output channel in DC mode always.
5. Observe the waveform simultaneously in two channels by keeping the same reference
ground.
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Experiment-4

Aim: To Study the V-I Characteristics of PN junction diode.

Component/Equipment Required:
I Diodes IN4007(Si), IK resistance, Power cord, Bread-board, connecting wires, Power
supply and DMM.

Theory & Design:

If the external voltage applied on the silicon diode is less than 0.7 volts, the silicon diode
allows only a small electric current. However, this small electric current is considered as
negligible. When the external voltage applied on the silicon diode reaches 0.7 volts, the p-n
junction diode starts allowing large electric current through it. At this point, a small increase
in voltage increases the electric current rapidly. The forward voltage at which the silicon
diode starts allowing large electric current is called cut-in voltage. The cut-in voltage for
silicon diode is approximately 0.7 volts.

If the external reverse voltage applied on the p-n junction diode is increased, the free
electrons from the n-type semiconductor and the holes from the p-type semiconductor are
moved away from the p-n junction. This increases the width of depletion region.
The wide depletion region of reverse biased p-n junction diode completely blocks the
majority charge carrier current. However, it allows the minority charge carrier current. The
free electrons (minority carriers) in the p-type semiconductor and the holes (minority carriers)
in the n-type semiconductor carry the electric current. The electric current, which is carried
by the minority charge carriers in the p-n junction diode, is called reverse current.
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Fig .v-I characteristics of Si diode

Circuit Diagram:

Fig. Diode Circuit

Procedure:
1. Connect the circuit as shown in the figure.
2. Connect the one multi-meter across the diode to measure the diode voltage.
3. Connect second multi-meter between diode and resistor to measure the current (set in mA
for forward current and A for reverse current).
 4. Vary the voltage from power supply and note down the voltage and current reading of
multi-meter
5. Now plot the VI characteristic.

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Observation Table:

Sr.No Voltage Current

1. -5v 0.68mA
2. -3v 0.67mA
3. -1v 0.67mA
4. 0v 0mA
5. 0.18v 12.8mA
6. 0.25v 41.3mA
7. 0.30v 92.27mA
8. 0.365v 0.234mA
9. 0.4v 0.4mA
10. 0.421v 0.57mA
11. 0.482v 1.52mA
12. 0.512v 2.41mA
13. 0.533v 3.41mA

Conclusion
1. Forward Cut-in Voltage of the diode is- V.
2. For forward bias, above cut in voltage current increases exponentially with voltage.
3. For reverse bias current remains almost constant and very small.

Precautions:
1. While doing the experiment do not exceed the readings of the diode. This may lead to
damaging of the diode.
2. Connect voltmeter and ammeter in correct polarities as shown in the circuit diagram
3. Do not switch ON the power supply unless you have checked the circuit connections as
per the circuit diagram
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Experiment-5
Aim: To verify V-I Characteristics of Zener Diode.

Component/Equipment Required:
1 Diodes 1N44728A, 1K resistance, Power cord, Bread-board, connecting wires, Power
supply, DMM

Theory & Design:

If the external voltage applied on the silicon diode is less than 0.7 volts, the silicon diode
allows only a small electric current. However, this small electric current is considered as
negligible. When the external voltage applied on the silicon diode reaches 0.7 volts, the p-n
junction diode starts allowing large electric current through it. At this point, a small increase
in voltage increases the electric current rapidly. The forward voltage at which the silicon
diode starts allowing large electric current is called cut-in voltage. The cut-in voltage for
silicon diode is approximately 0.7 volts.
When reverse biased voltage is applied to a zener diode, it allows only a small amount of
leakage current until the voltage is less than zener voltage. When reverse biased voltage
applied to the zener diode reaches zener voltage. it starts allowing large amount of electric
rapidly increases the electric current. At this point, a small increase in reverse voltage clectric
current. Because of this sudden rise in electric current breakdown occurs called zener
breakdown. However, zener diode exhibits a controlled breakdown that does damage the
device.
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Circuit Diagram:

Fig.Zener Diode Circuit

Procedure:
1. Connect the circuit as shown in the figure.
2. Connect the one multi-meter across the diode to measure the diode voltage
3. Connect second multi-meter between diode and resistor to measure the current (set in mA
for forward current and A for reverse current)
4. Vary the voltage from power supply and note down the voltage and current reading of
multi-meters.
5. Now plot the VI characteristic.
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Observation-Table:
Sr.No Voltage(Vz) Current(Iz)(mA)
1. -1.0 0
2. -2.0 0
3. -2.5 0 Reverse
4. -3.0 -3.98 Characteristics
5. -3.11 -385
6. -3.16 -1840
7. -3.18 -3820
8. 0.2 0
9. 0.4 0
10. 0.59 5,69 Forward
11. 0.65 49.64 Characteristics
12. 0.67 125.59
13. 0.69 302.72

Waveform:-
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Conclusion:
1. For forward bias, above cut in voltage current increases exponentially with voltage.
2. For reverse bias current remains almost constant and very small. Once Voltage exceed
Zener breakdown voltage, current increases rapidly.

Precautions:
1. While doing the experiment do not exceed the readings of the diode. This may lead to
damaging of the diode.
2. Connect voltmeter and ammeter correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections
as per the circuit diagram.
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E
Experiment-

Aim: To verify V-II Characteristics of BJT in CB, CE, CC Configuration.

Component/Equipment Req
Required:
I BC547B, 50K & 1K resistance Power cord, Bread
Bread-board,
board, connecting wires, Power supply.
2 DMM.

(A) Common Emitter Configuration

Theory & Design:
In common emitter (CE) configuration, the input current (Tu) is produced in the base region
which is lightly doped and has small width. So the base region produces only a small input
current (In). On the other hand, in common base (CB) configuration, the input current (IL) is
produced in the emitter region which is heavily doped and has large width. So th
thee emitter
region produces a large input current (I). Therefore, the input current (Ib) common emitter (CE) configuration is
the a forward biased diode and due to reverse bias, the collector
collector-base
base junction acts as a reverse biased diode.
Therefore, the width of the depletion region at the emitter
emitter-base
base junction is very small whereas the width of the
depletion region at the collector-base
base junction is very large. If the output voltage VCE applied to the collector-
collector
base junction is further increased, the depletio
depletion n region width further increases. The base region is lightly doped
as compared to the collector region. So the increases, depletion region penetrates more into the base region and
less into the collector region. As a result, the width of the base region de
decreases
creases which in turn reduces the input
current (Ib) produced in the base region.

To determine the output characteristics, the input current or base current la is kept constant at
output voltage Va is increased from zero volts to different voltage levels
levels. For
each level of output voltage, the corresponding output current (le) is recorded. When output
voltage Vee is reduced to a small value (0.2 V), the collector
collector-base
base junction becomes forward
biased. This is because the output voltage Vce has less effect oon collector-base
base junction than input voltage VBE.
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Circuit Diagram:

Procedure:
Input Characteristics:
1. Connect the circuit as shown in fig.(1).
2. Adjust all the knobs of the power supply to their minimum positions before switching the
supply on.
3. Adjust the VCE to 0 V by adjusting the supply VCC.
4. Vary the supply voltage VBB so that VBE varies in steps of 0.1 V from 0 to 0.5 V and then
in steps of 0.02 V from 0.5 to 0.7 V. In each step note the value of base current In-
5. Adjust VCE to 1, 2V and repeat step-3 for each value of VCE
6. Plot a graph between VBE and IB for different values of VCE. These curves are called input
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characteristics.

Output Characteristics:

1. Connect the circuit as shown in fig. (2). All the knobs of the power supply must be at the
minimum position before the supply is switched on
2. Adjust the base current la to 20 µA by adjusting the supply V10
3. Vary the supply voltage VCC so that the voltage VCE varies in steps of 0.2 V from 0 to 2.
V and then in steps of 1 V from 2 to 10 V. In each step the base current should be
adjusted to the present value and the collector current le should be recorded.
4. Adjust the base current at 40, 60 µA and repeat step-3 for each value of le
5. Plot a graph between the output voltage VCE and output current led for different values of
the input current Ip. These curves are called the output characteristics.

Input Characteristics
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Output Characteristics
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Waveform:
Input Characteristics:

Output Characteristics:
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Common-Base Configuration

Theory & Design:

In this configuration the base is made common to both the input and out. The emitter
is given the input and the output is taken across the collector. The current gain of this
configuration is less than unity. The voltage gain of CB configuration is high. Due to
the high voltage gain.
the power gain is also high. In CB configuration, Base is common to both input and
output. In CB configuration the input characteristics relate l and VEB for a constant
Ven Initially let
Vo then the input junction is equivalent to a forward biased diode and the
characteristics resembles that of a diode. Where VCB=+ Vi(volts) due to early effect
le increases and so the characteristics shifts to the left. The output characteristics
relate le and VCB for a constant le Initially le increases and then it levels for a value
IC=a.IE. When I is increased IC also increases proportionality. Though increase in
VCE causes an increase in a, since a is a fraction, it is negligible and so le remains a
constant for all values of VCE once it levels off.
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PROCEDURE:
Input Characteristics:
It is the curve between emitter current Ie and emitter-base voltage VBE at constant collector
base voltage Ven
1. Connect the circuit as per the circuit diagram.

2. Set VCE=5V, vary Vue in steps of 0.IV and note down the corresponding is. Repeat the

above procedure for 10V, 15V.

3. Plot the graph VBE, Vs Is for a constant VCE

Output Characteristics:
It is the curve between collector current IC and collector-base voltage VCB at
constant emitter current Is.
1. Connect the circuit as per the circuit diagram.
2. Set Ig"20uA, vary Ver in steps of IV and note down the corresponding le.
3. Plot the graph VCE Vs le for a constant le
Repeat the above procedure for 404A, 80A, etc.
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CIRCUIT DIAGRAM:

Fig. Common Base Configuration

Observation Table:
Input Characteristics:
S.NO VCB=0.5V VCB=1. VCB=10V
5
VE IE VE IE VE IE
B (mA B (mA B (mA
(V) ) (V) ) (V) )
1. -0.1 0 -0.1 0 -0.1 0
2. -0.2 0 -0.2 0 -0.2 0
3. -0.4 0 -0.4 0 -0.3 0
4. -0.51 8.5 -0.51 8.5 -0.5 3.73
5. -0.53 16.75 -0.53 16.77 -0.54 25.92
6. -0.54 25 -0.54 25.6 -0.58 145
7. -0.55 34.35 -0.55 34.8
8. -0.57 92 -0.58 141

Output Characteristics:
S.NO IE=1mA IE=1.44mA IE=1.93mA

VC IC(- VC IC VC IC
B ve) B (mA B (mA
(V) (mA) (V) ) (V) )
 1. -0.67 0.77 -0.7 0.7 -0.72 0.72
2. -0.53 1.03 -0.67 1.17 -0.7 1.12
3. -0.03 1.03 -0.43 1.43 -0.67 1.67
4. 0.96 1.03 0.07 1.43 0.07 1.93
5. 3.97 1.03 3.57 1.43 3.07 1.93

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Input Characteristics:

Common-Collector Configuration

Theory & Design:

BJT is a three terminal two junction semiconductor device in which the conduction is due
to both the charge carrier. Hence it is a bipolar device and it amplifier the sine waveform as
they are transferred from input to output. BJT is classified into two types - NPN or PNP. A
NPN transistor consists of two N types in between which a layer of P is sandwiched. The
transistor consists of three terminal emitter, collector and base. The emitter layer is the source
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of the charge carriers and it is heartily doped with a moderate cross sectional area. The
collector collects the charge carries and hence moderate doping and large cross sectional area.
The base region acts a path for the movement of the charge carriers. In order to reduce the
recombination of holes and electrons the base region is lightly doped and is of hollow cross
sectional area. Normally the transistor operates with the EB junction forward biased.

Procedure:
Input Characteristics:
1. Connect the circuit as per the circuit diagram.
2. Set VCE, vary VBE in regular interval of steps and note down the corresponding la
reading. Repeat the above procedure for different values of Var
3. Plot the graph: VCE Vs lC for a constant Vee

Output Characteristics:
1. Connect the circuit as per the circuit diagram.
2. Set IB , Vary VCE in regular interval of steps and note down the corresponding lc reading.
Repeat the above procedure for different values of In.
3. Plot the graph: V Vs le for a constant IB.

Fig. Common Collector Configuration

Input Characteristics:
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Output Characteristics:
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OBSERVATION TABLE:
Input Characteristics:

VCE=1 VCE=2V
V
VBC(V) IE (mA) VBC(V) IE (mA)

0.93 1.35 0.93 1.34

1.56 8.84 1.36 2.79
1.59 18.21 1.79 4.23
1.60 27.90 2.53 9.30
1.62 47.54 2.60 28
1.64 87.16 2.62 47.59
1.66 166.75 2.66 146.85

Output Characteristics:

IE=20m IE=40m
A A
VCE(V) IE (mA) VCE(V) IE (mA)

0.049 0.95 0.03 1.34

0.093 2.91 0.047 1.95
0.141 4.86 0.082 4.92
1.09 5.91 0.144 9.86
2.94 6.06 0.33 11.67
4.8 6.20 2.92 12.08
8.5 6.5

Conclusion
Input and Output Characteristics of a BJT in CE , CB ,CC Configuration are studied.

Precautions:
1. While performing the experiment do not exceed the ratings of the transistor. This may
lead to damage the transistor
2. Connect voltmeter and ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as
per the circuit diagram.
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EXPERIMENT -7
AIM: TO VERIFY VI CHARACTERISTICS OF FET

APPARATUS:

FET (BFW-10), Regulated power supply, Voltmeter (0-20V),

Ammeter (0-100mA), Bread Board, Connecting Wires.
THEORY:
The Field Effect Transistor or Simply FET uses the voltage that is
applied to their input terminal, called the Gate to control the
current flowing through them resulting in the output current being
proportional to the input voltage, the Gates to source junction of
the FET is always reversed biased. As their operation relies on
an electric field (hence the name field effect) generated by the
input Gate voltage, this then makes the Field Effect Transistor a
“VOLTAGE” operated device.
The Field Effect Transistor is a three terminal unipolar
semiconductor device that has very similar characteristics to
those of their Bipolar Transistor counterpart’s i.e., high efficiency,
instant operation, robust and cheap and can be used in most
electronic circuit applications to replace their equivalent bipolar
junction transistors (BJT).
The Field Effect Transistor has one major advantage over its
standard bipolar transistor, in that input impedance, (Rin) is very
high, (thousands of Ohms). This very high input impedance
makes them very sensitive to input voltage signals.
There are two basic configurations of junction field effect
transistor, the N-channel JFET and the P-channel JFET. The N-
channel JFET’s channel is doped with donor impurities meaning
that the flow of current through the channel is negative (hence
the term N-channel) in the form of electrons.
A FET is a three terminal device, having the characteristics of
high input impedance and less noise, the Gate to Source junction
of the FET is always reverse biased. In amplifier application, the
FET is always used in the region beyond the pinch-off.
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The characteristics curves example shown above, shows the four different
regions of operation for a JFET and these are given as:

 Ohmic Region-When VGS =0 the depletion layer of the channel is very

smalland the JFET acts like a voltage controlled resistor.

 Cut-off region- This is also known as the pinch-off region were the Gate
Voltage, VGS is sufficient to cause the JFET to act as an open circuit as
the channel resistance is at maximum.

 Saturation or Active Region – The JFET becomes a good

conductor and is controlled by the Gate-Source voltage, (VGS) while
the Drain-Sourcevoltage, (VDS) has little or no effect.

 Breakdown Region-The voltage between the Drain and the Source,

(VDS) ishigh enough to causes the JFET’s resistive channel to break down
and pass uncontrolled maximum
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TRANSFER OR TRANSCONDUCTANCE CHARACTERISTICS:

Transfer characteristics are useful in evaluating the operating conditions

of an FET. Drain current in the active region.
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TRANSFER CHARACTERISTICS

Gate - Source Voltage V Tn Volts

Transfer Characteristics of JFET

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EXPERIMENT NO: 8
The aim of this experiment is to plot
(i) the output characteristics and,
(ii) (ii) the transfer characteristics of an n-channel and p-channel MOSFET.

Introduction

The metal–oxide–semiconductor field-effect transistor (MOSFET) is a transistor

used for amplifying or switching electronic signals. In MOSFETs, a voltage on the
oxide-insulated gate electrode can induce a conducting channel between the two
other contacts called source and drain. The channel can be of n-type or p-type, and
is accordingly called an nMOSFET or a pMOSFET. Figure 1 shows the schematic
diagram of the structure of an nMOS device before and after channel formation.
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Output Characteristics

MOSFET output characteristics plot ID versus VDS for several values of VGS.

The characteristics of an nMOS transistor can be explained as follows. As the

voltage on the top electrode increases further, electrons are attracted to the surface.
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At a particular voltage level, which we will shortly define as the threshold voltage,
the electron density at the surface exceeds the hole density. At this voltage, the
surface has inverted from the p-type polarity of the original substrate to an n-type
inversion layer, or inversion region, directly underneath the top plate as indicated in
Fig. 1(b). This inversion region is an extremely shallow layer, existing as a charge
sheet directly below the gate. In the MOS capacitor, the high density of electrons in
the inversion layer is supplied by the electron–hole generation process within the
depletion layer. The positive charge on the gate is balanced by the combination of
negative charge in the inversion layer plus negative ionic acceptor charge in the
depletion layer. The voltage at which the surface inversion layer just forms plays an
extremely important role in field-effect transistors and is called the threshold voltage
Vtn. The region of output characteristics where VGStn and no current flows is called
the cutt-off region. When the channel forms in the nMOS (pMOS) transistor, a
positive (negative) drain voltage with respect to the source creates a horizontal
electric field moving the electrons (holes) toward the drain forming a positive
(negative) drain current coming into the transistor. The positive current convention
is used for electron and hole current, but in both cases electrons are the actual charge
carriers. If the channel horizontal electric field is of the same order or smaller than
the vertical thin oxide field, then the inversion channel remains almost uniform along
the device length. This continuous carrier profile from drain to source puts the
transistor in a bias state that is equivalently called either the non-saturated, linear, or
ohmic bias state. The drain and source are effectively short-circuited. This happens
when VGS > VDS + Vtn for nMOS transistor and VGS < VDS +Vtp for pMOS transistor.
Drain current is linearly related to drain-source voltage over small intervals in the
linear bias state.
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But if the nMOS drain voltage increases beyond the limit, so that VGS < VDS +
Vtn, then the horizontal electric field becomes stronger than the vertical field at the
drain end, creating an asymmetry of the channel carrier inversion distribution.

If the drain voltage riseswhile the gate voltage remains the same, then VGD can go
below the threshold voltage in the drain region. There can be no carrier inversion at
the drain-gate oxide region, so the inverted portion of the channel retracts from the
drain, and no longer “touches” this terminal. The pinched-off portion of the channel
forms a depletion region with a high electric field. The n-drain and p-bulk form a pn
junction. When this happens the inversion channel is said to be “pinched-off” and
the device is in the saturation region. The characteristics can be loosely modelled by
the following equations.

Transfer Characteristics

The transfer characteristic relates drain current (ID) response to the input gate- source
driving voltage (VGS). Since the gate terminal is electrically isolated from the
remaining terminals (drain, source, and bulk), the gate current is essentially zero, so
that gate current is not part of device characteristics. The transfer characteristic curve
can locate the gate voltage at which the transistor passes current and leaves the OFF-
state. This is the device threshold voltage (Vtn). Figure 5 shows measured input
characteristics for an nMOS and pMOS transistor with a small 0.1V potential across
their drain to source terminals.
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The transistors are in their non-saturated bias states. As VGS increases for the nMOS
transistor in Figure 5a, the threshold voltage is reached where drain current elevates.
For VGS between 0V and 0.7V, ID is nearly zero indicating that the equivalent
resistance between the drain and source terminals is extremely high. Once VGS
reaches 0.7V, the current increases rapidly with VGS indicating that the equivalent
resistance at the drain decreases with increasing gate-source voltage. Therefore, the
threshold voltage of the given nMOS transistor is about V tn ≈ 0.7V. The pMOS
transistor input characteristic in Figure 5b is analogous to the nMOS transistor except
the ID and VGS polarities are reversed.

EXPERIMENT NO. 9

AIM: TO DESIGN LC OSCILLATOR

The purpose of this simulation is to demonstrate the characteristics and

operation of a
Clapp oscillator. The Clapp oscillator is much like a Colpitts oscillator
with the
capacitive voltage divider producing the feedback signal. The addition
of a capacitor
C1 in series with the inductor L

results in the difference in the two designs and is what

makes the Clapp Oscillator unique. As with all oscillators, the
Barkhausen criteria
must be adhered to requiring a total gain of one and a phase shift of zero
degrees from
input to output.
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Ignoring the transistor capacitive effect between the base andcollector,

the resonant
frequency may be calculated using the equivalent capacitance:

C Ci C’:

B13t Sllice C is upicallj much smaller than Ct and C;. the effects of C and C becon
neelieible and:

As stated above it is the addition of arid the small alue of C that creates the Clapp
oscillator s unique characreristic of not be inc influenced b strap and traiisistor
capacitances which would o4heoi i se alter the values o1 Ct and C2. This results in a
O]3 t°fñt1Ofl IS 111Tl1te D 121 a 1d]3]3 OSClll£llOl' O12fi fldVdl4flñl C S S. Its 1st° Halo1111a" fRdXe S lfi £1
popular design. C i and C, may be adjusted for optimum feedback. The fiequeiicy of
oscillation is altered thi’oueh the adjustment of C

Parts
DC 10 \* Supplj
Transistor. BIT ?h4401
Resistors. 20 kf2. 3 9 kfl 1 2 kfl
Inductor: 2.4 mH. 6* pH
Capacitor : 12 riF. 750 pF. S.9 riF 120 pF

Test Equipment
• Oscilloscope
• Spectrum Atialvzer

i
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EXPERIMENT NO : 10

AIM: TO DESIGN RC PHASE SHIFT OSCILLATOR.

APPARATUS REQUIRED:

SEO. RANGE
EQUIPMENT 00.Sl
BC547 l
47kf2, useful
l0kfl,2.2kf 2,6 80f2 ence
3 Resistor 4.7kfl

3 Uapacitorc 1 pF,22pF

0.01 p.F 3
5 CRO
(0 — 30V) L
7 Tfi read Boo<zY L
8 Gon riecting intree Required

THEORY:
An c›scillattsr is an electronic circ sit for generating an AC signal
voltage with a DC supply as the only input requirement. The frequency
of the generated signal is decided by the circtiit elements used. An
oscillator requires an amplifier, a Neqiiency selective network and a
positive feedback frorri the output to the input.
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The barkhausen criterion for sustained oscillation is A]3 = I where A

is the gain of the arriplifier and Q is the feedback banter (gain).The
unity gain rrieans signal is in phase. ( If the signat is l 8O‘oiit of phase
and gain will be - 1 ). RR-Phase shift has a CE amplifier

s
followed by three sections of RC phase shift feed-back I etworks. The
c›iiiput cif the last stage is return tc› the input est the arnpli tier. The
satires of R and C are chosen such that the phase shift of each RC
secticin is 6O°.Thus The RC ladder network produces a total phase shift
cif 180° between its input and c›iitpii1 vciltage fc›r the given frequency.
CE Amplifier produces IRO ° phases shin The total phase shift
frc›m the base c›f the transistor arcsiind the circuit and back ie› the base
will be exactly 360.This satisfies the Barkhausen ccindito›n Weir sustaining
oscillotions and tc›tal Ic›op gain of thi.s circuit is greater or equal to 1,this
condition used to generate the sinusoidal oscillations.
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CIRCUIT DIAGRAM:
dcc =12V

68kñ R1
0.1y 0.1y 0.1y

1Kñ 10K R 1!**!*

R 1OKt R

PROCEDURE:

1. Identify be pin details of BC1O7 TRANSISTOR (Or equivalent silicon

Transistor such as BC108/547) and test it using a milliimeter. Setup the
circuit on breadboard as shown in figure.
2. A I 2v Supply voltage is given by using Regulated power supply
and output is taken from collector of the Transistor.
3. By using CRO the output time period amd voltage are noted.
4. Plot all the readings curves on single graph sheet.

RESULT:

Thus the RC phase shift oscillator using BJT was obtained and the output waveform
was plotted.