Sri Ramakrishna Engineering College: 20ec214 & Digital Cmos Vlsi Circuits

SRI RAMAKRISHNA ENGINEERING COLLEGE
[Educational Service : SNR Sons Charitable Trust]

[Autonomous Institution, Reaccredited by NAAC with ‘A+’ Grade]
[Approved by AICTE and Permanently Affiliated to Anna University, Chennai]
[ISO 9001:2015 Certified and all eligible programmes Accredited by NBA]
VATTAMALAIPALAYAM, N.G.G.O. COLONY POST, COIMBATORE – 641 022.
Department of Electronics and Communication Engineering
20EC214 & DIGITAL CMOS VLSI CIRCUITS
Course Instructor
Dr.C.S.Manikandababu
Associate Professor
Department of Electronics and Communication Engineering
No. of Credits : 3
VISION & MISSION OF THE COLLEGE
Vision of the College:

To develop into a leading world class Technological
University consisting of Schools of Excellence in various
disciplines with a co-existent Centre for Engineering
Solutions Development for world-wide clientele.
Mission of the College:
To provide all necessary inputs to the students for them
to grow into knowledge engineers and scientists
attaining.
• Excellence in domain knowledge- practice and theory.
• Excellence in co-curricular and Extra curricular
talents.
• Excellence in character and personality.
31-01-2023 Digital CMOS VLSI Circuits 2

VISION & MISSION OF THE DEPARTMENT
Vision of the Department:

To develop Electronics and Communication Engineers by
keeping pace with changing technologies, professionalism,
creativity research and employability.
Mission of the Department:

• To provide quality an contemporary education through
effective teaching- learning process that equips the
students with adequate knowledge in Electronics and
Communication Engineering for a successful career.
• To inculcate the students in problem solving and lifelong
learning skills that will enable them to pursue higher
studies and career in research.
• To produce engineers with effective communication skills,
the abilities to lead a team adhering to ethical values and
inclination serve the society.
PROGRAMME EDUCATIONAL OBJECTIVES
(PEOs)
The Program Educational Objective (PEOs) of ECE is

established through consultative process. The PEOs of
Electronics and Communication Engineering will
demonstrate the following qualities which would be
attained by the graduates after few years of graduation.
PEO1: Excel in professional career to provide engineering solution
by demonstrating technical competence and by acquiring knowledge
in electronics and communication engineering.
PEO2 : Identify, analyze and formulate problems to offer appropriate
design solutions that are technically superior, economically feasible,
environmentally compatible, professionally ethical and socially
acceptable.
PEO3 : Achieve progress in professional and research career through
communication skills, team work and knowledge up gradation
through higher education.
PROGRAM SPECIFIC OUTCOMES
Graduates of Electronics and Communication Engineering

at the time of graduation will be able to,
PSO1: Specify, design, implement and test digital and analog

electronic systems using state of art component and software tools
PSO2: Architect and specify the analog and digital communication

systems as per the performance requirement specifications.
PSO3: Understand and specify the components of RF/Wireless

communication systems.

20EC214 - DIGITAL CMOS VLSI CIRCUITS
COURSE OUTCOMES
On successful completion of the course, students

will be able to,
COURSE OUTCOMES
Interpret the characteristics and manufacturing process
CO1 technologyof MOS transistor.
Analyze the various logic styles of CMOS combinational
CO2 andsequential circuits
CO3 Design the various digital arithmetic logic circuits.
Illustrate the performance of the digital circuits by examining
CO4 the timing issues.
Make use of MOS concepts in construction of Memory Array
CO5 Subsystem.

COURSE CONTENTS
PREREQUISITES
✓ 20EC204 - Digital System Design
MOS TRANSISTOR AND PROCESSING 10
MOSFET theory - Transistor switches - Compound gates - Design equations - IV characteristics -
CV characteristics - Second order effects - Energy and Power - Resistance Estimation -
Capacitance Estimation - Switching Characteristics - RC Delay Models - Logical Effort for gates -
CMOS Process technology - Design Rules and Layout.
CMOS LOGIC STRUCTURES 11
Combinational Circuits: CMOS Inverter - DC Characteristics - Complementary Logic Structures -
Ratioed logic - Pass transistor logic - Transmission gate - Tristate Inverter - Multiplexers -
Dynamic logic structures. Sequential Circuits: Static latches and Registers, Dynamic latches and
Registers, Pulse Registers, Sense Amplifier Based Register, Pipelining.
DESIGN OF ARITHMETIC BUILDING BLOCKS 8
Full adder, Ripple carry adder, Carry bypass adder, Linear and Square root carry-select adder,
Carry look-ahead adder - Multipliers - Barrel and logarithmic shifter.
TIMING ISSUES 8
Timing Basics, Sources of Skew and Jitter, Clock-Distribution Techniques, Latch-Based locking,
Self-Timed Circuit Design, Synchronizers and Arbiters, Clock Synthesis and Synchronization
Using a Phase-Locked Loop.
MEMORY ARRAY SUBSYSTEM 8
SRAM: SRAM Cells, Row Circuitry, Column Circuitry. Multiported SRAM and Register files
DRAM: Subarray Architectures, Column Circuitry, Embedded DRAM. Read-Only Memory:
Programmable ROMs, NAND ROMs, Flash.

COURSE CONTENTS
TEXT BOOKS
1. Neil H.E. Weste and David Harris, "CMOS VLSI Design A Circuits
and Systems Perspective", 4th Edition, Pearson Education, Reprint
2010.
2. Jan M. Rabaey, Anantha Chandrakasan and B Nikolic, "Digital
Integrated Circuits: A Design Perspective", 2nd Edition, Pearson
Education India, 2016.
REFERENCES
1. Douglas. A. Pucknell, Kamran Eshraghian, "Basic VLSI Design",
3rd Edition, Prentice Hall India, 2010.
2. John P.Uyemura, "Introduction to VLSI Circuits and Systems",
John Wiley & Sons, 2012.
WEB REFERENCES
1. https://nptel.ac.in/courses/108/107/108107129/
2. https://nptel.ac.in/courses/117/106/117106093/
MODULE 2 - CMOS LOGIC STRUCTURES
Combinational Circuits: CMOS Inverter - DC

Characteristics - Complementary Logic Structures -
Ratioed logic - Pass transistor logic - Transmission gate -
Tristate Inverter - Multiplexers - Dynamic logic
structures. Sequential Circuits: Static latches and
Registers, Dynamic latches and Registers, Pulse
Registers, Sense Amplifier Based Register, Pipelining.

CMOS LOGIC
The Inverter
o Figure, shows the schematic and symbol for a
CMOS inverter or NOT gate using one nMOS
transistor and one pMOS transistor.
o The bar at the top indicates VDD and the triangle
at the bottom indicates GND.
o When the input A is 0,
o the nMOS transistor is OFF and the pMOS
transistor is ON
o the output Y is pulled up to 1, because it is
connected to VDD but not to GND
o When A is 1,
o the nMOS is ON, the pMOS is OFF
o Y is pulled down to ‘0’

CMOS LOGIC
The NAND Gate
❑ Figure, shows a 2-input CMOS NAND gate.
o It consists of two series nMOS transistors between Y
and GND and two parallel pMOS transistors between Y
and VDD.
❑ If either input A or B is 0,
o at least one of the nMOS transistors will be OFF,
breaking the path from Y to GND. But at least one of
the pMOS transistors will be ON, creating a path from
Y to VDD, the output Y will be 1
❑ If both inputs are 1,
– both of the nMOS transistors will be ON and both of
the pMOS transistors will be OFF, the output will be 0.

CMOS LOGIC
The NAND Gate
❑ k-input NAND gates are constructed using k series nMOS
transistors and k parallel pMOS transistors.
FOR EXAMPLE:
A a 3-input NAND gate is shown,
❑ When any of the inputs are 0,

✓ the output is pulled high
through the parallel pMOS
transistors
❑ When all of the inputs are 1,
✓ the output is pulled low
through the series nMOS
transistors
CMOS LOGIC
CMOS Logic Gates
❑ The inverter and NAND gates are
examples of static CMOS logic gates,
also called complementary CMOS
gates.
❑ In general, a static CMOS gate has
an nMOS pull-down network to
connect the output to 0 (GND) and
pMOS pull-up network to connect
the output to 1 (VDD), as shown in
Figure.
❑ The networks are arranged such
that one is ON and the other OFF
for any input pattern.

CMOS LOGIC
CMOS Logic Gates
❑ The pull-up and pull-down networks in the inverter each consist of a
single transistor.
❑ The NAND gate uses a series pull-down network and a parallel pullup
network.

CMOS LOGIC
CMOS Logic Gates
❑ More elaborate
networks are used for
more complex gates.
o Two or more
transistors in series
are ON only if all of
the series
transistors are ON.
o Two or more
transistors in
parallel are ON if
any of the parallel
transistors are ON.
CMOS LOGIC
CMOS Logic Gates
✓ when we join a pull-up network to a pull-down
network to form a logic gate as shown in Figure , they
both will attempt to exert a logic level at the output
✓ The possible levels at the output are,
✓ it can be seen that the output of a CMOS logic gate can be in four states
✓ The 1 and 0 levels have been encountered with the inverter and
✓ NAND gates, where either the pull-up or pull-down is OFF and the other
structure is ON.
✓ When both pull-up and pull-down are OFF, the high impedance or floating Z
output state results.
✓ The crowbarred (or contention) X level exists when both pull-up and pull-
down are simultaneously turned ON.
CMOS LOGIC
CMOS Logic Gates
❑ When both pull-up and pull-down are OFF, the high impedance or
floating Z output state results
– This is of importance in multiplexers, memory elements, and tristate
bus drivers.
❑ The crowbarred (or contention) X level exists when both pull-up and
pull-down are simultaneously turned ON.
– Contention between the two networks results in an indeterminate
output level and dissipates static power. It is usually an unwanted
condition.

CMOS LOGIC
The NOR Gate
❑ A 2-input NOR gate is shown in Figure,
➢ The nMOS transistors are in parallel
to pull the output low when either
input is high.
➢ The pMOS transistors are in series to
pull the output high when both
inputs are low, as indicated in Table
➢ The output is never crowbarred or
left floating.

CMOS LOGIC
Take Two minutes to Answer the Question
Tell,
o How to design a 3-input CMOS NOR gate?
o Its logic operation ?

SOLUTION:
CMOS LOGIC
If any input is high, the output is pulled low through the

parallel nMOS transistors.
If all inputs are low, the output is pulled high through the
series pMOS transistors.

Brain Game
‘Boost Your Brain Power’

CMOS LOGIC
Pass Transistors and Transmission Gates
❑ The strength of a signal is measured by how closely it approximates an ideal
voltage source.
– the stronger a signal, the more current it can source or sink
– The power supplies, or rails, (VDD and GND) are the source of the strongest
1s and 0s
❑ An nMOS transistor is an almost perfect switch,
o when passing a 0 and thus we say it passes a strong 0
o the nMOS transistor is imperfect at passing a 1
➢ The high voltage level is somewhat less than VDD
➢ say it passes a degraded or weak 1
Pass transistor strong

and degraded outputs

CMOS LOGIC
❑ A pMOS transistor again has the opposite behavior,
o Passing strong 1s but degraded 0s
Pass transistor strong and degraded outputs
❑ When an nMOS or pMOS is used alone as an imperfect switch,
o call it a PASS TRANSISTOR

CMOS LOGIC
❑ By combining an nMOS and a pMOS transistor in parallel (a),
o we obtain a switch that turns on when a 1 is applied to g (b)
o In which 0s and 1s are both passed in an acceptable fashion (c)
➢ this a Transmission Gate or Pass Gate
❑ In a circuit where only a 0 or a 1 has to be passed,

o the appropriate transistor (n or p) can be deleted, reverting to a single
nMOS or pMOS device.
Transmission Gate
CMOS LOGIC
Note :
❑ That both the control input and its complement are required by
the transmission gate. This is called double rail logic.
o Some circuit symbols for the transmission gate are shown (d)
Transmission Gate

CMOS LOGIC
SO FAR,
o the inputs drive the gate terminals of nMOS
transistors in the pull-down network and
pMOS transistors in the complementary pull-
up network, as was shown in Figure
o the nMOS transistors only need to pass 0s
and the pMOS only pass 1s, so the output is
always strongly driven and the levels are never
degraded.
o This is called a fully restored logic gate

CMOS LOGIC
o A consequence of the design of static CMOS
gates is that they must be inverting.
o The nMOS pull-down network turns ON
when inputs are 1, leading to 0 at the
output.
o We might be tempted to turn the
transistors upside down to build a
noninverting gate.
For example,
➢ Figure (A) shows a noninverting buffer.
o now both the nMOS and pMOS
transistors produce degraded outputs,
so the technique should be avoided

CMOS LOGIC
Pass Transistors and Transmission
Gates
For example,
❑ Instead, can build noninverting
functions from multiple stages of
inverting gates.
➢ Figure (B) shows several ways to
build a 4-input AND gate from
two levels of inverting static
CMOS gates.
➢ Each design has different speed,
size, and power trade-offs.

CMOS LOGIC
Similarly,
• The compound gate disused earlier could be built with two AND gates,
an OR gate, and an inverter.
• The AND and OR gates in turn could be constructed from NAND/NOR
gates and inverters, as shown below, using a total of 20 transistors, as
compared to eight in Figure SLIDE NO. 186
• Good CMOS logic designers exploit the the efficiencies of compound
gates rather than using large numbers of AND/OR gates.

Story Time
How To Face Hardships In Life?

Story Time
Moral of the Story

‘Pain is unavoidable’ means
that whatever pain the body
has to go through it has to,
But thinking about the pain
over and over again to be
miserable or not is your own
free will.
CMOS LOGIC
Sometimes both true and complementary enable signals,
are drawn explicitly, while sometimes only EN is shown.

CMOS LOGIC
Tristates
❑ The transmission gate in Figure has the same
truth table as a tristate buffer.
o It only requires two transistors but it is a
non-restoring circuit.
– If the input is noisy or otherwise degraded,
the output will receive the same noise.
– delay of a series of non-restoring gates
increases rapidly with the number of gates.

CMOS LOGIC
Tristates
❑ Figure (a) shows a Tristate Inverter,
– The output is actively driven from VDD or GND, so it
is a Restoring Logic Gate.
– the tristate inverter does not obey the conduction Tristate Inverter
complements rule because it allows the output to
float under certain input combinations.
➢ When EN is 0,
o Figure (b), both enable
transistors are OFF, leaving the
output floating.
➢ When EN is 1,
o Figure (c), both enable
transistors are ON.

CMOS LOGIC
Tristates
❑ Tristate Inverter,
o are conceptually removed from the circuit, leaving
a simple inverter
o Figure (d) shows symbols for the tristate inverter.
o The complementary enable signal can be
generated internally or can be routed to the cell
explicitly
o A Tristate Buffer can be built as an ordinary
inverter followed by a tristate inverter.

CMOS LOGIC
Tristates
❑ Tristates were once commonly,
o used to allow multiple units to drive a common bus, as long as exactly one
unit is enabled at a time
o If multiple units drive the bus,
o contention occurs and power is wasted
o If no units drive the bus,
o it can float to an invalid logic level that causes the receivers to waste
power
❑ Moreover,
✓ it can be difficult to switch enable signals at exactly the same time when they
are distributed across a large chip
❑ Delay between different enables switching can cause contention.
Due to the above Problems,
❑ Multiplexers are now preferred over Tristate Busses
CMOS LOGIC
Multiplexers
❑ Multiplexers are key components in CMOS memory elements and data
manipulation structures.
❑ A multiplexer chooses the output from among several inputs based on a
select signal.
❑ A 2-input, or 2:1 multiplexer,
➢ chooses input D0,
✓ when the select is 0
➢ chooses input D1,
✓ when the select is 1
❑ The truth table is for,
✓ the logic function

CMOS LOGIC
Multiplexers
❑ Two transmission gates can be tied together to
form a compact 2-input multiplexer, as shown in
Figure (a).
❑ The select and its complement enable exactly one
of the two transmission gates at any given time.
The complementary select S is often not drawn in
the symbol, as shown in Figure (b)
➢ Again,
➢ the transmission gates produce a nonrestoring Transmission
multiplexer Gate Multiplexer
➢ So, build a restoring, inverting multiplexer out
of gates in several ways

CMOS LOGIC
Multiplexers
❑ One is the compound gate of Figure (a), connected as shown in Figure
(b).
(a) CMOS Compound gate (b) Inverting Multiplexer

CMOS LOGIC
Multiplexers
❑ Another is to gang together two tristate inverters, as
shown in Figure (c).
❑ the schematics of these two approaches are nearly
identical, save that the pull-up network has been
slightly simplified and permuted in Figure (c).
❑ This is possible because the select and its (c) Inverting
complement are mutually exclusive. Multiplexer
❑ The tristate approach is slightly more compact and
faster because it requires less internal wire
❑ If the complementary select is generated within the
cell, it is omitted from the symbol, in Figure (d)
➢ Larger multiplexers can be built from multiple 2-
input multiplexers or by directly ganging together Figure (d)
several tristates
CMOS LOGIC
Multiplexers
✓ The latter approach requires
decoded enable signals for each
tristate; the enables should switch
simultaneously to prevent
contention.
✓ 4-input (4:1) multiplexers using
each of these approaches are
shown.
✓ In practice, both inverting and
noninverting multiplexers are
simply called multiplexers or
muxes.
4:1 Multiplexer

CMOS LOGIC
Sequential Circuits
❑ So far, combinational circuits, whose outputs depend only on the current
inputs.
❑ Sequential circuits have memory: their outputs depend on both current
and previous inputs.
❑ Using the combinational circuits developed so far,
❑ now build sequential circuits such as latches and flip-flops.
❑ These elements receive a clock, CLK, and a data input, D, and produce an
output, Q.
❑ A D latch is transparent,
❑ when CLK = 1, meaning that Q follows D, It becomes opaque
❑ when CLK = 0, meaning Q retains its previous value and ignores changes in
D
❑ An edge-triggered flip-flop copies D to Q on the rising edge of CLK and
remembers its old value at other times.
CMOS LOGIC
Sequential Circuits - Latches
❑ A D latch built from a 2-input multiplexer and two inverters is
shown in Figure (a)
❑ The multiplexer can be built from a pair of transmission gates,
shown in Figure (b), because the inverters are restoring.

CMOS LOGIC
❑ D latch also produces a complementary output, .
✓ When CLK = 1,
o the latch is transparent and D flows through to Q (Figure c)
✓ When CLK falls to 0,
o the latch becomes opaque. A feedback path around the inverter pair
is established (Figure d) to hold the current state of Q indefinitely.

CMOS LOGIC
❑ The D latch is also known as a level-sensitive latch because the state
of the output is dependent on the level of the clock signal, as shown in
Figure (e).
❑ The latch shown is a positive-level-sensitive latch, represented by the
symbol in Figure (f). By inverting the control connections to the
multiplexer, the latch becomes negative-level-sensitive.

CMOS LOGIC
Sequential Circuits - Flip-Flops
❑ By combining two level-sensitive latches, one negative-sensitive and one
positive-sensitive, the edge-triggered flip-flop is constructed shown in
Figure (a–b).
❑ The first latch stage is called the master and the second is called
the slave.

CMOS LOGIC
❑ While CLK is low,
❑ the master negative-level-sensitive latch output (QM) follows
the D input while the slave positive-level-sensitive latch holds
the previous value Figure(c)

CMOS LOGIC
❑ When the clock transitions from 0 to 1,
❑ the master latch becomes opaque and holds the D value at the
time of the clock transition. The slave latch becomes transparent,
passing the stored master value (QM) to the output of the slave
latch (Q).
❑ The D input is blocked from affecting the output because the
master is disconnected from the D input (Figure d)

CMOS LOGIC
❑ When the clock transitions from 1 to 0, the slave latch holds its
value and the master starts sampling the input again.
❑ While we have shown a transmission gate multiplexer as the
input stage, good design practice would buffer the input and
output with inverters, as shown in Figure (e), to preserve what we
call “modularity.”

CMOS LOGIC
❑ This flip-flop copies D to Q on the rising edge of the clock, as
shown in Figure (f)
✓ Thus, this device is called a Positive-edge Triggered Flip-flop (also
called a D flip-flop, D register, or master–slave flip-flop).
✓ By reversing the latch polarities, a negative-edge triggered flip-flop
may be constructed
❑ Figure (g) shows the circuit symbol for the flip-flop.

CMOS LOGIC
❑ A collection of D flip-flops sharing a common clock input is called

a register.
o A register is often drawn as a flip-flop with multi-bit D and Q busses
❑ Flip-flops may experience hold-time failures if the system has

too much clock skew,
i.e., if one flip-flop triggers early and another triggers late

because of variations in clock arrival times.

CMOS LOGIC
➢ Hold-time Problems can be avoided altogether,
– by distributing a two-phase nonoverlapping clock
– Figure shows the flip-flop clocked with two nonoverlapping phases
– As long as the phases never overlap, at least one latch will be opaque
at any given time and hold-time problems cannot occur.

1. In CMOS logic circuit the n-MOS transistor acts as:

a) Load
b) Pull up network
c) Pull down network
d) Not used in CMOS circuits
2. When both nMOS and pMOS transistors of CMOS logic design
are in OFF condition, the output is:
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) High impedance or floating(Z)
d) None of the mentioned
3. When both nMOS and pMOS transistors of CMOS logic gates
are ON, the output is:
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) Crowbarred or Contention(X)
4. In CMOS logic circuit, the switching operation occurs

because:
a) Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’
and turns ON simultaneously for input ‘1’
b) Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’
and turns OFF simultaneously for input ‘1’
c) N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF
for input ‘1’ and N-MOS transistor turns OFF, and p-MOS transistor
turns ON for input ‘0’
5. Inverters are essential for ________
a) NAND gates
b) NOR gates
c) sequential circuits
d) all of the mentioned

Answers:
1. c) Pull down network
2. c) High impedance or floating(Z)
3. c) Crowbarred or Contention(X)
4. c) N-MOSFET transistor turns ON, and p-MOSFET transistor
turns OFF for input ‘1’ and N-MOS transistor turns OFF, and p-
MOS transistor turns ON for input ‘0’
5. d) all of the mentioned

Give Your Mind a Workout
‘Brain
Teasers
That’ll
Improve Your Memory’

1. A woman shoots her husband. Then she holds him

under water for over 5 minutes. Finally, she hangs
him. But 5 minutes later they both go out together
and enjoy a wonderful dinner together. How can
this be?
2. How can 8 + 8 = 4?
3. There is a word in the English language in which

the first two letters signify a male, the first
three letters signify a female, the first four
signify a great man, and the whole word, a great
woman. What is the word?
Answers:
1. The woman was a photographer. She shot a picture of
her husband, developed it, and hung it up to dry.
2. When you think in terms of time.

8 AM + 8 hours = 4 o’clock.
3. Heroine

Static CMOS Inverter- DC Transfer Characteristics

❑ The DC transfer function (Vout vs. Vin) for the static (A)
CMOS inverter shown in in Figure (A)
❑ The below Table outlines various regions of operation
for the n- and p-transistors


❑ In the table,
o Vtn is the threshold voltage of the n-channel device
o Vtp is the threshold voltage of the p-channel device
o Vtp is negative.
❑ The equations are given both in terms of,
Vgs /Vds and Vin /Vout
❑ The source of the nMOS transistor is grounded,
Vgsn = Vin and Vdsn = Vout

CMOS INVERTER
❑ The source of the pMOS transistor is tied to VDD,
Vgsp = Vin – VDD and Vdsp = Vout – VDD


❑ Objective is to find the variation in output voltage (Vout) as a function of
the input voltage (Vin).
❑ Given Vin,
o find Vout subject to the constraint that Idsn = |Idsp|.
o assume Vtp = –Vtn and
o that the pMOS transistor is 2 – 3 times as wide as the nMOS
transistor
o so, βn = βp
➢ The graphical representation of the simple algebraic equations for the
two transistors, (Next Slide)

The plot shows Idsn

and Idsp in terms of
Vdsn and Vdsp for
various values of
Vgsn and Vgsp


o The below graphical
representation shows the
same plot of Idsn and
|Idsp| now in terms of
Vout for various values of
Vin.
o The possible operating
points of the inverter,
marked with dots,
• are the values of Vout
where,
• Idsn = |Idsp| for a
given value of Vin

o These operating points are

plotted on Vout vs. Vin
axes in the below graphical
representation to show the
inverter DC transfer
characteristics
➢ Indicating the five regions

of operation of the CMOS
inverter


❑ The supply current,
IDD = Idsn = |Idsp|
is also plotted against Vin in below graphical representation
o showing that both transistors are momentarily ON as Vin passes
through voltages between GND and VDD,
➢ resulting in a pulse of current drawn from the power supply


➢ Indicating the five regions of operation of the CMOS inverter, the
state of each transistor in each region is shown in Table
Summary of CMOS Inverter Operation


❑ In region A,
o the nMOS transistor is OFF so the pMOS
transistor pulls the output to VDD
❑ In region B,
o the nMOS transistor starts to turn ON,
pulling the output down
❑ In region C,
o both transistors are in saturation
o Notice in region C ,
o ideal transistors are only for Vin = VDD/2
o and the slope of the transfer curve is – ∞ in this
region, corresponding to infinite gain
o Real transistors have finite output resistances on
account of channel length modulation and thus
have finite slopes over a broader in this region

❑ In region D,
o the pMOS transistor is partially ON
❑ In region E,
o the pMOS it is completely OFF, leaving
the nMOS transistor to pull the output
down to GND
Notice,
➢ that the inverter’s current
consumption is ideally zero, neglecting
leakage, when the input is within a
threshold voltage of the VDD or GND
rails.
➢ This feature is important for low-power
operation


Case Study :
❑ The graphical representation shows simulation
results of an inverter from a 65 nm process.
o The pMOS transistor is twice as wide as the
nMOS transistor to achieve approximately equal
betas.
o Simulation matches the simple models reasonably
well, although the transition is not quite as steep
because transistors are not ideal current sources
in saturation.
o The crossover point where Vinv = Vin = Vout is
called the input threshold.
o Because both mobility and the magnitude of the
threshold voltage decrease with temperature for Simulated CMOS
nMOS and pMOS transistors, the input threshold inverter DC
of the gate is only weakly sensitive to temperature. characteristic

Story Time
‘Mullah and the

Donkey’

Story Time
Logic is –
‘Proven it keeps you limited,
Unproven it keeps in a limited
sphere of Understanding’


1. If the n-MOS and p-MOS of the CMOS inverters are interchanged

the output is measured at:
a) Source of both transistor
b) Drains of both transistor
c) Drain of n-MOS and source of p-MOS
d) Source of n-MOS and drain of p-MOS
2. What will be the effect on output voltage if the positions of n-

MOS and p-MOS in CMOS inverter circuit are exchanged?
a) Output is same
b) Output is reversed
c) Output is always high
d) Output is always low

3. In the CMOS inverter the output voltage is measured across:

a) Drain of n-MOS transistor and ground
b) Source of p-MOS transistor and ground
c) Source of n-MOS transistor and source of p-MOS transistor
d) Gate of p-MOS transistor and Gate of n-MOS transistor
4.The switching threshold voltage VTH for an ideal inverter is equal

to:
a) (VDD-VOL)/2
b) VDD
c) (VDD)/2
d) 0

5. In latch-up condition, parasitic component gives rise to

__________ conducting path.
a) low resistance
b) high resistance
c) low capacitance
d) high capacitance
6. If p-transistor is conducting and has small voltage between

source and drain, then it is said to work in ________
a) linear region
b) saturation region
c) non saturation resistive region
d) cut-off region

1. a) Source of both transistor

2. b) Output is reversed
3. a) Drain of n-MOS transistor and
ground
4. c) (VDD)/2
5. a) low resistance
6. c) non saturation resistive region


Beta Ratio Effects
❑ For βp = βn,
o the inverter threshold voltage Vinv is VDD/2.
o This may be desirable because it maximizes noise margins and
allows a capacitive load to charge and discharge in equal times by
providing equal current source and sink
o Inverters with different beta ratios r = βp/βn are called skewed
inverters
– If r > 1, the inverter is HI-skewed
– If r < 1, the inverter is LO-skewed
– If r = 1, the inverter has normal skew or is unskewed

Beta Ratio Effects
❑ A HI-skew inverter,
o has a stronger pMOS transistor
o if the input is VDD /2
➢ the output will be greater than VDD /2
➢ In other words,
✓ the input threshold must be higher than for an unskewed
inverter.
❑ A LO-skew inverter,
o has a weaker pMOS transistor
o thus a lower switching threshold

Beta Ratio Effects
❑ The graphical representation
explores the impact of skewing the
beta ratio on the DC transfer
characteristics.
❑ The beta ratio is changed, the
switching threshold moves.
o The output voltage transition
remains sharp.
o Gates are usually skewed by
adjusting the widths of Transfer characteristics of
transistors while maintaining skewed inverters
minimum length for speed


Beta Ratio Effects
❑ The inverter threshold can also be computed analytically. If the long
channel models for saturated transistors are valid:
❑ By setting the currents to be equal and opposite, we can solve for Vinv as
a function of r:


Beta Ratio Effects
❑ In the limit that the transistors are fully velocity saturated, shows
❑ Redefining, r = Wp vsat-p / Wn vsat-n, we can again find the inverter

threshold


Beta Ratio Effects
❑ In case if,
Vtn = –Vtp and r = 1, Vinv = VDD /2 as expected
o velocity saturated inverters are more sensitive to skewing because
their DC transfer characteristics are not as sharp
Note:
❑ DC transfer characteristics of other static CMOS gates can be
understood by collapsing the gates into an equivalent inverter.
o Series transistors can be viewed as a single transistor of greater
length.
o If only one of several parallel transistors is ON, the other transistors
can be ignored.
o If several parallel transistors are ON, the collection can be viewed as
a single transistor of greater width.

Noise Margin
❑ Noise margin is closely related to the DC voltage characteristics
o This allows you to determine the allowable noise voltage on the input
of a gate so that the output will not be corrupted
o The noise margin (or noise immunity) uses two parameters,
✓ the LOW noise margin, NML
✓ the HIGH noise margin, NMH
❑ NML is defined as,
o the difference in maximum LOW input voltage recognized by the
receiving gate and the maximum LOW output voltage produced by
the driving gate.
Where,
VIL = maximum LOW input voltage
VOL = maximum LOW output voltage


Noise Margin
❑ NMH is defined as,
o the difference between the minimum HIGH output voltage of the
driving gate and the minimum HIGH input voltage recognized by the
receiving gate
Where,
VIH = minimum HIGH input voltage
VOH = minimum HIGH output voltage
Fig. Noise Margin Definitions


Noise Margin
❑ Inputs between VIL and VIH
are said to be in the
indeterminate region or
forbidden zone and do not
represent legal digital logic
levels.
❑ Therefore, it is generally
desirable to have VIH as Fig. Noise Margin Definitions
close as possible to VIL and
➢ This implies that the transfer
for this value to be midway
characteristic should switch
in the “logic swing,” VOL to
abruptly;
VOH.
➢ that is, there should be high
gain in the transition region


Noise Margin
❑ To calculating noise margins,
– the transfer characteristic of the inverter
and the definition of voltage levels VIL,
VOL, VIH, and VOH are shown in Figure.
– Logic levels are defined at the unity
gain point where the slope is –1.
• This gives a conservative bound on the
worst case static noise
❑ For the inverter shown,
– the NML is 0.46 VDD while the NMH is 0.13
VDD.
– the output is slightly degraded when the
input is at its worst legal value; this is called
noise feedthrough or propagated noise. Fig. CMOS Inverter Noise
Margins

Noise Margin
❑ If either NML or NMH for a gate are too small,
o the gate may be disturbed by noise that occurs on the inputs
❑ An unskewed gate has equal noise margins,
o which maximizes immunity to arbitrary noise sources
❑ If a gate sees more noise in the high or low input state,
o the gate can be skewed to improve that noise margin at the expense
of the other
❑ Note that,
o if |Vtp| = Vtn
➢ then NMH and NML increase as threshold voltages are increased

❑ Often, noise margins are compromised to improve speed


Noise Margin
❑ DC analysis,
o gives the static noise margins specifying the level of noise that a gate
may see for an indefinite duration
o Larger noise pulses may be acceptable if they are brief;
o these are dynamic noise margins specified by a maximum amplitude as a
function of the duration
o But, there is no simple amplitude-duration product that conveniently
specifies dynamic noise margins
❑ Trade-off,
o Noise sources tend to scale with the supply voltage, so noise margins are best
given as a fraction of the supply voltage.
❑ Case Study:
o A noise margin of 0.4 V is quite comfortable in a 1.8 V process, but marginal
in a 5 V process.

Propagation Delay (tp)
❑ tp – measures speed of output reaction to input change
tp = ½(tpf + tpr)
tpf , Fall propagation delay,
o time for output to fall by 50%
o reference to input change by 50%
tpr, Rise propagation delay,
o time for output to rise by 50%
o reference to input change by 50%
❑ Ideal expression (if input is step change), Propagation delay measurement:
tpf = ln(2) τn and tpr = ln(2) τp -from time input reaches 50% value
-to time output reaches 50% value
❑Total Propagation Delay ,
tp = 0.35( τn + τp )

1. Noise Margin is :
a) Amount of noise the logic circuit can withstand
b) Difference between VOH and VIH
c) Difference between VIL and VOL
d) All of the Mentioned
2. The Lower Noise Margin is given by:
a) VOL – VIL
b) VIL – VOL
c) VIL ~ VOL(Difference between VIL and VOL, depends on which one is
greater)
d) All of the Mentioned
3. The Higher Noise Margin is given by:
a) VOH – VIH
b) VIH – VOH
c) VIH ~ VOH(Difference between VIH and VOH, depends on which one is
greater)
d) All of the mentioned
1. d) All of the Mentioned

2. b) VIL – VOL
3. a) VOH – VIH

Static CMOS – Pseudo - nMOS

❑ Figure (a) shows a pseudo-nMOS inverter
❑ Neither high-value resistors nor depletion mode transistors are readily
available as static loads in most CMOS processes
❑ Instead, the static load is built from a single pMOS transistor that has its gate
grounded so it is always ON.
❑ The DC transfer characteristics are derived by finding Vout for which
Idsn = |Idsp| for a given Vin, as shown in Figure (b–c) for a 180 nm process.


❑ The beta ratio affects the shape of
the transfer characteristics and the
VOL of the inverter
❑ Larger relative pMOS transistor sizes

offer faster rise times but less sharp
transfer characteristics
❑ Figure (d) shows that when the

nMOS transistor is turned on, a
static DC current flows in the circuit.


❑ Figure below shows several pseudo-nMOS logic gates.
❑ The pulldown network is like that of an ordinary static gate, but the pullup
network has been replaced with a single pMOS transistor that is grounded
so it is always ON.
❑ The pMOS transistor widths are selected to be about 1/4 the strength (i.e.,
1/2 the effective width) of the nMOS pulldown network as a compromise
between noise margin and speed; this best size is process-dependent, but is
usually in the range of 1/3 to 1/6

❑ To calculate the logical effort of pseudo-nMOS gates, suppose a
complementary CMOS unit inverter delivers current I in both rising and
falling transitions.
❑ For the widths shown,
o the pMOS transistors produce I/3 and the nMOS networks produce
4I/3.
o The logical effort for each transition is computed as the ratio of the
input capacitance to that of a complementary CMOS inverter with
equal current for that transition.
❑ For the falling transition,
o the pMOS transistor effectively fights the nMOS pulldown
o The output current is estimated as the pulldown current minus the
pullup current,
(4I/3 – I/3) = I
❑ So, will compare each gate to a unit inverter to calculate gd.


Example,
o The logical effort for a falling transition of the pseudo-nMOS inverter is
the ratio of its input capacitance (4/3) to that of a unit complementary
CMOS inverter (3),
➢ i.e., 4/9. gu is three times as great because the current is 1/3 as
much
❑ The parasitic delay is also found by counting output capacitance and
comparing it to an inverter with equal current.
Example,
❑ The pseudo-nMOS NOR has 10/3 units of diffusion capacitance as
compared to 3 for a unit-sized complementary CMOS inverter,
❑ so its parasitic delay pulling down is 10/9.
❑ The pullup current is 1/3 as great, so the parasitic delay pulling up
is 10/3.


❑ pseudo-nMOS is slower on average than static CMOS for NAND
structures.
❑ pseudo-nMOS works well for NOR structures.
✓ The logical effort is independent of the number of inputs in wide NORs, so
pseudo-nMOS is useful for fast wide NOR gates or NOR-based structures like
ROMs and PLAs when power permits.
o Pseudo-nMOS gates will not operate correctly

if VOL > VIL of the receiving gate.
o This is most likely in the SF (SLOW FAST)
design corner where nMOS transistors are
weak and pMOS transistors are strong.
o Designing for acceptable noise margin in the SF
corner forces a conservative choice of weak
pMOS transistors in the normal corner.
Fig. Replica biasing
o A biasing circuit can be used to reduce of pseudo-nMOS gates
process sensitivity, as shown in Figure.

o The goal of the biasing circuit is to create a
Vbias that causes P2 to deliver 1/3 the
current of N2, independent of the relative
mobilities of the pMOS and nMOS
transistors.
o Transistor N2 has width of 3/2 and hence
produces current 3I/2 when ON.
o Transistor N1 is tied ON to act as a current
source with 1/3 the current of N2, i.e., I/2.
o P1 acts as a current mirror using feedback to
establish the bias voltage sufficient to provide
equal current as N1, I/2. Fig. Replica biasing
of pseudo-nMOS gates
o The size of P1 is noncritical so long as it is
large enough to produce sufficient current
and is equal in size to P2. Now, P2 ideally
also provides I/2.

❑ when A is low,
✓ the pseudo-nMOS gate pulls up with a
current of I/2
❑ When A is high,
❑ the pseudo-nMOS gate pulls down with
an effective current of (3I/2 – I/2) = I.
❑ To first order,
o this biasing technique sets the relative
currents strictly by transistor widths,
independent of relative pMOS and nMOS
Fig. Replica biasing
mobilities
❑ Such replica biasing permits the 1/3 current
ratio rather than the conservative 1/4 ratio,
resulting in lower logical effort


❑ The bias voltage Vbias can be distributed to multiple
pseudo-nMOS gates.
❑ Ideally, Vbias will adjust itself to keep VOL
constant across process corners
❑ Unfortunately,
❑ the currents through the two pMOS transistors
do not exactly match because their drain voltages Fig. Replica biasing
are unequal, so this technique still has some
process sensitivity.
❑ Note :
❑ that this bias is relative to VDD, so any noise on
either the bias voltage line or the VDD supply rail
will impact circuit performance
❑ Turning off the pMOS transistor can reduce power
when the logic is idle or during IDDQ (Direct Drain Fig. Pseudo nMOS
Quiescent Current) test mode as shown in Figure Gate with Enabled
Pullup

1. Four cars come to a four way stop, all coming from a

different direction. They can’t decide who got there
first, so they all go forward at the same time. They do
not crash into each other, but all four cars go. How is
this possible?
2. An elevator is on the ground floor. There are four
people in the elevator including me. When the lift
reaches the first floor, one person gets out and three
people get in. The lift goes up to the second floor, 2
people get out, 6 people get in. It then goes up to the
next floor up, no-one gets out but 12 people get in.
Halfway up to the next floor up the elevator cable
snaps, it crashes to the floor. Everyone else dies in
the elevator except me. How did I survive?
Answers:
1. They all made right hand turns
2. I got off on the first floor

Dynamic CMOS Logic Circuits

❑ Ratioed circuits reduce the input capacitance by replacing the
pMOS transistors connected to the inputs with a single resistive
pullup.
➢ The drawbacks of ratioed circuits include,
– slow rising transitions,
– contention on the falling transitions,
– static power dissipation, and
– a nonzero VOL
❑ Dynamic circuits by-pass these drawbacks by,

❑ using a clocked pullup transistor rather than a pMOS that is
always ON


❑ Figure below compares (a) static CMOS, (b) pseudo-nMOS, and (c)
dynamic inverters.
Precharge and Evaluation of

Dynamic Gates
❑ Dynamic circuit operation is divided into two modes, as shown in Figure
❑ During precharge,
o the clock ø is 0, so the clocked pMOS is ON
o initializes the output Y high.
❑ During evaluation,
o the clock is 1 and the clocked pMOS turns OFF.
o the output may remain high or may be discharged low through the
pulldown network.

❑ Dynamic circuits are the fastest commonly used circuit family because,
– they have lower input capacitance and no contention during switching
– have zero static power dissipation
❑ Dynamic circuits,
Fig. Dynamic
o require careful clocking, Inverters
o consume significant dynamic power, and
o are sensitive to noise during evaluation
❑ In Figure (c),
✓ if the input A is 1 during precharge,
o contention will take place because both the
pMOS and nMOS transistors will be ON.
✓ When the input cannot be guaranteed to be 0 during
precharge,
o an extra clocked evaluation transistor can be
added to the bottom of the nMOS stack to avoid
contention as shown in Figure Fig. Footed dynamic
Inverter
o The extra transistor is sometimes called a foot.

❑ Figure (A), shows generic footed and
unfooted gates
❑ Figure (B) estimates the falling logical
effort of both footed and unfooted
dynamic gates.
Fig.(A)Generalized footed and
Fig. (B)Catalog of Dynamic Gates unfooted dynamic gates


❑ The pulldown transistors’ widths are chosen to give unit resistance.
❑ Precharge occurs while the gate is idle and often may take place more
slowly.
o Therefore, the precharge transistor width is chosen for twice unit resistance.
➢ This reduces the capacitive load on the clock and the parasitic capacitance
at the expense of greater rising delays.
Fig. Catalog of Dynamic Gates


❑ The logical efforts are very low.
✓ Footed gates have higher logical effort than their unfooted
counterparts but are still an improvement over static logic.
❑ In practice, the logical effort of footed gates is better than predicted
because velocity saturation means series nMOS transistors have less
resistance than we have estimated.


❑ Logical efforts are also slightly better than predicted because there is no
contention between nMOS and pMOS transistors during the input
transition.
❑ The size of the foot can be increased relative to the other nMOS
transistors to reduce logical effort of the other inputs at the expense of
greater clock loading.


❑ Logical efforts are also slightly better than predicted because there is no
contention between nMOS and pMOS transistors during the input
transition.
❑ The size of the foot can be increased relative to the other nMOS
transistors to reduce logical effort of the other inputs at the expense of
greater clock loading.


❑ Like pseudo-nMOS gates,
✓ dynamic gates are particularly well suited to wide NOR functions or
multiplexers because the logical effort is indepen-dent of the number
of inputs.
✓ the parasitic delay does increase with the number of inputs because
there is more diffusion capacitance on the output node.
❑ Characterizing the logical effort and parasitic delay of dynamic gates is
tricky because,
❑ the output tends to fall much faster than the input rises, leading to
potentially misleading dependence of propagation delay on fanout


❑A fundamental difficulty with dynamic circuits is the monotonicity
requirement. While a dynamic gate is in evaluation, the inputs must be
monotonically rising.
❑ That is,
✓ the input can start LOW and remain LOW, start LOW and rise
HIGH, start HIGH and remain HIGH, but not start HIGH and fall
LOW.
Monotonicity Problem


❑ Below Figure shows waveforms for a footed dynamic inverter in which the input
violates monotonicity.
o During precharge, the output is pulled HIGH.
❑ When the clock rises,
o the input is HIGH so the output is discharged LOW through the pulldown
network, as that happen in an inverter.
❑ The input later falls LOW,
❑ turning off the pulldown network
❑ the precharge transistor is also OFF so the output floats, staying LOW rather
than rising as it would in a normal inverter
❑ The output will remain low until the next precharge step
❑ The inputs must be monotonically rising for the dynamic gate to compute the
correct function
Monotonicity Problem


❑ the output of a dynamic gate begins HIGH and monotonically falls LOW during
evaluation.
❑ This monotonically falling output X is not a suitable input to a second dynamic
gate expecting monotonically rising signals, as shown in Figure below
❑ Dynamic gates sharing the same clock cannot be directly connected. This problem
is often overcome with domino logic.
Incorrect Connection Of Dynamic Gates


Domino Logic
❑ The monotonicity problem can be solved
by placing a static CMOS inverter between
dynamic gates, as shown in Figure (a).
This converts the monotonically

falling output into a monotonically
rising signal suitable for the next
gate, as shown in Figure (b). The
dynamic-static pair together is called
a domino gate, because,
o precharge resembles setting up a
chain of dominos and evaluation
causes the gates to fire like
dominos tipping over, each
triggering the next

Domino Logic
❑ A single clock can be used to
precharge and evaluate all the
logic gates within the chain. The
dynamic output is,
❑ monotonically falling during
evaluation, so the static inverter
output is monotonically rising.
❑ Therefore, the static inverter is
usually a HI-skew gate to favor
this rising output.
❑ Observe that,
❑ precharge occurs in parallel,
but evaluation occurs
sequentially


Domino Logic
❑ The symbols for the dynamic NAND, HI-skew inverter, and domino AND
are shown in Figure below figure (c),
❑ More complex inverting static CMOS gates such as NANDs or NORs can
be used in place of the inverter.
o This mixture of dynamic and static logic is called compound
domino.


Domino Logic
For Example,
❑ Figure (d), shows an 8-input domino multiplexer built from two 4-input
dynamic multiplexers and a HI-skew NAND gate.
o This is often faster than an 8-input dynamic mux and HI-skew
inverter because, the dynamic stage has less,
o diffusion capacitance and
o parasitic delay
Fig. (d) Domino gate using logic in

static CMOS stage


Domino Logic
❑ Domino gates are inherently noninverting,
o while some functions like XOR gates necessarily require inversion.
❑ Three methods of addressing this problem include,
o pushing inversions into static logic,
o delaying clocks, and
o using dual-rail domino logic.
❑ In many circuits including arithmetic logic units (ALUs), the necessary XOR gate
at the end of the path can be built,
o with a conventional static CMOS XOR gate driven by the last domino circuit
❑ the XOR output no longer is monotonically rising and thus cannot directly
drive more domino logic
❑ A second approach is to directly cascade dynamic gates without the static CMOS
inverter, delaying the clock to the later gates to ensure the inputs are monotonic
during evaluation.
❑ This is commonly done in content-addressable memories (CAMs) and NOR-
NOR PLAs

Dual-Rail Domino Logic
❑ Dual-rail domino gates encode each signal with a pair of wires.
❑ The input and output signal pairs are denoted with _h and _l, respectively as
shown in table below.
– The _h wire is asserted to indicate that the output of the gate is
“high” or 1.
– The _l wire is asserted to indicate that the output of the gate is “low”
or 0.
❑ When the gate is precharged, neither
_h nor _l is asserted.
❑ The pair of lines should never be
both asserted simultaneously during
correct operation.
Dual-rail Domino Signal Encoding


❑ Dual-rail domino gates accept both true and complementary inputs and
compute both true and complementary outputs, as shown in Figure (a).
❑ Dual-rail domino is a complete logic family
in that it can compute all inverting and
noninverting logic functions.
o it requires more area, wiring, and
power.
❑ Dual-rail structures also lose the efficiency
of wide dynamic NOR gates because they
require complementary tall dynamic NAND
stacks.


❑ Dual-rail domino signals not only the result of a computation but also
indicates when the computation is done.
o Before computation completes, both rails are precharged
o When the computation completes, one rail will be asserted
o A NAND gate can be used for completion detection, as shown in
Figure below
o This is particularly useful for

asynchronous circuits
Fig. Dual-rail
domino gate
with completion
detection


NP Domino
❑ Another variation on domino is shown in Figure (a),
o The HI-skew inverting static gates are replaced with pre-discharged
dynamic gates using pMOS logic.


NP Domino
❑ For example, a footed dynamic p-logic NAND gate is shown in
Figure (b),
❑ When ø is 0, the first and third stages precharge high while the
second stage pre-discharges low.
❑ When ø rises, all the stages evaluate.


NP Domino
❑ Domino connections are possible, as shown in Figure (c).
o The design style is called NP Domino or NORA Domino (NO RAce)


NP Domino
❑ NP Domino or NORA Domino (NO RAce) - has two major drawbacks
o The logical effort of footed p-logic gates is generally worse than that
of HI-skew gates (e.g., 2 vs. 3/2 for NOR2 and 4/3 vs. 1 for NAND2).
o NORA is extremely susceptible to noise.
➢ In an ordinary dynamic gate, the input has a low noise margin
(about Vt ), but is strongly driven by a static CMOS gate.
➢ The floating dynamic output is more prone to noise from
coupling and charge sharing, but drives another static CMOS
gate with a larger noise margin.
❑ Note: NORA,
o the sensitive dynamic inputs are driven by noise prone dynamic outputs.
o these drawbacks and the extra clock phase required, there is little reason to
use NORA.

BICMOS Logic
• BICMOS Logic is typically comprised of CMOS
logic feeding a bipolar drive
– 2-input NAND is shown below
• N-tree pull down logic must be inserted twice:
– once in the actual CMOS logic circuit
– again in the base current path for the pull-
down NPN transistor (N1 and N2)
• N3 holds the pull-down NPN off when the
output is pulling high
• The circuit in (a) contains a VBE drop on the
output up-level (VOH = VDD – VBE) VOL is a
VCEsat which is a few hundred mV above
ground
• Feedback provided by the inverter in (b) pulls
output VOH all the way to VDD

MODULE 1
INTRODUCTION TO CMOS VLSI CIRCUITS

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SRI RAMAKRISHNA ENGINEERING COLLEGE

[Educational Service : SNR Sons Charitable Trust]

Department of Electronics and Communication Engineering

20EC214 & DIGITAL CMOS VLSI CIRCUITS

Vision of the College:

31-01-2023 Digital CMOS VLSI Circuits 2

Vision of the Department:

Mission of the Department:

The Program Educational Objective (PEOs) of ECE is

Graduates of Electronics and Communication Engineering

PSO1: Specify, design, implement and test digital and analog

PSO2: Architect and specify the analog and digital communication

PSO3: Understand and specify the components of RF/Wireless

31-01-2023 Digital CMOS VLSI Circuits 5

On successful completion of the course, students

31-01-2023 Digital CMOS VLSI Circuits 6

31-01-2023 Digital CMOS VLSI Circuits 7

Combinational Circuits: CMOS Inverter - DC

31-01-2023 Digital CMOS VLSI Circuits 9

31-01-2023 Digital CMOS VLSI Circuits 10

31-01-2023 Digital CMOS VLSI Circuits 11

❑ When any of the inputs are 0,

31-01-2023 Digital CMOS VLSI Circuits 13

31-01-2023 Digital CMOS VLSI Circuits 14

31-01-2023 Digital CMOS VLSI Circuits 17

31-01-2023 Digital CMOS VLSI Circuits 18

Take Two minutes to Answer the Question

31-01-2023 Digital CMOS VLSI Circuits 19

If any input is high, the output is pulled low through the

31-01-2023 Digital CMOS VLSI Circuits 20

‘Boost Your Brain Power’

31-01-2023 Digital CMOS VLSI Circuits 21

Pass transistor strong

31-01-2023 Digital CMOS VLSI Circuits 24

Pass transistor strong and degraded outputs

❑ When an nMOS or pMOS is used alone as an imperfect switch,

o call it a PASS TRANSISTOR

31-01-2023 Digital CMOS VLSI Circuits 25

❑ In a circuit where only a 0 or a 1 has to be passed,

31-01-2023 Digital CMOS VLSI Circuits 27

31-01-2023 Digital CMOS VLSI Circuits 28

31-01-2023 Digital CMOS VLSI Circuits 29

31-01-2023 Digital CMOS VLSI Circuits 30

31-01-2023 Digital CMOS VLSI Circuits 31

How To Face Hardships In Life?

31-01-2023 Digital CMOS VLSI Circuits 32

Moral of the Story

Sometimes both true and complementary enable signals,

are drawn explicitly, while sometimes only EN is shown.

31-01-2023 Digital CMOS VLSI Circuits 35

31-01-2023 Digital CMOS VLSI Circuits 36

31-01-2023 Digital CMOS VLSI Circuits 37

31-01-2023 Digital CMOS VLSI Circuits 39

31-01-2023 Digital CMOS VLSI Circuits 40

(a) CMOS Compound gate (b) Inverting Multiplexer

31-01-2023 Digital CMOS VLSI Circuits 41

31-01-2023 Digital CMOS VLSI Circuits 43