VISHNU INSTITUTE OF TECHNOLOGY

(Autonomous)
Vishnupur, Bhimavaram

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LESSON PLAN

Name of the Faculty: K. RAMESH CHANDRA Academic Year: 2022-2023

Designation: Associate Professor Branch: AIML
Department: ECE Year & Semester: I – II
Subject: Digital Logic Design Regulation: R-20

Text Books Required for the Subject

S. No Name of the Text Book Author(s) Name

T1 Switching Theory and Logic design Hill and Peterson
T2 Switching Theory and Logic design A.Anand Kumar
T3 Digital Design Mano
T4 Modern Digital Electronics RP Jain

S.No Hour Topics to be Covered Remarks

UNIT –I - REVIEW OF NUMBERS & CODES
1 1 Introduction to DLD, Importance, Applications T3
2 1 Representation of numbers of radix T1,T2
3 1 Conversion from one radix to another radix T1,T3
Complements and r’s complement of signed
4 1 T1,T2,T4
numbers, Problems
4-bit codes, BCD, Excess-3 code, 2421, 8421,
5 2 T1,T3
Gray code
6 2 Arithmetic addition and subtraction T1,T2
7 2 problems T1,T2
UNIT – II – BOOLEAN THEOREMS
&MINIMIZATION TECHNIQUES
8 1 Boolean theorems T1,T2
Minimization of logic functions using Boolean
9 2 theorems. Principle of complementation and T1,T2
duality, De-morgans theorems
10 1 Standard SOP and POS forms T1,T3
11 1 Standard POS forms, Problems T1,T3
Basic logic operations-NOT, OR, AND, Universal
12 1 T1,T4
building blocks, EX-OR, EX-NOR-gates
Standard POS forms Problems. NAND-NAND
13 2 T1,T3
Realizations.
14 2 NOR-NOR Realizations. T1,T3
 Minimization of switching functions using K-map
15 2 for 3-variables, 4-variables. Minimization of T1,T4
switching functions using K-map for 5 variables.
16 1 Problems T1,T4
17 1 Problems T1,T4
UNIT – III
COMBINATIONAL LOGIC CIRCUITS
Design of half adder and full adder. Half
18 2 subtractor, Full subtractor, applications of full T1
adders,4-bit binary subtractor
19 1 Adder-subtractor circuit, BCD adder circuit. T1,T2
20 1 Excess-3 adder circuit, Look-a-head adder circuit T1,T2, T3,T4
21 2 Multiplexer, Higher order Multiplexing, problems T1,T2,T4
Realization of Boolean functions using
22 2 T1,T2,T3,T4
Multiplexers, problems
23 1 Demultiplexer, Higher order demultiplexing T1,T2,T3,T4
24 1 Encoder, Priority Encoder T1,T2,T3,T4
25 2 Design of decoder, problems T1,T2,T4
Realization of Boolean functions using decoders,
26 2 T1,T2,T4
4-bit digital comparator
27 1 problems T1,T2,T4
UNIT – IV – Synchronous Sequential logic
Classification of sequential circuits (synchronous
28 1 T3
and asynchronous)
29 1 Basic Flip-Flops, truth tables T3
Excitation tables of NAND RS-Latch, NOR RS-
Latch, RS-Flip-Flop. Excitation tables of JK-flip-
30 2 T3
flop, T-flip-flop, D- flip-flop with reset and clear
terminals
Conversion from one flip-flop to flip-flop, Practice
31 2 T3
class
32 1 Practice class
33 1 Test
UNIT-V-Registers and Counters
34 1 Registers T3
35 2 Shift Register T3
Bi-directional shift register, Universal shift
36 2 T3
register, problems
37 1 Design of Ripple Counters T3
38 1 Design of Synchronous Counters T3
Design of Johnson, Ring Counters. Design of
39 2 T3
Registers-Buffer register, Problems
40 1 Practice class

Faculty HOD Principal