DEPARTAMENTO DE ENGENHARIA

ELECTROTÉCNICA
2º TESTE DE ELECTRÓNICA III
17 DE MAIO DE 2017 – SALAS 201 E 202 ED. IV
16H30-17H45
PROBLEM 1: A/D CONVERTERS

Stage 2 Stage 1 Stage 0

vres2 vres0
Sample

Sample

Sample
& Hold

& Hold

& Hold
vin + 2 + 2
- - v
vDAC2 DAC1
DAC

DAC
ADC

ADC

ADC
clk 2 2 clk 2 2 clk 2

dout2 dout1 dout0

Fig. 1
Consider the pipeline ADC with 3 stages whose block diagram is depicted above. The input voltage range of the ADC is
 Vref Vref 
 ,  . This ADC has digital correction (Vref=1 V).
 2 2 
(Carefully justify all the answers)

a) What is the overall resolution of the ADC?

b) What is the maximum SNR of this ADC?
c) What is the latency of this ADC?
d) Draw the circuit of the 2-bit ADC inside each stage and plot its transfer function (Dout(vin))
e) Plot the transfer function of a stage (Vres(vin)), according to the block diagram.

F1
-
2C C 2C Vout
+0.5Vref
F2 F1 F2 F1 F1 F2 +

-0.5Vref b1 b1 b0 b0

vin

Fig. 2
f) Calculate the output voltage of the circuit shown in Fig. 2 at the end of phase F2 and show that this circuit
has the same transfer function calculated in e) if the control bits are determine by the ADC of d) (assume
ideal amplifier)
g) Calculate the 3-bit digital output code of the ADC and all the internal voltages values, when the input
voltage (vin) is equal to 0.2V.
h) Considering that the comparator, with a reference voltage of 0.25V in the first stage, has an offset voltage
of -70mV, repeat the previous question.