1

a) Resolution=1+1+1=3 bits

b) v lsb =
V ref
2
nbits
=
1
2
3
=0.125V

SNRmax v i n=
V ref
2 
=6.02⋅nbits1.76=19.82 dB

c) SNRmax =6.02⋅nbits1.76=36 dB ⇔nbits=5.7 nbits=6

d) vx2 R R
ideal opamp  V =V  ⇔v i n=v x2⋅
R
v res2⋅
R
⇔
- vres2 RR RR
vin + ⇔ v res2 =2⋅vi nv x2

{ }
Vref b2 V ref
e) 2 vx2 if b2 =1 V ref V ref
v x2= 2 = b2⋅V ref v res2 =2⋅v i n b2⋅V ref
-Vref b2 V ref 2 2
2 if b2=0
2
f)
1 0
0.5 V 0.5 V R R 0.5 V R R
vres2 -0.5 V vres1 vin0
- -

+
-
-0.5 V 0 0.1 V -0.5 V 1 -0.3 V + S&H
+ -0.3 V -0.1 V C0

vin 0.1 V vin1 clk b0

+

+
-

S&H S&H
C2 -0.3 V C1 0

clk b2 clk b1
1 0

g)
0 1
0.5 V -0.5 V R R 0.5 V 0.5 V R R
- vres2 - vres1 vin0 +
S&H -
-0.5 V 1 0.1 V + 0.7 V -0.5 V 0 0.7 V +
0.9 V C0

vin 0.1 V vin1 clk b0

+

+
-

S&H S&H
C2 0.7 V C1 1

clk V =0.12V clk

b2 offset b1
0 1

h) The conversion time of pipeline ADC is given by the comparator time and the residue amplification time. The
digital output data is ready after a certain number of clock cycles (latency). The data is available in each clock
cycle. The number of components grows linearly with the ADC resolution. The pipeline architecture is modular
which results in a design that can be easily optimized
The conversion time of a flash ADC is given by the comparator time and the digital data is immediately available.
The number of components grows exponentially with the ADC resolution.

Advantages of a pipeline ADC: smaller cost and power dissipation (smaller number of components), this specially
important for resolution larger than 8 bits. It can use digital correction to improve comparator offset errors.
Disadvantages of a pipeline ADC: longer conversion time (2x to 4x longer)

i) At the end of the 1st half of the 1st clock cycle the first stage produces b2. During the 2nd half of the 1st clock the first
stage calculates the residue voltage. At the end of the 2nd half of the 1st clock cycle the second stage produces b1.
During the 1st half of the 2nd clock the second stage calculates the residue voltage. At the end of the 1st half of the 2nd
clock cycle the last stage produces b0. Therefore the data latency is 1.5 clock cycles.
2
a) Itotal IF RF V ref V ref V ref
I 2= I 3= I 4=
- R2 R3 R4
b2 b1 b0 Vout
V out
I total=I 2⋅b2I 3⋅b1I 4⋅b0 I F=
+ RF
I2 R2 I3 R3 I4 R4
Vref
I total=I F ⇔V out =V ref⋅RF⋅
 b 2 b1 b0
 
R2 R3 R4 
b) 7⋅V ref =V ref⋅R F⋅
1
 
1
 1
R2 R3 R4 ⇔ R F =4⋅R 
R2=R ; R3=2⋅R ; R 4=4⋅R

c) V out =V ref⋅ 4⋅b22⋅b1b0 

b2
0
b2
0
b0
0
Vout
0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7

d) e) V out =V ref⋅

 4
1.05
⋅b 2
4

⋅b b =3.81⋅b22.11⋅b1b 0
2×0.95 1 0

b2 b2 b0 Vout DNL INL

0 0 0 0 0
V out codeV out 0code⋅V lsb 0 0 1 1 0,01 0,01
INLcode= real

0 1 0 2,11 0,12 0,13

V lsb real
0 1 1 3,11 0,01 0,14
1 0 0 3,81 -0,29 -0,14
V out codeV out code1 1 0 1 4,81 0,01 -0,13
DNLcode= 1 1 1 0 5,91 0,12 -0,01
V lsb real
1 1 1 6,91 0,01 0

V out 7V out 0

V lsb = =0.99 V
real
7

log  Max  INLMin INL

f) linearity=resolution
log2
=31.8=4.8 bits