TEST | (OPEN BOOK) TIME: 60 Mi the following. [Give Values in Hex only] a) MOV AX, E5:[D1+BP+04,) 24/02/2016 IDNO: Name: BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI— K K BIRLA GOA CAMPUS II SEMESTER 2015-2016 (CSF241/EEEF241/INSTRF241MICROPROCESSOR PROGRAMMING AND INTERFACING MM: 40 ._ In.an 80486 processor that is working in 32-bit mode. For the instructions given below determine BI ‘Addressing Mode ‘Machine Code 2. Replace the following program segments by a single instruction of 80486. [Clarification: Each program segment achieves a certain final result. You need to give a single instruction that will achieve the same result. The single instruction needs only achieve the final result] [3+4] Program Instruction Program Instruction A mov ox{bx] B | push ax bt x15, | pushf inc xt pop ax or — ecx,Offff0000h xor ax,0001h imp x2 push ax x1: and ecx,0000fftfh pop x2: pop_ax cycles that will be executed in proper order. Q3. For the following Instructions what will be the machine cycles executed by 8086. Enter the machine Instruction Cycles Instruction Cycles: ‘A | Movsw 8 | STD ¢ | MOV WORD D | PUSH [011C,] PTR[2000%), 1000, ‘Marks on this pageaa. a6. If an 8086 processor is working at 10 MHz and the memory access time is 400ns. The number of wait states required will be _ considering an address set-up time of, 110ns, data set-up time of 40ns with a latching and buffer delays of 30ns. [2] In an 80486 processor that is working in real mode. Suppose that EAX 11112222 EX 55556666, [eox | 77778888, EBX 33334444, ESP (00003000, BP (00009999, ESI O000AAAAn iG (00008888), What will be the effect of executing the following code snippet on an 80486 processor? Fill in the table given below [8] PUSH EBP PUSHAD. POPA . POP ECK POP CX EAX ~ | ECK | EBx ESP BP ESI Write an 80486 ALP that will examine a series of memory locations storing 16-bit signed numbers. The numbers are stored starting from location loc. The program should separate the positive ‘numbers and store them in memory starting from location posi and the negative numbers in memory location starting from negi. The count of memory locations to be examined is stored in ‘entd and will not exceed 2504. The checking and the separation must be done by a sub-routine named sepd. The number to be examined should be passed to sub-routine using SI as pointer. The main program only does the initialization and looping. [22] Eg. if loc1: — -200,200,300,500,-700,900,-100 after program negi: —-200,-700,-100 post: — 200,300,500,900 [YOU CAN USE THE BLANK SPACE AT THE BACK OF THIS PAGE FOR WRITING THE PROGRAM] Marks on this pageTime: 1 Hr Date: Birla Institute of Technology and Science, Pilani- KK Birla Goa Campus Il Semester 2015-2016 CS/EEE/INSTR F241 Microprocessor Programming and Interfacing Test-2 (Open Book) 0-03-2016 MM: 40 Qu. Design an 80286 based system that has the following memory requirements: [20] 2 MB of ROM from 000000, 2 MB of ROM from £00000, 8 MB of RAM from 400000, hips available: 1 MB ROM chip 4 nos. 1 MB RAM chip 8 nos. 18138 Ano. 7432(Quad 2 i/p OR chip) 1no. Show the complete memory mapping and design the memory decoding circuit using only the chips given. All system bus signals ( MEMR’, MEMW', IOR’, IOW’ BHE’, Ac- Ars, Do~ Dss) are available. Show the memory interfacing circuit. Use absolute addressing. For memory interfacing show at least the connections to 1 even ROM chip, 1. odd ROM chip, 1 even RAM chip and 1 odd RAM chip. [Note: The ROM chips have required address and data lines, OE’, CS’ and RAM chips have required address and data lines, OE’, WE’ and CS'.] Using 8255 design a system that counts up from 01 - 99 in decimal if a switch Sp is closed. The switch Sois connected to PBy of 8255. When the switch is closed it gives a high output pulse. The ALP for 8255 should check if PBo is high, ifit is high then it should count from 01 to 99 in decimal The decimal count is displayed on two 7-segment common anode displays that are connected to Port A via 7447 (BCD to common anode seven segment converter). At the beginning while the condition of the switch is being checked 00 should be displayed on the 7-segment. The count is incremented every 0.5 seconds. When the count reaches 99, the display should be reset to 00 and the process should stop. You can assume that there is a delay routine (d_hs) is available for generating a delay of 0.5s. The starting address of 8255 is 00s. Chips available; 8255 1no. 7432(Quad 2 i/o OR chip) 2nos. Show the complete hardware interfacing to 8255 using only the chips given. The system is 8086 based. All system bus signals (MEMR’, MEMW’, |OR’, IOW’ BHE’, Ag- Ais, Do~ Dis) are available. Write the required ALP code for implementing this system. [Note : Program Port C as input port even though it is not used] [20]Birla institute of Technology and Science, Pilani- KK Birla Goa Campus li Semester 2015-2016 EEE/CS/INSTR F241/ Microprocessor Programming and Interfacing Comprehensive Examination- Part A (Open Book) Time: 60 min. Date: 6-5-2016 MM: 30 (Note: Answer Part A on the Q-Paper itself and Part B on a separate answer sheet provided.) ID No.: Nam Section Q1. Give two possible opcodes for the following instruction running on 8086: MOV AX, [2345x] BI) Q2. _Vrer+ of ADC 0808 is connected to 4.0 V and Vser — is connected to OV. What will the minimum voltage difference that can be detected using ADC 0808. [2] Q3. In 80486 DX based system 8255 is connected to data lines Do-D7. The starting address of 8255 is 30x. What will the address of Port A, Port B, Port C and the control Register? (2) Q4. How many 8259's are required for 64 Interrupt Inputs? (2) Q5. What is the maximum amount of memory required for storing the GDT? (1 Marks on this Page: aQ6. The descriptor of an 80286 Processor stored in the GDT is as follows 00 00 B1 32 00 00 3F FF, [From SB onwards] Answer the following questions with respect to this descriptor _[1+1+1+1] (i) Staring address of the Segment i Size of the segment is ‘The minimum CPL and RPL required to access this segment (iv) Is the segment code or data segment? Q7. The data 0011 1101 has to be transmitted via USB bus. Draw the NRZI encoded data pattern for the data. Assume that initially data is at high state. (4) time Q8. Write an Assembly language program segment to do the following function: JC 3FFH [3] Q9. IF INTR is raised during a DIV instruction execution and the DIV instruction results in a divide by 0 interrupt - what will be the order in which the interrupts are serviced? i Q10. if the DPL of a call gate is 10 and the RPL of the selector within the Call gate is OO — what should the minimum CPL and RPL of the selector if an application task wants to use the call gate? [1] Marks on this Page: 2Q11. Which type of cache miss is reduced in set associative caches when compared to direct-mapped caches? (1) 12. Ifthe cache access time is Sns, the access of main memory is 25ns and we require an average memory access time of 10ns. What should be the hit rate of the cache? [assuming that there is only one level of cache in the system.] [3] Q13. Write a sub-routine that can be used for transferring data from HDD to memory location using DMAC 8237. The starting address of the DMAC is 80H. The HDD uses burst transfer of upto 1K of data/burst. The starting address of memory location to which the transfer must be done is O6000H. DMA channel Ois used by HDD- HDD DREQ is active high, DACK is active low. [3] Recheck Request Marks on this Page: 3Birla Institute of Technology and Science, Pilani ~ KK Birla Goa Campus MSemester 2015-2016 EEE/CS/INSTR F241/ Microprocessor Programming and Interfacing ‘Comprehensive Examination Part B (Open Book) Recommended Time: 2Hrs Date: 6-05-2016 Mm: 60 [Note: Software Routines will not be evaluated if H/w interface is incorrect] Q1. The system to be designed is used for Automated Railway Gate. The specifications of the system are as follow: ‘* System is built around the 8086 processor which is working at a frequency of 5 MHz. + Ithas 1 MB of memory — of which 384 Kis RAM and the rest is ROM — Half of the ROM is mapped to address space starting at 0.00 00} and half it to address space starting from B 00 00y The RAM is mapped to the rest of the addresses. a) Show the complete memory mapping and design the memory interfacing circuit using only the chips given in table below. All system bus signals ( MEMR’, MEMW’, IOR’, IOW’, BHE’, Ac- Ars, Do- Dis) are available. Use Absolute Addressing. (15) Chips Available other than peripheral 1/O | Nos. 32 KROM 20 32K RAM 12 1s138 4 © Inadi n the system has 1 8259, 1 8255, 1 16550, 1 8254s. b) Show the complete I/O mapping and I/O decoding circuit using only a single decoder (15138). All system bus signals (MEMR’, MEMW’, IOR’, IOW’, BHE’, Ao- Ais, Do — Dis) are available. (Starting Address: 8255- 20y, 8254 - 40,, 16550- 30,8259 — 50,). Use Incremental Addressing. [10] R2 |@| @ % | a1 v2 |@ ev © The figure shown above gives the 2D lay-out of the railway gate system. © G1 and G2 are the two railway gates that have to be opened and closed simultaneously.d) ‘Advance warning of approach of train is provided from a remote system to the Automated Railway Gate via serial interface using 16550. Communication rate is 19,200 baud. Four bytes of data that carry the warning about approaching training is sent to 16550. Each data byte is 8-bits, with 1 stop bit and 1 bit for odd parity. 16550 must raise an interrupt to 8086 via 8259 whenever 4 bytes of data have been received. Yellow LEDs Y1 and Y2 will now glow whenever advance warning is obtained. After the advance warning - the system waits until the train reaches point P1. When the train reaches point P1 the sensing output at point P'1 goes high. This should raise an interrupt to the 8086 via 8259. The RED LEDs R1 and R2 will glow now and Y1 and Y2 will be turned off. Then 8086 closes both Gate G1 and G2. G1 and G2 are controlled by two servo systems that require a PWM input. The same PWM signal goes to both the servo systems so that they open and close synchronously. The PWM signal to open the gate is at frequency of 10 KHz with 20% duty cycle. This has to be generated using 8254. When the gate reaches the required closing position a switch mechanism (S1) available on the gate will give a high output at this point the timer should stop generating the PWM signal. When the train reaches point P2 the sensing output at point P2 goes high. This should raise an interrupt to the 8086 via 8259. All LEDs will now turn-off. Then 8086 opens both Gate G1 and G2. G1 and G2 are opened using the same PWM signal with frequency of 10 KHz but to rotate in the anti-clockwise direction a 60% duty cycle is required. This has to be generated using 8254. When the gate reaches the required opening position a switch mechanism ($2) available on the gate will give a high output at this point the timer should stop generating the PWM signal. Show all the required hardware connection for 8255 to the System Bus. Switch S1, S2 is connected to Port A of 8255. LEDS R1, R2, Y1 and Y2 are connected to lower Port C. Gate signal for 10KHz generation by 8254 will be provided by PC4, Port B is default input. Also write the ALP to initialize 8255. (5) Show all the required hardware connection for 8254 to the System Bus as well as to the sensor and interrupt. Write an ALP routine that es 8254 for generating PWM. Also give the count that will be given to each timer for 10KHz PWM with 20% and 60% duty cycle. (14) All three interrupts- interrupt from 16550, P1 and P2 are connected to 8259 IRO, IR1 and IR2 respectively. The interrupts are edge triggered and IRO is mapped to vector number 60x. ‘Automatic end of Interrupt has to be enabled and only three interrupts should be enabled. Show all the required hardware connection for 8259 to the System Bus as well as to IR inputs. Write an ALP routine that initializes 8259. [8] The 16550 has a separate crystal of 18.432MHz. Show all the required hardware connection for 16550 to the System Bus as well as null modem. Write an ALP routine that initializes 16550. 3]