Cadence® I/O Planner:

Application Note
Product Version 16.2
November 2008
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 Cadence I/O Planner: Application Note

Contents
Flow Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Library Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
OA Reference Library Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
IC Initialization and Placement into the Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Flow 1 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flow 2 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Flow Details Between FE and IOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flow Details Between IOP and SiP Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File Formats and File Management 8
Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Open Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Licensing and First Encounter Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Encounter Functionality in IOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Cross Probing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bumps (Die-Connect Point Separate from I/O Cell) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ECO (Addition/Deletion of Nets at the IC/Package Boundary) . . . . . . . . . . . . . . . . . . . . 14
Physical Die vs. Drawn Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bump Array Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bump Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RDL Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Manual Wire Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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Cadence I/O Planner

This document is for customers using Cadence's Encounter-based I/O Planning functionality
in the SiP Layout and SiP Architect products. It describes the flows, file formats, and
operations between the package environment and the IC environment to enable IC/package
co-design. In this document, references to SiP Layout also apply to SiP Architect. References
to I/O Planner (IOP), apply to the version of Encounter that is included with SiP Layout.
References to Encounter or First Encounter (FE) refer to a full version of First Encounter that
is used for full IC implementation and is not included as part of the SiP package.

This document does not provide command reference information, but does refer to some
commands that are used in the System-in-Package (SiP) design flow.

Flow Descriptions
Figure1-1 shows the data flow among these tools: SiP Layout, I/O Planner (IOP), and First
Encounter (FE). You initialize a design in FE by reading LEF library files and Verilog design
files. You send IC I/O design data from FE to SiP Layout through a Design Exchange Format
(DEF) file or an OpenAccess (OA) database. Then you return I/O design data to Encounter
from SiP Layout through a DEF file.

Library Setup
Before you can create an instance of the die and edit the die in SiP Layout, you must first read
the LEF libraries into SiP Layout, using the SiP Layout LEF Library Manager.

There are two sources for initial IC die data. One is from DEF or OA, generated by FE.
Another is the Verilog gate level netlist from the IC design. If any of these files is available,
you can create an instance of the IC in the package.

Within SiP Layout, the package environment and IOP communicate via Message Passing
System (MPS) calls. Data transfers through an OA database.

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Figure 1-1 System-in-Package Data Flow

OA Reference Library Setup

Before using SiP Layout and IOP in a co-design flow, create your OA reference libraries from
the LEF files. Follow these steps:
1. Create a Verilog file of the leaf cells in the library.

a. Load a representative Verilog netlist and LEF library into Encounter (or IOP).

b. Run this command from the Encounter console:

saveNetlist <filename> -onlyLeafCell

2. Convert the LEF files to an OA reference library using the lef2oa and
verilogAnnotate commands.
The following example shows the commands to create three OA reference libraries:
techFile, FEOAreflib, and memReflib. You can compile your LEF files into one or many
OA reference libraries.
lef2oa -lib techFile -lef gpdk090_tech_9lm.lef -DMSystem oaDMFileSys
lef2oa -lib FEOAreflib -lef io_sites.lef -DMSystem oaDMFileSys -techLib
techFile
lef2oa -lib FEOAreflib -lef gsclib090.lef -DMSystem oaDMFileSys -techLib
techFile
lef2oa -lib FEOAreflib -lef abstractFlipChip.lef -DMSystem oaDMFileSys -
techLib techFile
lef2oa -lib FEOAreflib -lef bump.lef -DMSystem oaDMFileSys -techLib techFile

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lef2oa -lib FEOAreflib -lef bump8.lef -DMSystem oaDMFileSys -techLib techFile

lef2oa -lib FEOAreflib -lef ether_jgrad.lef -DMSystem oaDMFileSys -techLib
techFile
lef2oa -lib memReflib -lef RAM2P_1024x32.lef -DMSystem oaDMFileSys -techLib
techFile
lef2oa -lib memReflib -lef RAM2P_128x16.lef -DMSystem oaDMFileSys -techLib
techFile
verilogAnnotate -refLibs FEOAreflib -verilog ./.leaf.v
verilogAnnotate -refLibs memReflib -verilog ./memLeaf.v

When you run the lef2oa command, a lib.defs file is automatically created. The
script above creates the following lib.defs file:
DEFINE techFile techFile
ASSIGN techFile libMode shared
DEFINE FEOAreflib FEOAreflib
ASSIGN FEOAreflib libMode shared
DEFINE memReflib .memReflib
ASSIGN memReflib libMode shared
DEFINE test test
ASSIGN test libMode shared

This lib.defs file must reside in your working directory. You must modify it point to your
OA reference libraries which should not be in your working directory. For this example, the
reference libraries are in the library/lef directory and the working directory is at the
same level as the library/ directory, so the lib.defs file is modified as follows:
DEFINE techFile ../library/lef/techFile
ASSIGN techFile libMode shared
DEFINE FEOAreflib ../library/lef/FEOAreflib
ASSIGN FEOAreflib libMode shared
DEFINE memReflib ../library/lef/memReflib
ASSIGN memReflib libMode shared
DEFINE test test
ASSIGN test libMode shared

IC Initialization and Placement into the Package

You can initiate the IC I/O design from two different flows. The first flow, Flow 1, in Figure 1-2,
shows the IC Verilog gate level netlist and LEF files loading into FE, which runs die
initialization, and then generates either a DEF file or an OA database for SiP to create an
instance of the die in the package.

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The second flow, Flow 2 in Figure 1-2, shows the System Connectivity Manager (SCM) and
SiP Layout loading the IC Verilog gate level netlist and building it into the system netlist. IOP
then opens to load the IC Verilog netlist. The IC physical I/O plan initializes in IOP, then
returns to SiP Layout for placement in the package.

Figure 1-2 Die Initialization Flows

Flow 1 Outline
1. IC initialization occurs within FE.
The design is written to disk in one of two formats (For flow details, see Flow Details
Between FE and IOP on page 6):
❑ Open Access
FE saves the full design into the OA database. When IOP accesses this database,
it loads the full design. This provides more design information for I/O planning, but
comes at the cost of higher memory consumption and longer run times.
❑ DEF
FE generates a DEF file with all the standard cells and nets removed from the
design. IOP sees only the I/O cells and nets, and any hard macro blocks in the
design. Run times are faster, and memory use is lower.

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2. SiP Layout adds the die to the package by creating a die symbol, places the die in the
package, and creates nets in the package that correspond to nets assigned to the IC
bumps, or wire bond I/O cells. You can assign nets imported from the IC bump
assignments to the package ball array.
3. From Sip Layout, open the IC for editing. An IOP window opens.
4. From IOP, you can:

a. Create and edit a bump array.

b. Create and edit net assignments to bumps.

c. Place I/O cells.

d. Run physical routing between I/O and bumps.

5. When you complete the edits, you can update them to the package or discard them.
If you update them to the package, the tool creates a temporary OA file, and the changes
appear in the die abstract in the package. At this point in the flow, the modifications made
in IOP have not yet been permanently saved.
6. When you save the package design in SiP Layout, the temporary OA database moves
into the original OA database.
If you discard package changes, the tool discards the IC changes.
7. When you complete all the changes to a die in IOP and package views, send the data
back to FE by writing a DEF file from IOP.
8. FE reads the DEF file and automatically merges the data to the IC database by making
incremental changes to the full IC database.

Flow 2 Outline
1. SCM or SiP Layout reads the IC Verilog netlist, creates an instance in the package
netlist, and connects it to other package components (BGA, memories, and so on).
Since there is no physical definition for the die, it is not placed in the package.
2. Open the IC for editing from SiP Layout.
An IOP window opens.
3. IOP reads the LEF libraries and Verilog netlist.
4. In the IOP window, the physical floorplan is initialized, and the rest of the flow continues
as is described above from step 4 of Flow 1.

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Flow Details Between FE and IOP

Follow these steps to generate a partial DEF file or an OA file from FE:
1. Load a full IC database in FE.
2. Write a partial IC database from FE to a DEF file with this command:
defOut -noCoreCells -netlist -layout <filename>

-or-
Create an OA database with this command: File – Save OA Design

To send modifications to the IC database back to FE from IOP, you must use DEF because
the OA reader does not support incremental updates. Create the DEF file with this command:
defOut -noCoreCells -netlist -layout <filename>

Note: if you read the IC design into IOP from a DEF file that has no core cells in it, you do
not need to use any of the options (noCoreCells, netlist, layout).

When FE reads the DEF, all bumps and RDL routes append to the full design database. To
prevent duplication of bumps and routes, you must run the defIn command as shown below:
defIn -deleteRDL -deleteBump <filename>

This causes FE to delete all the bumps and RDL routes before reading the DEF file.

Flow Details Between IOP and SiP Layout

1. Before placing an IC design in SiP Layout, you must create and load .ldf and .cml files.
This is required even if you use an OA database instead of DEF. The reason for this is
that the .cml files are the mechanism that SiP Layout uses to keep track of which
information in the OA database defines the die-connect shapes in the IC. Use the Setup
– LEF Libraries command in SiP Layout to set up your LEF files.
2. Choose Add – Co-Design Die in SiP Layout to add the co-design die to the package.
The Add Co-Design Die dialog box appears with three tabs. From the first tab you can
load a design from an OA database; from the second tab you can load a design from
DEF; and from the third tab you can load a design from a Verilog file.
From the OA Import command dialog box:

a. Select the library definition file to use, normally lib.defs, in the current working
directory.

b. Select the OA library to read the IC layout for the co-design.

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c. Select the cell from the chosen OA library for the co-design IC.

d. Select the view of the chosen cell that contains the IC layout for the co-design die.
Note that FE must have written the library, cell, and view using its saveOaDesign
command, or the co-design die will not work correctly.

e. If you select the option to load from DEF, specify the DEF input file. Then specify the
library name for the OA file used as the data exchange format between SiP Layout
and IOP. You cannot give it a name of a file that already exists. If you do, the OK
button is disabled. The cell name is taken from the DEF file, and the view name is
layout.

f. If you select the option to load from Verilog, specify the Verilog input file, then the
library and cell name of the OA file used as the data exchange format between SiP
Layout and IOP.

g. Once you specify the input and output file names, a dialog box appears. Follow the
sequence below to add the die to the package:
❍ Specify the reference designator for the co-design die.
❍ Specify the orientation, location, and rotation for the co-design die.
❍ Click Import to import the IC data from OA and add an instance of it to the
package as a co-design die.
If the import is successful, the tool adds the die to the package according to the
specified placement parameters. IOP does not launch because you are not
making any changes to the die; you are only adding the existing die to the
package from OA.
If you select an OA design that already exists in the package, the tool displays
an error message since currently, multiple instances of a co-design die are not
allowed in a package.
❍ Once the add codesign die command has worked successfully, save the
SiP design using the File – Save command in SiP Layout.
3. To edit the die in IOP, use the Edit – Die command. Follow the sequence of steps
described below:

a. From the first screen of the Die Editor dialog box, select the co-design die for editing.
SiP Layout determines which OA library, cell, and view contains the IC design for the
die. It then launches IOP and instructs IOP to open the IC layout from that OA library,
cell, and view. Note that FE must have previously written the OA library, cell, and
view or this operation fails.

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b. IOP launches, performs a handshake with SiP Layout to make sure it was launched
correctly and can communicate successfully with SiP Layout, and then reads the OA
library, cell, and view using its Restore OA Design capability.

c. Change the IOP view to Floorplan view (from Physical View).

d. Modify the die.

Typical modifications involve power or signal assignment, bump or bond pad
placement, I/O cell placement, and RDL routing.

e. When you complete the current set of changes, use the IOP updatePackage
command.
IOP saves the current IC layout to a temporary OA library, cell, and view using its
Save OA Design capability. Then IOP sends a message to SiP Layout to instruct
it to import the data from OA and update the die instance in the package design.
SiP Layout reads the specified temp OA library, cell, and view, and replaces the
previous version of the die representation with a new one according to the original
placement location and orientation.

f. To make changes to the IC layout, invoke the updatePackage command in IOP

several times to investigate the impact of the changes on the package.

g. When you are satisfied with the latest set of changes, save the design using the File
– Save command in SiP Layout.
SiP Layout saves the current SiP database, and then for each co-design die that has
unsaved changes stored in temporary OA library, cell, and views, it replaces the
original OA library, cell, and view with the latest temporary version written by IOP.

File Formats and File Management

This section describes file formats related to FE, IOP, and SiP Layout.

Verilog
FE and IOP load a design from either a Verilog gate level netlist or an OA design database.
When you send data from FE to IOP to load into the SiP Layout environment, you can use
either a DEF file or an OA database. If you use a DEF file, you load it into IOP with the
loadDefFile command, which converts the DEF file to a Verilog file. The Verilog file, which
defines the logical connectivity in IOP, automatically loads, then the DEF file loads to include
any physical implementation details.

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In Flow 2 (Figure 1-2,) a Verilog file exists for the IC, but no DEF file exists. SCM reads the
Verilog description of the IC, connects it logically to the system or package netlist, and then
passes it to SiP Layout. SiP Layout opens IOP loading the LEF files and the Verilog netlist.
You can initialize the physical IC in IOP and feed the data back to SiP Layout for the physical
floorplanning of the package.

LEF
You must have LEF files for any design flow in the SiP environment. The LEF files must
contain the technology information and the MACRO definition of all cells referenced in the
Verilog, DEF, or OA files.

In Sip Layout, you use the LEF files to create .ldf and .cml files. You load them with each
SiP Layout session before using IOP. Use the Setup – LEF Libraries command.

DEF
Currently, DEF is the recommended file format for transferring data between FE and IOP for
two reasons:
■ FE can write a DEF file stripped of its standard cells and nets. This results in a smaller
DEF file for use in IOP. In doing this, it also hides any IP implementations in the gate level
netlist.
■ FE reads the DEF file incrementally. So, when you complete an I/O plan in SiP Layout
and IOP, you can then send it back to FE for incremental reading into an existing IC
design.

Open Access
OA is the database for sharing information between SiP Layout and IOP. When you initially
import a die into the SiP environment, you can use either a DEF file or an OA database. If it
is a DEF file, IOP saves an OA database to disk. SiP Layout uses the OA database to create
an instance of the die in the package.

An OA database consists of multiple file and directory structures. A lib.defs file defines
the directory structures that make up the OA database. An example of a lib.defs file,
showing two libraries, is shown below:
DEFINE FEOAreflib FEOAreflib
ASSIGN FEOAreflib libMode shared
DEFINE assigned assigned

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ASSIGN assigned libMode shared

The first library, FEOAreflib, is the cell macro library. This includes I/O cells, bump cells,
hard macros, and the IC technology information. In this example, assigned represents the
IC design database. When assigned loads, it references the macro library FEOAreflib.

The OA libraries are structured in a lib-cell-view format. The FEOAreflib library contains a
cell for each macro in the library, and each cell will have a view, which is typically an abstract
view.
■ FEOAreflib
❑ ADDFX1
❍ abstract
❑ ADDFX2
❍ abstract
❑ AND2X2
❍ abstract
.
.
.

The design library has one cell and potentially multiple views.
■ assigned
❑ talon_chip
o layout
o sipTempView

When you make changes to the IC die database in IOP, you can update changes to the
package, update and exit, or discard changes and exit. If you update the changes to the
package, the tool saves a temporary OA view (sipTempView) to disk, and SiP Layout
imports those changes from the temporary OA database. Once you execute a Save
command from SiP Layout, the sipTempView replaces the original view (layout in the
example above). You can permanently save the changes in FE only by saving the design in
SiP Layout. If you exit without saving the design in SiP Layout, the tool discards the temporary
OA database and all changes.

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Licensing and First Encounter Feature Set

When you launch IOP, only the SiP Layout license is checked out even though IOP contains
a subset of the Encounter product. An Encounter license is not checked out. If you need to
check out an Encounter license to enable functionality that is not available in IOP, enter the
following command in the IOP command console:
locklicense <license>
Where <license> may be any one of the following license identifiers, based on what you
own:
❑ SOC_Encounter_GXL
❑ SOC_Encounter_GPS
❑ SOC_Encounter
❑ First_Encounter_GXL
❑ FE_GPS
❑ FE_Ultra
❑ Nano_Encounter_DBS
❑ FE_Classic
❑ FirstEncounterSOC
❑ FirstEncounter
❑ First_Encounter_VIP

Encounter Functionality in IOP

Prototyping Floorplanning
I/O and Bump Placement
Design Viewer
Power Planning
FE RC Extraction
Block Implementation and Design Closure OpenAccess

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Placement (placeDesign)
Signal Wire / Manual Editing
ECO Flat
AreaIO
Verify Geometry
RDL Routing
Low Power Design Power Route (Sroute)
Power domain creation
65nm and Design for Yield 65nm Rule Support (LEF Read)

Cross Probing
The highlighting of any net or pin that connects to a die in SiP Layout causes IOP to select
that net and pin. The selection of any net or pin that connects to a die in IOP causes SiP
Layout to highlight that net and pin.

Pin Swapping
Pin swapping is changing the assignment of logical nets to physical connect points with the
purpose of improving the routability of the design either in the package or die view. Swapping
pins in this context does not change the logical functionality of the design. The implication is
that if you swap the die-connect points of two nets in a package, their corresponding nets in
the co-design die also swap. The inverse is also true. If two die nets swap bumps, the
corresponding nets in the package also swap.

When you open a co-design die in an IOP window, IOP controls all edits performed on the
die. This means that you cannot perform pin swaps from the package view when the die is
open in IOP. When you close IOP, you can make pin swaps to the die from SiP Layout. These
swaps update in IOP the next time you open the tool.

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Bumps (Die-Connect Point Separate from I/O Cell)

Inside IOP

In a design that uses bumps for the die connect points, use the following steps to complete
pin swaps:
1. Select the bumps to swap.
At least one bump should have a net assignment.
2. Choose the Floorplan – Flipchip – Swap Signals command.
All pin swaps update to the package with either of the Update commands.

Inside SiP Layout

Complete package net assignments to IC bumps with these steps:

1. Close IOP if it is open.
2. Choose the Place – Swap – Pins command from the SiP Layout menu.
3. Click on two bumps that you want to swap.
4. Right-click and choose Done.
5. Update all pin swaps to the die by doing one of the following:
❑ Choose Edit – Die to open the die for editing in IOP.
When you run this command, SiP Layout writes an I/O file to disk. This I/O file
contains bump net assignment information that can then be loaded into IOP. When
IOP is open, run these commands:
deleteBumps -all
loadIoFile <refdes>.io
redraw
Note: If bumps have been routed, duplicate bumps will be created.
❑ Save the design.
You may automate this process by setting the ICP_SEND_IO_TO_IOP environment
variable in SiP Layout.

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Updates pass automatically to the Encounter database.

Note: You cannot always swap nets from either the IC or the package views. You also cannot
swap nets connected to fixed IP in the IC, nets that are routed, and nets connected to fixed
bumps.

I/O Pads
There is no true pin swapping available when the die connect pad connects directly to an I/O
cell. This is typically the case in a wire bond design where the wire bond pad is an integral
part of the I/O cell. In this case, rather than swapping pins, you need to change the places of
the actual I/O cells in the die to have the same effect as a pin swap.

You can easily do this in IOP by selecting two I/Os, clicking the middle mouse button, and
running the swapinstances command in the console. This switches the placement of the
two I/O cells.

ECO (Addition/Deletion of Nets at the IC/Package

Boundary)
See Appendix B, ECO Flows, in the Encounter User Guide for information on supported
Encounter ECO flows from a new Verilog netlist:

http://sourcelink.cadence.com/docs/files/Release_Info/Docs/soceUG/soceUG6.2.2/
ECOFlow.html#1059375

Physical Die vs. Drawn Die

The physical die design, which occurs in the IOP view, does not fully represent the actual
dimensions of the die after manufacturing when you place it in the package. Two factors that
are ignored in the IC design phase but that you cannot ignore when placing the die in a
package are:
■ Scribe lane – the silicon between the active area of the die and the edge where the die
was cut from the wafer.
■ Optical shrink – the amount the die is shrunk in an optical shrink to take advantage of
smaller geometries.

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In the physical IC design tools, the designer’s only interest is the drawn dimensions of the die,
but when placing the die in the package, stacking die, or wire bonding a design, you must
know the dimensions of the physical die, and not just the drawn die.

The Add – Co-design Die command accounts for these factors. You enter both the scribe
lane width and the optical shrink values. When you place the die in the package, the tool adds
the scribe lane width to the die dimensions from the drawn die, then the die shrinks by the
given shrink value. SiP Layout always displays the actual die dimensions and IOP always
shows the drawn die dimensions.

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A
I/O Planning Functionality Overview

This appendix provides a catalog of functions and utilities within the Cadence I/O Planner
(IOP) which are useful in the IC/package co-design flows.

Bump Array Creation

You create bump arrays in IOP with the following command: Floorplan – Flip Chip – Create
Bump Array.

Bump Assignment
I/O cells always have a pad signal assigned to them from the Verilog (OA) netlist that IOP
reads in when you load the design. Therefore, there will never be a situation in which you
assign nets from a bump to an I/O cell. You always assign bumps from the I/O cells to the
bumps. Choose Floorplan – Flip Chip – Assign Signals from the IOP menu. In the
Assign to Tiles/Bumps section of the dialog box, click Closest. Then click Apply.

RDL Routing
You can route nets connecting the I/O cells to the bumps with the command:
Route – Flip Chip – Signal

You can route power and ground nets with the command:
Route – Flip Chip – Power

Manual Wire Editing

To manually edit wires:

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1. Use the Edit – Edit Route command.

-or-
Use the bindkey of 'e' to open the dialog box.
2. Set IOP into the Auto Query mode by selecting the Q icon at the bottom center of the
IOP screen.
3. To auto-fill the form with the wire parameters, place the cursor over the net to be edited
and press Shift-s. If the cursor is over multiple items, you can cycle through the items
before selecting it by pressing 'p'revious or 'n'ext.
The wire editing dialog box provides the following commands:
❑ Add wire
❑ Move wire
❑ Cut wire
❑ Stretch wire
❑ Change wire layer
❑ Delete wires
❑ Merge wires
❑ Trim wires
4. When editing wires that are not the minimum width, be sure to set the Force Special
option in the Nets tab.

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B
Definition of Terms and Acronyms

The following list includes some of the terms used in this application note.

APD option XL
The Allegro Package Designer single die co-design product.

Cadence I/O Planner (IOP)

Refers to the separate FE I/O Planner Window spawned by SiP Layout for editing the
definition of a co-design die, and planning its I/O cells and their mapping to the die pins.

Condensed Macro Language (CML)

An ASCII file format used by SiP Layout to store extra information about I/O cells in LEF
that is required in order to interpret I/O driver cells correctly when imported into the
system-in-package design.

co-design die
A die that is concurrently designed with its end package to ensure that the combination
of die and package meets all design requirements, while at the same time minimizes
the overall cost of production. SiP and IC tools work together

Design Exchange Format (DEF)

An industry-standard ASCII file format for exchange of digital IC implementation data.

die editor
An editor used to edit the placement of pins and tiles for standard dies, or gaining access
to the Cadence I/O Planner environment for editing co-design dies.

Engineering Change Order (ECO)

A mechanism used to pass design change requests between different teams and
mediate the impact of the changes.

First Encounter (FE)

A Cadence digital IC implementation tool.

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ICD
The IC Digital business unit of Cadence.

I/O Driver (driver)

Inside an IC, the buffer cell connected to the die pad that acts as the interface between
the IC circuitry and the pad for external connection to the IC. It provides input, output or
input/output driver circuitry and buffering for the signal on the associated die pad.

Library Exchange Format (LEF)

Together with DEF forms an industry standard ASCII file format for exchange of digital
IC implementation data. LEF contains the description of abstracts for library cells used
in the DEF.

Message Passing System (MPS)

The vehicle of communication between an active IOP and its owning SiP Layout window.

OpenAccess (OA)
An open source database format and schema that has been adopted by Cadence and
other companies for representation and interchange of IC tool data.

System Connectivity Manager (SCM)

A new logic design tool based on TDD for designing SiP connectivity.

System-in-Package (SiP)
A new design fabric and paradigm for system design using multiple dies in a single
package.

.sip
The database file format used for storing the system-in-package information about the
co-design project under development.

SiP Layout
A System-in-Package design tool that uses IOP for co-design. Current marketing plans
for the SPB Release 15.7 include this in three possible license tiers of the cdnsip
executable, Cadence SiP Digital Architect GXL, Cadence SiP Digital Layout GXL and
Cadence SiP RF Layout GXL, as well as in one tier of the apd executable, namely
Allegro Package Designer XL. This capability existing in any of these products is
referred to as SiP Layout.

standard die
A die that has already been designed, such as memory chips from external vendors or
internal dies already in production. The standard die also refers to any die with fixed die

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bumps that is not currently being designed along with the package. A standard die is
sometimes referred to as an off-the-shelf or third-party die.

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