SN74ALVC125

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS
www.ti.com SCES110H – JULY 1997 – REVISED SEPTEMBER 2004

FEATURES D, DGV, NS, OR PW PACKAGE

• Operates from 1.65 V to 3.6 V (TOP VIEW)
• Max tpd of 2.8 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V 1OE 1 14 VCC
1A 2 13 4OE
• Latch-up Performance Exceeds 250 mA Per
1Y 3 12 4A
JESD 17
2OE 4 11 4Y
• ESD Performance Exceeds JESD 22 2A 5 10 3OE
– 2000-V Human-Body Model (A114-A) 2Y 6 9 3A
– 200-V Machine Model (A115-A) GND 7 8 3Y
– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION
TA PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74ALVC125D
SOIC - D ALVC125
Tape and reel SN74ALVC125DR
SOP - NS Tape and reel SN74ALVC125NSR ALVC125
-40°C to 85°C
Tube SN74ALVC125PW
TSSOP - PW VA125
Tape and reel SN74ALVC125PWR
TVSOP - DGV Tape and reel SN74ALVC125DGVR VA125

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

FUNCTION TABLE
(each buffer)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

LOGIC DIAGRAM (POSITIVE LOGIC)

1 10
1OE 3OE

2 3 9 8
1A 1Y 3A 3Y

4 13
2OE 4OE

5 6 12 11
2A 2Y 4A 4Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVC125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS www.ti.com
SCES110H – JULY 1997 – REVISED SEPTEMBER 2004

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range -0.5 4.6 V
VI Input voltage range (2) -0.5 4.6 V
VO Output voltage range (2) (3) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 -50 mA
IOK Output clamp current VO < 0 -50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
D package 86
DGV package 127
θJA Package thermal impedance (4) °C/W
NS package 76
PW package 113
Tstg Storage temperature range -65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNIT
VCC Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 × VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8
VI Input voltage 0 3.6 V
VO Output voltage 0 VCC V
VCC = 1.65 V -4
VCC = 2.3 V -12
IOH High-level output current mA
VCC = 2.7 V -12
VCC = 3 V -24
VCC = 1.65 V 4
VCC = 2.3 V 12
IOL Low-level output current mA
VCC = 2.7 V 12
VCC = 3 V 24
TA Operating free-air temperature -40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

2
 SN74ALVC125
QUADRUPLE BUS BUFFER GATE
www.ti.com
WITH 3-STATE OUTPUTS
SCES110H – JULY 1997 – REVISED SEPTEMBER 2004

ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = -100 µA 1.65 V to 3.6 V VCC - 0.2
IOH = -4 mA 1.65 V 1.2
IOH = -6 mA 2.3 V 2
VOH 2.3 V 1.7 V
IOH = -12 mA 2.7 V 2.2
3V 2.4
IOH = -24 mA 3V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 6 mA 2.3 V 0.4
VOL V
2.3 V 0.7
IOL = 12 mA
2.7 V 0.4
IOL = 24 mA 3V 0.55
II VI = VCC or GND 3.6 V ±5 µA
IOZ VO = VCC or GND 3.6 V ±10 µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 µA
∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
Control inputs 3.5
Ci VI = VCC or GND 3.3 V pF
Data inputs 3.5
Co Outputs VO = VCC or GND 3.3 V 5.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
FROM TO VCC = 2.7 V
PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1.3 5.3 1 3.2 3.1 1.1 2.8 ns
ten OE Y 1.4 6.4 1 4.1 4.3 1 3.5 ns
tdis OE Y 1.8 5.9 1 3.4 4 1.4 4 ns

OPERATING CHARACTERISTICS
TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP
Power dissipation Outputs enabled CL = 0, 15 17 19
Cpd pF
capacitance per gate Outputs disabled f = 10 MHz 2 2 3

3
SN74ALVC125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS www.ti.com
SCES110H – JULY 1997 – REVISED SEPTEMBER 2004

PARAMETER MEASUREMENT INFORMATION

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tpd Open
CL tPLZ/tPZL VLOAD
RL
(see Note A) tPHZ/tPZH GND

LOAD CIRCUIT

INPUT
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

tw
VI
VI Input VM VM
Timing
VM 0V
Input
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu th
VI Output
Data VI
VM VM Control
Input VM VM
0V (low-level
enabling) 0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPZL tPLZ
Output VLOAD/2
VI Waveform 1
Input VM VM S1 at VLOAD VM VOL + V∆
0V (see Note B) VOL

tPLH tPHL tPZH tPHZ

Output VOH
VOH
Waveform 2 VOH − V∆
Output VM VM VM
S1 at GND
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

4
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74ALVC125D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC125 Samples

SN74ALVC125DGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VA125 Samples

SN74ALVC125DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC125 Samples

SN74ALVC125NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVC125 Samples

SN74ALVC125PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VA125 Samples

SN74ALVC125PWE4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VA125 Samples

SN74ALVC125PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VA125 Samples

SN74ALVC125PWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VA125 Samples

SN74ALVC125PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VA125 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALVC125DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74ALVC125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ALVC125NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74ALVC125PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVC125DGVR TVSOP DGV 14 2000 356.0 356.0 35.0
SN74ALVC125DR SOIC D 14 2500 356.0 356.0 35.0
SN74ALVC125NSR SO NS 14 2000 356.0 356.0 35.0
SN74ALVC125PWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74ALVC125D D SOIC 14 50 506.6 8 3940 4.32
SN74ALVC125PW PW TSSOP 14 90 530 10.2 3600 3.5
SN74ALVC125PWE4 PW TSSOP 14 90 530 10.2 3600 3.5

Pack Materials-Page 3
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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