DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

ACOE419 TEST1 Date: 13/12/13

Instructions: Please answer any four questions only. Use the separate answer sheet. Time: 90
min

Question 1.
A. State which of the statements below correspond to a pMOS and which to an nMOS
transistor (11%)

i) Charge carriers are holes

ii) Charge carriers are electrons
iii) The body is tied to GND
iv) The body is tied to VDD
v) It is used in the pull-up network
vi) It is used in the pull-down network
vii) it has a weak 0
viii) It has a weak 1
ix) Its equivalent resistance is R/k
x) Its equivalent resistance is 2R/k
xi) It has greater gate leakage current

B. For the highlighted path between Y and F in the circuit of Figure Q1 calculate:
a. Total delay [2%]
b. Path logical effort [2%]
c. Path electrical effort [2%]
d. Path effort [2%]
e. Path parasitic delay [2%]
f. Best stage effort [2%]
g. minimum theoretical delay [2%]

4 6

6
20C

Figure Q1
Logical effort of common gates: Parasitic delay of common gates:
Gate type Number of inputs Gate type Number of inputs
1 2 3 4 N 1 2 3 4 N
Inverter 1 Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3 NAND 2 3 4 N
NOR 5/3 7/3 9/3 (2n+1)/3 NOR 2 3 4 N
Question 2:
A. Draw the circuit diagram of a 4-input CMOS NOR gate (10%)
B. Draw the stick diagram (10%)
C. Estimate the area of the layout from the stick diagram (5%)

Question 3:
Two transistors of the same type and technology have a threshold voltage Vt=0.5V, and are
connected to Vgs equal to 1 V. To the first transistor is applied a Vds = 0.2 V while in the
second one a Vds = 0.6 V.
a) Calculate the saturation voltage Vdsat (5%)
b) Are the transistors in cutoff, linear or saturation region? (5%)
c) Calculate the ratio of the source-drain current for the two transistors (10%)
d) Calculate the effective resistance ratio of the two transistors (5%)

 0 Vgs  Vt cutoff


I ds    Vgs  Vt  ds Vds Vds  Vdsat
V
linear
2
 
 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

Question 4:
Evaluate the following 8-input NAND gate implementations below.
i) What is their path logical effort? (5%)
ii) What is their path parasitic delay? (5%)
iii) What is their path effort as a function of the electrical effort H? (5%)
iv) What is their best stage effort? (5%)
v) Which is fastest for path electrical effort H=1; (5%)

(a) (b) (c)

Question 5:
For the circuit of Figure Q5:
a) Give the corresponding Boolean equation (5 %)
b) Draw the stick diagram (5 %)
c) Give the transistor sizes required for the gate to have the same effective rise and fall
resistance as a unit inverter (5 %)
d) Calculate the input capacitance (5%)
e) What is the logical effort for this compound gate? (5%)
A C

B D

A B

C D

Figure Q5