VPE_T: Issues

Floorplan stage:
With update: TMAC occupied the macro location after movement
Adjusted the Macros location
To resolve Latch up issues
Tap Cell Movement is done in priority in case Tap cell is not aligned with other Tap cells and
Tap cells are added for few locations
DRCs and Flow issues: Missing Power Switches, Improper Power Gird, Missing Physical cells and Stream Out
Error, Fatal Error in Floorplan stages
Synchronized the contents of the local work space with the latest version of files.
Used the perforce version control system called P4 sync.

Placement:
Congestion at the edge of the rectilinear shape of tile
Added partial placement blockage with 50% blocked area and dimensions of 10um*15um
Keep outs are added for isolation cells and bound buffers and removed for registers
To reduce the congestion, provide adequate clearance and prevent electrical interface keep outs are added for
highly Sensitive elements like ISO and BOUNDBUFF which routes the high frequency signals
Adding the keep outs for registers increasing the complexity by limiting space for other components which
limits the available routing options.
ELPE: Enhanced low power Efficiency: Technique for optimizing the circuit at Architectural level by selecting
low power techniques – EPLPE Medium is used
ELPE Low setting was giving the Better results which is not considerable difference compared to default ELPE
(ELPE Medium) with the cost of power efficiency. ELPE default is considered for better power Efficiency.
SAIF: Switching Activity Interchange format: File format used to represent the switching activity. It estimates
the dynamic switching power, area of circuit consuming more power and optimize it. –SAIF Yes is used
As PPA are interrelated. SAIF yes is considered by default and results by SAIF yes are better than SAIF no in
most of the cases.
CCD: Concurrent clock and data optimization Technique used to optimize both the data path and clock path
simultaneously by adjusting the clock distribution scheme and use of low power techniques. – CCD is used
CCD use for better results.

CTS:
With update: Clock port moved from center to edge, Mesh root buffer is not there and net length is more
than 400um
Added 3 clock buffers one at source, sink and middle of the net with ratio of 1:2:1 at CTS stage
Clock tree is not built at OptCts stage
Clock is in locked stage, unrestricted the clock at CTS stage
Skew of Vpe clk: created bounds
With update: Clock ports moved and timing degraded, there was change in Time Period of clocks
Reported to Top level

Routing:
LVS:
Resolved Signal Nets by Rerouting/Moving the Nets
Moved VIAs Near Pins of M1 Layer.
Removed Isolated Nets and Additional VIAs on different Nets.
Cells sitting in the wrong domain
Cells Moved to correct domain in case of wrong domain.
Other case: Cell in the Right domain but Net connecting to it in belongs to different domain.
Timing Degradation after Moving the cells with small distance movement from one domain to other
To overcome cells moved in the direction of Net slightly larger distance instead of moving smaller distance
NBIO_NB_T: Issues
Floorplan stage:
With update: SSB occupied the macro location after movement
Adjusted the Macros location
To resolve Latch up issues
Tap Cell Movement is done in priority in case Tap cell is not aligned with other Tap cells and
Tap cells are added for few locations
DRCs and Flow issues: Missing Power Switches, Improper Power Gird, Missing Physical cells.
Synchronized the contents of the local work space with the latest version of files.
Used the perforce version control system called P4 sync.

Placement:
Congestion at the SSB bus
Added placement blockage and Routing Guide
Keep outs are added for isolation cells and bound buffers and removed for registers
To reduce the congestion, provide adequate clearance and prevent electrical interface keep outs are added for
highly Sensitive elements like ISO and BOUNDBUFF which routes the high frequency signals
Adding the keep outs for registers increasing the complexity by limiting space for other components which
limits the available routing options.
ELPE: Enhanced low power Efficiency: Technique for optimizing the circuit at Architectural level by selecting
low power techniques –ELPE Low is used
ELPE Low setting was giving the Better results which is a considerable to default ELPE (ELPE Medium) with the
cost of power efficiency. ELPE Low is considered for better timing results due to considerable difference.
SAIF: Switching Activity Interchange format: File format used to represent the switching activity. It estimates
the dynamic switching power, area of circuit consuming more power and optimize it. - SAIF YES is used
As PPA are interrelated. SAIF yes is considered by default and results by SAIF yes are better than SAIF no in
most of the cases.
CCD: Concurrent clock and data optimization Technique used to optimize both the data path and clock path
simultaneously by adjusting the clock distribution scheme and use of low power techniques – CCD is used
CCD use for better results.

CTS:
Skew of Vpe clk: created bounds
With update: Clock ports moved and timing degraded, there was change in Time Period of clocks
Reported to Top level

Routing:
LVS:
Resolved signal Nets by Rerouting/Moving the Nets
Moved VIAs Near pins of M1 Layer.
Removed Isolated Nets and additional VIAs on different Nets.
Cells sitting in the wrong domain
Cells Moved to correct domain in case of wrong domain.
Other case: Cell in the Right domain but Net connecting to it in belongs to different domain.
Timing Degradation after Moving the cells with small distance movement from one domain to other
To overcome cells moved in the direction of Net slightly larger distance instead of moving smaller distance