H265 Encoder Master

Block Diagrams with the signal flow

Encoder
control
data
Encoder
control
data

Intra
Prediction
data

Filter
control
data

Motion
data
 H265 Encoder Master

Tb_top
H265 Core(dut)
Fetch

Encoder_top

Hevc_md_top

buf_ram_1p_6x85_0 buf_ram_1p_6x85_1
 Encoder_top
Fme_top
cabac_top Top_cntrl (fractional motion
estimation)

db_top Intra_top MC(mc_top)

(motion compensation)

FIME(ime_top) Tq_top Md(motion data)

(integer motion estimation) (Transform quantization)

Rf_2p mem0 Rf_2p mem1 Rf_2p mem2

Mem_lipo_lp_bw0 Mem_lipo_lp_bw1 Mem_buf

 Fetch Block

Fetch_cntrl Fetch_db

Fetch_cur_luma Fetch_cur_chroma

Fetch_ref_luma Fetch_ref_chroma
 Transform Cabac Coded
Quantization (entropy coding) bitstream

Motion Estimation

Motion Compensation
IME FME

Intra-Prediction
 clk
rstn
Cabac_top cu_luma_mode_ren_o

mb_type_i
cu_luma_mode_raddr_o
inputs mb_x_total_i
Cabac_binarization
mb_y_total_i cu_chroma_mode_ren_o
mb_x_i
mb_y_i cu_chroma_mode_raddr_o

qp_i
param_qp_i mb_mvd_ren_o
sao_i
Cabac_slice_init mb_mvd_raddr_o
luma_mode_i
chroma_mode_i Coeff_type_o
flags
mb_p_pu_mode_i
tq_ren_o
merge_flag_i
merge_idx_i tq_raddr_o
mb_partition_i Cabac_modeling
done_o
cu_skip_flag_i
mb_mvd_radata_i slice_done_o
tq_rdata_i
tq_cbf_luma_i bs_val_o

tq_cbf_cb_i Bit stream

Cabac_bae bs_data_o output
tq_cbf_cr_i
start_i
bs_wait_i
 Cabac_top
cabac_slice_init

cabac_mn_1p_16x64_u0
Cabac_binarization
sram_0_mn ROM
.dat

cabac_mn_1p_16x64_u1

sram_1_mn ROM
.dat

cabac_mn_1p_16x64_u2 bs_val_o
sram_2_mn Cabac_modelling Cabac_bae
.dat ROM
bs_data_o

cabac_mn_1p_ 16x64_ u3

sram_3_mn ROM
.dat

cabac_mn_1p_ 16x64_ u4

sram_4_mn
.dat
ROM
 clk binary_pair_0_o
rstn cabac_binarization binary_pair_1_o
cabac_start_i binary_pair_2_o
slice_start_i
binary_pair_3_o
mb_x_total_i
slice _init_flag_o
mb_y_total_i
mb_x_i cu_luma_mode_ren_o
mb_y_i cu_luma_mode_raddr_o
lcu_qp_i cu_chroma_mode_ren_o
param_qp_i cu_chroma_mode_raddr_o
sao_i
cu_mvd_ren_o
luma_mode_i cu_mvd_raddr_o
cabac_bae chroma_mode_i
no_bit_flag_i
table_build_end_i cu_coeff_ren_o
cabac_slice_initial
cu_coeff_raddr_o
inter_cu_part_size_i
cu_coeff_type_o
merge_flag_i
merge_idx_i
cu_split_flag_i cabac_curr_state_o
cu_skip_flag_i binary_pair_valid_num_o
luma_cbf_i
cr_cbf_i cabac_slice_done_o
cb_cbf_i cabac_mb_done_o
cu_mvd_i
coeff_data_i
 clk
rstn cabac_modelling

modelling_ctx_pair_0_o
modelling_ctx_pair_1_o
modelling_ctx_pair_0_i
cabac_binarization modelling_ctx_pair_1_i
modelling_ctx_pair_2_o
modelling_ctx_pair_2_i
modelling_ctx_pair_3_i modelling_ctx_pair_3_o

valid_num_modelling_o

w_en_ctx_state_0_i
w_addr_ctx_state_0_i
w_data_ctx_state_0_i
w_en_ctx_state_1_i
w_addr_ctx_state_1_i
w_data_ctx_state_1_i
w_en_ctx_state_2_i cabac_bae
cabac_slice_initial w_addr_ctx_state_2_i
w_data_ctx_state_2_i
w_en_ctx_state_3_i
w_addr_ctx_state_3_i
w_data_ctx_state_3_i

w_en_ctx_state_4_i
w_addr_ctx_state_4_i
w_data_ctx_state_4_i
 clk
rstn Cabac_bae(binary arithmetic encoding)
Cabac_modelling
bae_ctx_pair_0_i
Stage _1
bae_ctx_pair_1_i
Loop_up_table for i_range_lut and
bae_ctx_pair_2_i shift_lut and calculation
bae_ctx_pair_3_i bin_eq_lps(least probable symbol)

Stage _2
Range update
Stage _4 output_byte_en_o
Bits generation (bs_val_o)

Stage _3 Bae_output_byte_o
Low update (bs_data_o)

Bit stream output from

CABAC top

Note:
bae_ctx_pair is 10 bits.
{coding_mode, bin, MPS, pStadeidx}={2,1,1,6}
Coding mode:- 0: regular mode, 1: Invalid input, 2:bypass mode,
3:terminal mode.
 cabac_slice_initial

clk cabac_mn_1p_16x64_u0
table_build_end_o
rstn
w_en_ctx_state_o
start_slice_init_i ROM
slice_type_i
slice_qp_i
cabac_mn_1p_16x64_u1
w_en_ctx_state_0_i
ROM w_addr_ctx_state_0_i
w_data_ctx_state_0_i
w_en_ctx_state_1_i
w_addr_ctx_state_1_i
cabac_mn_1p_16x64_u2 w_data_ctx_state_1_i
w_en_ctx_state_2_i
ROM w_addr_ctx_state_2_i
w_data_ctx_state_2_i
w_en_ctx_state_3_i
cabac_mn_1p_ 16x64_ u3
w_addr_ctx_state_3_i
w_data_ctx_state_3_i
ROM w_en_ctx_state_4_i
w_addr_ctx_state_4_i
w_data_ctx_state_4_i
cabac_mn_1p_
16x64_ u4

ROM