This article has been accepted for publication in IEEE Transactions on Power Electronics.
This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3215179
JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX
A Single Switch Continuous Input Current
Buck-Boost Converter With Non-Inverted Output
Voltage
Mukkapati Ashok Bhupathi Kumar and Vijayakumar Krishnasamy, Member, IEEE
Abstract—In this paper, a single switch continuous input cur-
rent (CIC) buck-boost converter with non inverted output voltage
is proposed. The proposed converter utilizes a capacitor and
inductor along with three diodes in conjunction with quadratic
boost converter (QBC) to adopt its CIC feature. The features
of high voltage gain, single active power switch, less ripple CIC
and non-inverted output voltage makes the proposed converter
suitable for renewable and industrial applications. In addition, it
provides a wide operating voltage gain with optimum component
count which is higher than conventional buck-boost converter.
Further, it has low voltage stress across the power switch with
comparable converters. To elevate the importance of the proposed
converter, a detailed comparison analysis has been carried out
considering voltage stress, voltage gain, effectiveness index and
component count. The operating principle and steady state
analysis in continuous conduction mode(CCM) and discontinuous
conduction mode (DCM) of the proposed converter are discussed
in detail. To validate the theoretical analysis and performance
of the proposed converter, a prototype has been developed and
tested in laboratory.
Index Terms—Buck-boost converter, continuous input current,
Non inverted output voltage.
I. I NTRODUCTION
I N the current scenario, renewable energy resources capti-
vate considerable attention due to issues aroused because
of global warming, increase in energy consumption, abatement
of fossil fuels, climate changes, etc [1]. In general, power
electronics equipment has an indispensable role in integrating
these renewable energy resources such as photovoltaic (PV),
wind energy and fuel cells to the load. In addition, these
power electronic equipments are used in many applications
such as battery systems, power factor correction, electric
vehicle (EV), portable devices, etc., and maintains the load
voltage on account of broad variation in source voltage.
In contrast, some applications like multi-functional switched
mode power supplies require a varied range of output voltages
with respect to constant source at the input end. A dc-dc
converter with a wide voltage conversion ratio becomes a
promising solution for the aforementioned aspects. Boost and
Buck converters are conventional and well established due to
their intelligible and simple structure. On the other hand, these
converters are confined to limited voltage conversion ratio
requirements in the extremes of desired voltages, either low
or high. Consequently, to discard these limitations, the voltage
multipliers, voltage lift, switched capacitor/switched inductor,
and cascading techniques are employed for achieving high
voltage gain. Furthermore, interleaved converters are useful in
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1
achieving either step-down or step-up mode with low ripple
current. However, it is adding complication in the converter
structure as well as control strategy due to additional switches.
A buck-boost converter benefits in providing both step-
up as well as step-down modes in contrast to conventional
boost or buck converter. In PV applications, the buck-boost
converter faces difficulties in integrating the loads due to
its pulsating source current [2], which is not admissible. In
addition, the pulsating source current slackens or degrades
efficiency, life, and performance of PV and fuel cell [3]. Cuk
converter is derived from a boost converter where the diode is
replaced with an LCD network. It abolishes the indispensable
pulsating current and smoothen with the use of an inductor
at the input end. An added advantage of continuous output
port current, due to the presence of another inductor at the
load end, makes the converter more suitable for PV and fuel
cell applications. The inverted output voltage which is still
present in the converter as like buck-boost converter pertains
to some specific applications like data transmission and signal
generators etc. However, extra circuitry is needed to invert the
voltage polarity in the control loop. To overcome the issue of
inverted voltage polarity, a pair of converters are introduced,
namely SEPIC and Zeta. The SEPIC converter is a variant
of Cuk converter, where the inductor and diode are swapped
in the LCD network. However, it attains non-inverted output
voltage with the expense of absence in continuous output port
current. In the case of Zeta converter, which is developed and
derived from a conventional buck-boost converter by replacing
the diode with LCD network as like Cuk converter. But, in
contrast to the Cuk converter, this converter achieves non-
inverted output voltage and continuous output port current
with a shortcoming of pulsating input current, which is not
agreeable. Additionally, these derived converters have the
same voltage conversion ratio as like conventional buck-boost
converter, and it may not be suitable for a wide range of
operations.
Hence, a quadratic buck-boost converter [4] is presented in
the literature which was developed by integrating two con-
ventional buck-boost converters in a cascade manner utilizing
a single switch. This converter facilitates a wide operating
range in terms of quadratic gain. However, this converter fails
in providing continuous input and output port current as well
as its ability to work in boost mode for d > 0.5 because

of the
voltage stress across diode Db VDb = V0 . 1 − 2d/d2 . With
the inclusion of an additional switch to the aforementioned
converter, a modified quadratic buck-boost converter [5] was
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JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 2

Lc,Cb,Dc,Dd --- added to qbc
qBC --- La,Lb,Ca,Cc,Da,Db,Dc and S

Dc Cb De Dc Cb De Dc Cb De
La Db La Db La Db
Da Da Da
Vi Lc Cc V0 Vi Lc Cc V0 Vi Lc Cc V0
Ca Lb Ca Lb Ca Lb
S S S
Dd Dd Dd

(a) (b) (c)

ILa=0 Dc Cb De Dc Db C b De Dc Cb De
La Db La La Db
Da Da ILb=0 Da
Vi Lc Cc V0 Vi Lc Cc V0 Vi Lc Cc V0
ILc=0
Ca Lb Ca Lb Ca Lb
S S S
Dd Dd Dd

(d) (e) (f)

Fig. 1. Equivalent circuits. (a) Proposed converter. (b) ON state. (c) OFF state. (d) DCM La state. (e) DCM Lb state. (f) DCM Lc state.

proposed with the ability to work in boost mode. Perhaps,
this converter finds difficulty in providing continuous input
and output port current like the aforementioned converter in
[4]. This is due to the floating switches presented in the
converter. To preserve the property of continuous input current
of the converter in [5], converter in [6] is proposed with
reconfiguration of similar component count. Which further
deviates the voltage gain and gives inverting voltage polarity.
The converters presented in [7], [8] employed capacitors in
series with input source reflects output voltage. Which makes
the converter to achieve quadratic gain with pulsating current
due to switched capacitor.
In pursuit of minimizing the switch count, a series of
converters with single switch are proposed with elevation
of conversion ratio and which resembles conventional buck-
boost, Cuk, SEPIC and Zeta in terms of properties. Con-
verters presented in [9], [10] achieves twice voltage gain of
conventional buck-boost converters along with properties of
zeta converter. However, in [9], the load is tapped across
two capacitors which are connected in series fashion. This
increases the output voltage ripple and is not advisable. A
quadratic gain based buck-boost converter is proposed in
[11] with a single switch. Further, it derived from a buck-
boost converter where the inductor is replaced with switched
inductor cell to improve the conversion ratio. In the same
fashion, with increment of passive components in switched
inductor cell which is integrated in buck-boost converter as
like in [11] is proposed in [12]. Hence, the converter enhances
the conversion ratio three times of conventional buck-boost
conversion ratio. However, these set of converters are unable
to abolish the difficulties which are present in [5] mainly the
continuous input current.
With the importance of quality of continuous input current,
single switch, and high conversion ratio, a pair of converters
are introduced in [13] and [14] with inverting voltage polarity.
The converter presented in [13] utilizes Cuk converter as its
embodiment. Further, it achieves high gain in step-up mode
when compared with the Cuk converter. Similarly, in [14]
with inclusion of basic buck, buck-boost and boost convert-
ers, converter with quadratic gain is proposed. Unlike the
aforementioned converters, the SEPIC based implementation
of converter [15] is pertinent in terms of continuous input
current and non inverting voltage polarity.
In this paper, the number of energy storage elements of
the SEPIC based converter presented in [15] are minimized.
Also, the proposed converter achieves better voltage gain
capabilities in both boost as well as buck mode. Furthermore,
unique features of the proposed converter like non-inverting
voltage polarity, comparable high gain, less voltage stress
and substantial continuous input current are noteworthy to
mention. The proposed buck-boost converter configuration is
divergent to the conventional buck-boost converter and other
presented converters in literature.
II. C IRCUIT SCHEMATIC OF THE PROPOSED CONVERTER
AND ITS DESCRIPTION
The proposed converter configuration emanates from the
traditional quadratic boost converter to preserve the abilities in
terms of continuous input current, non-inverted output voltage
and wide operating range which are inevitable shortcomings in
conventional buck-boost converter. As shown in the Fig. 1(a),
an additional set of passive elements such as inductor Lc ,
capacitor Cb and diodes Dc , Dd are employed in quadratic
boost converter for acquiring the abilities of buck mode along
with the boost mode. The quadratic boost converter comprises
of a pair of inductors (La &Lb ), capacitors (Ca &Cc ), three
diodes (Da , Db , &Dc ) and a power switch (S). In continuous
conduction mode (CCM ), the proposed configuration shuttles
between two operating modes based on the state of power
switch either on or off over a switching period as shown
in Fig. 2. Further, the steady state typical waveforms of the
proposed converter are shown in Fig. 3.
The following assumptions are made to ease the analysis
of proposed converter in view of operating modes and steady
state analysis.
1) Non-conducting passive devices and switch are shown in
light gray colour.
2) Voltage across the utilized capacitors are contemplated as
constant over a switch cycle due to the enough value of
capacitance is used.

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 This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3215179

JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 3

TABLE I
P ROPOSED CONVERTER STATE EQUATIONS

diLa diLb diLc dvCa dvCb dvCc

VLa = La VLb = Lb VLc = Lc iCa = Ca iC b = Cb iCc = Cc
dt dt dt dt dt dt
ON state (dT ) vi vCa vCb −iLb −iLc −i0
OF F state ((1 − d) T ) vi − vCa vCa − vCb −vCc iLa − iLb i Lb i Lc − i 0
DCM La state (dx T ) 0 vCa − vCb −vCc −iLb i Lb i Lc − i 0
DCM Lb state (dy T ) vi − vCa 0 −vCc iLa − iLb 0 i Lc − i 0
DCM Lc state (dz T ) vi − vCa vCa − vCb 0 i La − i Lb i Lb −i0

ON ON
state State
t=T t=T
t=T t=T
t=T
t=T

DCM Lb DCM La DCM Lc DCM Lb

t=T
DCM La
t = dT
DCM Lc
state t=T state t = dT state State State State

i La = 0
i La = 0
iLb = 0 iLc = 0
iLb = 0 iLc = 0
OFF
OFF State
state

(a) (b)

ON ON ON
State State State

t=T t=T t=T t=T t=T t=T

t=T t=T t=T

DCM Lb DCM La DCM Lc DCM Lb DCM La DCM Lc DCM Lb DCM La DCM Lc

State t=T State t = dT State t=T t = dT t = dT t=T
State State State State State State

iLa = 0 i La = 0 iLa = 0

iLb = 0 iLc = 0 iLb = 0 iLc = 0 iLb = 0 iLc = 0

OFF OFF OFF

State State State

(c) (d) (e)

Fig. 2. Conduction mode state diagram of proposed converter. (a) General representation, (b) CCM , (c) DCM La , (d) DCM Lb , (e) DCM Lc .

3) Power devices are considered as ideal. Thus, the parasitics
are neglected.
A. Operation Principle
1) Mode1 [ta − tb ]: This mode commences by switching
the power switch S at t = ta and lasts until t = tb before
entering into the subsequent interval. The equivalent schematic
of this mode is shown in Fig. 1(b). During this mode, the
diodes (Db &Dd ) assists the inductors (La &Lb ) to magne-
tize by utilizing the input voltage source (Vi ) and capacitor
(Ca ) being in conduction state. Additionally, the diode (Da )
at the input end turn into reverse biased by the virtue of
voltage (VCa ) across it. The inductor Lc gets magnetized
using capacitor Cb with the entitling reverse biased diodes
(Dc &De ). Where the diodes (Dc &De ) block the voltages of
VCb and VCc + VCb respectively. Finally, the capacitor (Cc )
alone energies the load by discharging through it. The voltages
across inductor followed by currents through capacitor are
expressed in Table I.
2) Mode2 [tb − tc ]: As subsequent mode to the mode1,
this mode starts off at instant tb by switching off the power
switch S lasts until tc which becomes starting point to the
Mode1. The equivalent schematic of this mode is shown in
Fig. 1(c) and the current paths are represented as dotted lines.
In contrast to earlier mode, the inductors starts discharging in
a way to charge the capacitors. Where, inductor La &Lb and
voltage source Vi are accompanies the capacitor Ca , inductor
Lb assist the capacitor Cb and finally the capacitor Cc charged
up by inductor Lc . The posterior energy exchange is through
the forward biased diodes (Da , Dc &De ) in addition to reverse

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 This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3215179

JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 4

TABLE II
VOLTAGE ACROSS THE CAPACITORS AND CURRENT THROUGH THE INDUCTORS

VCa VCb VCc i La i Lb i Lc

Vi VCa Vi dVCb dVi iLb dI0 diLc dI0 I0
CCM = = = =
(1 − d) (1 − d) (1 − d)2 (1 − d) (1 − d)3 (1 − d) (1 − d)3 (1 − d) (1 − d)2 (1 − d)
Vi (d + dx ) VCa Vi (d + dx ) dVCb Vi d (d + dx ) vi d (d + dx ) diLc Q La I0
OF F
DCM La = = =
dx (1 − d) dx (1 − d) (1 − d) dx (1 − d)2 2La f (1 − d) T (1 − d)
Vi VCa (d + dy ) Vi (d + dy ) dVCb Vi d (d + dy ) i Lb vCa d (d + dy ) Q Lb
OF F
DCM Lb = = 2
(1 − d) dy dy (1 − d) (1 − d) dy (1 − d) (1 − d) 2Lb f dT
Vi VCa Vi dVCb dVi i Lb diLc vCb d (d + dz )
DCM Lc = =
(1 − d) (1 − d) (1 − d)2 dz dz (1 − d)2 (1 − d) (1 − d) 2Lc f

2) Voltage Stress: From the operating mode in Fig. 1(c), it

VGS VGS
is discernible that the voltage stress across the switch S can
0 t 0 t be written as the combination of voltages across the capacitor
VLa VDa
iLa Cb and Cc as shown in (3)
iDa
0 t 0 t V0 Vi
VDb
VLb iDb
VDS = VCb + V0 = = 3 (3)
iLb
d (1 − d)
0 t
0 t VDc
iDc Similarly, the voltage stress across diodes Db and Dd can
VLc 0 t be written as follows:
iLc VDd
0 t iDd dVi
0 t VDb = VCb − VCa = V0 (1 − d) = 2 (4)
VS VDe (1 − d)
iS iDe
0
dT (1 − d) T t 0
dT (1 − d) T t dVi
T T VDd = VCc = V0 = 3 (5)
ta tb tc ta tb tc (1 − d)
With the help of operating mode in Fig. 1(b), the remaining
Fig. 3. Key waveforms of the proposed converter during CCM.
diode voltages can be written as follows:
2
V0 (1 − d) Vi
biased diodes (Db &Dd ). The voltages across inductor fol- VDa = VCa = = (6)
d (1 − d)
lowed by currents through capacitor are expressed in Table I.
V0 (1 − d) Vi
VDc = VCb = = 2 (7)
d (1 − d)
III. S TEADY STATE ANALYSIS
V0 Vi
VDe = VCb + V0 = = 3 (8)
A. CCM Analysis d (1 − d)
1) Voltage Gain: To ease the analysis of voltage gain 3) Current Stress: During mode1 means (switch on state),
derivation, it is assumed that the voltage ripple content on the the switch current stress can be calculated as summation of
all capacitors is negligible. With this, the voltage across each three inductor currents ILa , ILb , and ILc which are flowing
capacitor can be found by utilizing the volt-second balance through switch. The inductor currents can be found using amp-
principle on inductors which is given in (1) second balance of the capacitor currents during both modes
Z tb Z tc which is given in (9).
VLP ON dt + VLP OF F (1 − d) t = 0, P = a, b, &c. Z tb Z tc
ta tb
(1) ICP ON dt + ICP OF F (1 − d) t = 0, P = a, b, &c (9)
ta tb
By substituting the state equations in Table I into the (1),
the capacitor voltages are calculated and presented in Table II. With the consideration of resistive load, the load current
Finally, the voltage gain of the proposed QBC based buck- i0 can be written as V0 /R because the load capacitor Cc
boost converter can be written from Table II as is discharging to the load R. Knowing the load current, the
inductor currents ILa , ILb , and ILc are calculated with the aid
V0 VCc d
MCCM = = = 3. (2) of (9) and Table I and are presented in Table II.
Vi Vi (1 − d) From Table II, the relation between RMS switch current and
With reference to (2), it can be stated that, the presented load current can be obtained as
converter is capable of working in boost as well as buck mode √ I0 √
with duty ratio boundary of 0.3178. ISrms = (ILa + ILb + ILc ) d = 3 d (10)
(1 − d)

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JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 5

iLP 1.2 6
VLPON Ky =0.2
iLPM AX = dT, P = a, b, &c 1 5 Ky =0.4
LP Ky =0.6
0.8 4 Ky =0.8
iLPM AX di T

MDCM Lb
MDCM La
Ky =1.2
QLPOF F = 0.6 Kx =0.4 3 Ky =1.6
2 Kx =0.8 Ky =3.0
i = x, y, &z 0.4 Kx =1.2 2
Kx =1.6
0.2 Kx =2.0 1
0 ta tb ti tc Kx =3.0
t
dT di T 0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
T Duty ratio (d) Duty ratio (d)

(a) (b)
Fig. 4. Generalized DCM inductor current waveform.
8 0.4
Since, the inductor La current flows through diode Da and Kz =0.2
Kz =0.3
Db in successive modes. By utilizing the Table II, the rms 6 Kz =0.4 0.3
Kz =0.5
current of these diodes can be estimated as CCM

MDCM Lc
Kz =0.6
√ dI0 √

Kx
4 Kz =0.7 0.2 DCM La
IDarms = (ILa ) 1 − d = 3 1−d (11) Kz =1.2
(1 − d) 2 0.1
√ dI0 √
IDbrms = (ILa ) d = 3 d (12) 0 0
(1 − d) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.2 0.4 0.6 0.8 1
Duty ratio (d) Duty ratio (d)
The rms current of diodes Dc and De can be estimated as
(c) (d)
currents ILb and ILc flowing through those accordingly during
mode2. So, 0.4 1.2

√ dI0 √ 1
IDcrms = (ILb ) 1 − d = 2 1−d (13) 0.3
(1 − d) CCM
0.8 CCM

√ I0 √

Kz
Ky

0.2 DCM Lb 0.6

IDerms = (ILc ) 1 − d = 1−d (14) 0.4
(1 − d) 0.1
0.2 DCM Lc
Finally, rms current through Dd can be evaluated as the
0 0
combination of inductor currents ILa and ILb and expressed 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Duty ratio (d) Duty ratio (d)
as
√ (2 − d) dI0 √
IDdrms = (ILa + ILb ) d = d (15) (e) (f)
3
(1 − d)
Fig. 5. DCM voltage gain versus duty ratio: (a) DCM La . (b) DCM Lb .
(c) DCM Lc ., Boundary condition between: (d) CCM and DCM La . (e)
B. DCM Analysis CCM and DCM Lb . (f) CCM and DCM Lc .
1) DCM La : This mode arises when the inductor current
iLa becomes zero marked as tx between the time interval
tb and tc shown in Fig. 4. Where the diode Da becomes Finding the roots of (18) leads the unknown dx as shown
reverse biased as shown in Fig. 1(d) and the inductor voltage in (19)
is also goes to zero. Hence, during the volt-second balance of
 s 
4
inductor La will be having a time interval dx instead of 1 − d dKx .A 4(1 − d) 
dx = 4, A = 1 + 1 + (19)
and remaining inductors follows the same as CCM. With the 2(1 − d) Kx
evaluation of volt-second balance via Table I, the outcomes
are appended in Table II. By replacing the dx in Table II with (19), the DCM La of
The charge balance on the capacitor Ca leads to the (16). converter states are resulted as follows:
Where, the QLaOF F represents the charge delivered to the Vi d2 .A2
 
 ILa =  V = Vi .A
capacitor Ca by inductor La before undergoing the DCM La

 4  Ca


 4R(1 − d) 

 2
state.  
Vi .A
Vi d2 .A
 
−iLb T + QLaOF F  
VCb =
=0 (16) ILb = 4 2 (1 − d) (20)
T 
 2R(1 − d)  
Vi dA
 
By using QLaOF F in Fig. 4 and solving the (16), the 
 Vi dA


 VCc =
 
I =
  2
dimensionless parameter Kx can written as  Lc

3 2 (1 − d)
2R (1 − d)
4 2
2La (1 − d) (dx )
Kx = = (17) 2) DCM Lb : As like DCM La , this mode starts with the
RT (d + dx ) d
discontinuity in the inductor current iLb at time ty . Further, the
Rearranging the (17) results the (18) as a quadratic equation
diode Dc becomes reverse biased and makes no charging path
shown below
to the capacitor Cc results iCc as zero as shown in Fig. 1(e).
4 2
(1 − d) (dx ) − Kx ddx − Kx d2 = 0 (18) As stated in DCM La , only the volt-second balance of the

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 This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3215179

JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 6

16 10 2.0
Sepic converter
Sepic converter

14 [9], [10], & [13]

[10], & [13]
[12], & [15] [15]

Effectiveness index (EI)

8 1.6
12 [6], & [11] [6], & [11]
Voltage gain (M)

[17] [23]

10 [7] [16]

0
6 1.2

/ V
[16] [14]

sw
8 [5], & [14] Proposed converter

V
Proposed converter
4 0.8
6

4
[5] & [14]
2 0.4
[7]
2
[18]

Proposed converter, [6], & [17]

0 0 0.0

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
0.0 0.2 0.4 0.6 0.8 1.0

Duty ratio (d) Duty ratio (d) Duty ratio (d)

(a) (b) (c)

Fig. 6. Comparison, (a) Voltage gain versus duty ratio. (b) VSW /V0 versus duty ratio. (c) EI versus duty ratio.

TABLE III Substituting the dy in the expressions stated in Table II, the
S UMMARY OF DCM VOLTAGE GAIN converter state variables are obtained as follows:
Vi d2 .B 2

 VC = Vi

M ode DCM Gain  ILa =

 4  a
VCc Vi dA


 4R(1 − d) 

 (1 − d)
DCM La MDCM La = =
 
2 2 Vi .B
 
Vi 2 (1 − d)2 Vi d .B
 
ILb = VCb = (25)
VCc Vi d.B 4R(1 − d) 
3  2 (1 − d)
DCM Lb MDCM Lb = =


Vi 2 (1 − d)2
 

 Vi dB

 Vi d.B
 VCc =
 
 ILc =
 
VCc Vi d  2
DCM Lc MDCM Lc = = √ 2R (1 − d)
3 2 (1 − d)
Vi (1 − d)2 . Kz

3) DCM Lc : As shown in Fig. 1(f), the diode De becomes

TABLE IV reverse biased with the discontinuity of inductor current iLc
C ONDITION FOR THE BOUNDARY BETWEEN CCM AND DCM’ S at time tz names the converter operating mode as DCM Lc .
The steady state expression of capacitor voltages are obtained
T ransition Condition with volt-second balance of the inductors utilizing Table I and
(1 − d)6 listed in Table II.
CCM →DCM La Kacritical =
d −i0 T + QLcOF F
(1 − d)4
=0 (26)
CCM →DCM Lb Kbcritical = T
d
Solving the above equation results the dimensionless pa-
CCM →DCM Lc Kccritical = (1 − d)2
rameter Kz as
2Lc
Kz = = d2z (27)
RT
inductor Lb changes and the associated state equations and Rearranging the (27) leads to
outcomes are furbished in Table I and Table II respectively.
The amp-second balance on the capacitor Cb results as fol- d2z − Kz = 0 (28)
lows: Taking the positive root of the quadratic equation (27) gives
−iLc dT + QLbOF F
=0 (21) the dz as
T
p
dz = Kz (29)
By solving (21), the dimensionless parameter Ky can be
By substituting the dz in Table II results the average values
obtained as given below
of converter states in DCM Lc as
2 2 √

2Lb (1 − d) (dy ) Vi d2 d + Kz 

Vi
Ky = = (22) 
 ILa =  VCa =
RT (d + dy ) d 



4
R (1 − d)√ Kz



 (1 − d)
2
 
The unknown parameter dy is obtained by rearranging the

 Vi d d + Kz 
 Vi
ILb = 3 VCb = 2
above equation as  R (1 − d) Kz  (1 − d)

 √


Vi d d + Kz Vi d

 

2 2
(1 − d) (dy ) − Ky ddy − Ky d2 = 0  VCc = 2 √
 
(23)  ILc =


2

R (1 − d) Kz (1 − d) . Kz
s ! (30)
dKy .B 4(1 − d)2 Finally, the voltage gain associated with DCM’s are tab-
dy = 2, B= 1+ 1+ (24)
2(1 − d) Ky ulated in Table III and graphically represented in Fig. 5(a),
Fig. 5(b), and Fig. 5(c) along with duty cycle respectively.

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 This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
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JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 7

TABLE V
C OMPARISON BETWEEN PROPOSED CONVERTER AND OTHER CONVERTERS .

Component count VSW /Vin @ O/P voltage RF @ d@ MCCMmax

Converter in Voltage gain VSW CIC
MCCM = 1 polarity MCCM = 1 MCCM = 1 @ d = 0.8
S L C D T
d2 V0
[5] 2 2 2 2 8 4 Non-inverted No 1.0033 0.5 16
(1 − d)2 d2
d (2 − d) V0
[6] 2 2 2 2 8 3.415 Inverted Yes 0.5041 0.2928 24
(1 − d)2 d
d V0 (2 − d)
[7] 2 2 2 2 8 4.2369 Inverted Yes 0.4033 0.3819 20
(1 − d)2 d
d (1 + d) V0
[16] 2 3 4 3 12 2.2528 Non-inverted Yes 0.057 0.3333 36
(1 − d)2 d (1 + d)
2d V0
[17] 2 2 3 3 10 3.7327 Inverted Yes 0.057 0.2679 40
(1 − d)2 d
3d V0
[12] 1 3 5 3 12 1.333 Inverted No 1.7359 0.25 12
1−d 3d
3d V0
[15] 1 4 6 3 14 1.333 Non-inverted Yes 0.057 0.25 12
1−d 3d
d (2 − d) V0
[11] 1 2 2 3 8 2 Inverted No 1.5578 0.2928 24
(1 − d)2 d (2 − d)
2d V0
[9] 1 2 3 2 8 1.5 Non-inverted No 1.4177 0.3333 8
1−d 2d
2d V0
[10] 1 3 4 2 10 1.5 Non-inverted No 1.4177 0.3333 8
1−d 2d
2d V0
[13] 1 3 4 2 10 1.5 Inverted Yes 0.057 0.3333 8
1−d 2d
d2 V0
[14] 1 3 3 5 12 4 Inverted Yes 0.057 0.5 16
(1 − d)2 d2
d2 (2 − d) V0
[18] 1 3 3 5 12 3.24 Inverted Yes 0.2066 0.445 19.2
(1 − d)2 d2 (2 − d)
d V0
Proposed 1 3 5 3 12 3.14 Non-inverted Yes 0.057 0.3178 100
(1 − d)3 d

S - Switches ; L - Inductors ; C - Capacitors ; D - Diodes ; T- Total number of components; RF - Ripple factor

C. Boundary Conduction Mode (BCM )
The BCM of a converter is when the inductor current
touches the zero exactly at the end of switching cycle. For
example as shown in Fig. 4, where the time tx will be
equals to tc . Hence, by replacing the di shown in Fig. 4
with (1 − d) in (16), (21) and (28), the boundary condition
between the CCM and the DCM’s is resulted as shown in
Table IV. The graphical representation of all the BCM’s i.e,
CCM →DCM La , CCM →DCM Lb , and CCM →DCM Lc
are shown in Fig. 5(d), Fig. 5(e), and Fig. 5(f).
IV. C OMPARISON
A comprehensive comparative investigation of presented
converter among other converters is facilitated in Table V
to demonstrate its performance in CCM. The investigation
consider various parameters like voltage gain, components
count, voltage stress across switch, output voltage polarity,
and input current nature. As illustrated, converters presented in
[5] and [12] having a switch in conjunction with input source.
Further in [7] the input source is in conjunction with capacitor
and switch. Which makes the input current as continuous but
due to capacitive switching an additional ripple content is
injected and which is not admissible. Whereas, the proposed
converter and the converters presented in [6], [15] and [14]
are employed only an inductor in series with the input source.
Hence, its leads to less ripple input source current. The input
current ripple is quantified by finding the ripple factor of
input current of each converter and given in Table V. The
proposed converter is having a ripple factor of 0.057 due to its
continuous input current as like in converter presented in [14].
Furthermore, considering the worst case duty ratio as 0.8, the
maximum voltage gain of the each converter shown in Table V
is calculated and tabulated in Table V. It can be seen that the
proposed converter delivers a voltage gain of 100 which is too
high when compared with its par converters. In the aspects
of device count, single switch and continuous input current,
the proposed converter exhibits non inverting output voltage
polarity when compared to remaining converters. Furthermore,
the proposed converter and converter presented in [15] exhibits
same favourable features. But, the SEPIC based converter [15]
employs more device count when compared with the proposed
converter which leads to increase in size. Finally, the proposed
converter is benefited with less switch voltage stress (i.e, duty
ratio times) in comparison with its counterpart in [14] as

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JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 8

1
η= √
√ × 100% (31)
rDSON d rLa d rLb d 2
rLc 1 d 3d − d2 + 1 − d VF
2
1+ + + + +
R (1 − d)6 R (1 − d)6 R (1 − d)4 R (1 − d)2 (1 − d)
3 V0
0.5fs (tf + tr ) rCa d3 rCb 1 rCc 1
+ 3 + + +
(1 − d) R (1 − d)5 R (1 − d)3 R 1−d

shown in Fig. 6(b). TABLE VI

In addition, a graphical representation of voltage gain I NDUCTOR AND CAPACITOR DESIGN VALUES .
comparison with variation of duty cycle among proposed and
refereed converters is presented in Fig. 6(a). Furthermore, the Parameter Symbol Value
quantified voltage stress ratio on switch at a voltage gain of Vi (1 − d)3 V0
one for proposed converter and its par converters is given La dTs = = 450µH
∆iLa ∆iLa fs
Table V. From the Table V, it can be seen that the proposed
VCa (1 − d)2 V0
converter is having a reduction of 21.5% voltage stress ratio on Inductors Lb dTs = = 1.8mH
∆iLb ∆iLb fs
switch and non-inverted voltage polarity when compared with
VCb (1 − d) V0
its par converter in [14]. Furthermore, the converter in [15] Lc dTs = = 3.6mH
∆iLb ∆iLc fs
is having better reduction in voltage stress ratio with limited
maximum voltage gain of 12 and which is 12% of proposed QCa V0 d2
Ca = = 47µF
converter maximum voltage gain. In addition, the converter in ∆VCa 2∆vCa (1 − d)2 Rfs
[15] utilizes four inductors and a total component count of QCb V0 d
Capacitors Cb = = 47µF
14 which is higher the proposed converter component count. ∆VCb 2∆vCb (1 − d) Rfs
Basically, the proposed converter provides amenable degree of QCc V0 d
Cc = = 100µF
freedom in terms of duty cycle for high voltage gain in step up ∆VCc ∆vCc Rfs
mode instead of going for extreme duty cycles. Furthermore,
it exhibits better buck gain when compared with the converters
presented in [15] and [12]. Eventually, the presented converter TABLE VII
display an remarkable performance with relative converters as C OMPONENTS AND PARAMETER SPECIFICATIONS OF PROPOSED
CONVERTER HARDWARE PROTOTYPE
presented in Table V. Finally, an effectiveness index (EI) is
utilized to evaluate the power density of the converter and
Details
which illustrated for the proposed converter along with the Parameter Symbol
other converters shown in Fig. 6(c). Where, EI is the ratio of Boost mode Buck mode
voltage gain to the number of utilized elements. Input voltage Vi 30V 30V
Output power P0 100W 30W

V. E XPERIMENTAL RESULTS Voltage gain M 4 0.875

Duty ratio d 0.5 0.3
To validate the theoretical analysis provided in CCM op-
Switch S IRFP460
erating mode, a laboratory prototype is developed and tested
with 100 W in boost mode and 30 W in buck mode. The Switching frequency f 50 kHz
component values of inductor and capacitor are tabulated in Da and Db NTSV20U100CTG
Diodes
Table VI along with its design equations where the duty ratio Dc , Dd and De MBR20200CTG
and the ripple current are chosen as 0.5 and 20% of respec-
tive inductor current. Further, the semiconductor components
which are utilized to built the converter prototype are detailed TABLE VIII
in Table VII and its converter part converter presented in [14] C OMPONENTS AND PARAMETER SPECIFICATIONS OF CONVERTER
HARDWARE PROTOTYPE IN [14].
are detailed in Table VIII. The experimental verification is
done at the full load with input voltage of 30 V as specified
in Table VII. Details
Parameter Symbol
A TI based DSP TMS320F28379D is utilized to generate Boost mode Buck mode
the driving signal to the MOSFET along with the driver Input voltage Vi 20V 20V
circuit associated with the IC TLP350. In addition, voltage Output power P0 33.75W 1.48W
and current probes of N2863B and YOKOGAWA 50 MHz/30 Voltage gain M 2.25 0.445
ARMS; oscilloscope of DSO-X-2024A and APLAB series
Switch S IRFP260N
L3230 power supply are used to perform the experiment and
capture the key waveforms of the converter. Furthermore, a Switching frequency f 40 kHz
TLP350 photocoupler is utilized to drive the MOSFET by Diodes Da -De DSEP8-06A
generating a isolated driving signal.

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JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX 9

ILa @ 0.2 A/div.

ILa @ 0.5 A/div.
ILb @ 0.5 A/div.
ILb @ 0.5 A/div.
VS @ 50 V/div.
VDa @ 50 V/div. VDb @ 50 V/div. VDd @ 50 V/div.

Time @ 10 µs/div.
Time @ 10 µs/div. Time @ 10 µs/div. Time @ 10 µs/div.

(a) (b) (c) (d)

Vin @ 50 V/div.
VCa @ 20 V/div. I0 @ 1 A/div.
ILc @ 2 A/div.
Vin @ 25 V/div. VCc = V0 @ 50 V/div.
VCb @ 20 V/div.

ILa @ 2 A/div.
VDe @ 100 V/div. VCa @ 50 V/div.

Time @ 10 µs/div. Time @ 10 µs/div. Time @ 10 µs/div. Time @ 10 µs/div. VLc @ 50 V/div.

(e) (f) (g) (h)

Vin @ 50 V/div.
ILb @ 1 A/div. ILa @ 2 A/div.
ILa @ 1 A/div. VCc = V0 @ 50 V/div.

Time @ 10 µs/div. VLc @ 50 V/div.

VDa @ 50 V/div. VD4 @ 50 V/div.

Time @ 10 µs/div. VSW @ 50 V/div. Time @ 10 µs/div. Time @ 10 µs/div.

(i) (j) (k) (l)

Fig. 7. Experimental results, Buck mode - (a) ILa &VS . (b) ILb &VDa . (c) ILa &VDb . (d) ILb &VDd . (e) ILc &VDe . (f) VCa , Vin &ILb . (g) I0 , VCa &VCb .
(h) Vin , V0 &VLc ., Boost mode- (i) ILa &VSW . (j) ILb , &VDa . (k) ILa &VDd . (l) Vin , V0 &VLc .

The proposed buck-boost converter is tested at a voltage

gain of 4 in boost mode and 0.875 in buck mode with
96 94

Theoretical
92
Theoretical the respected duty ratio d which is given in Fig. 5(a). The
Experimental Experimental
94
90
experimental results of the converter in both boost and buck
Efficiency (%)

88
Efficiency (%)

92
86
mode are demonstrated in Fig. 7. It is worthwhile to mention
90
84
that, the experimentally measured and theoretical values are
82

88 80
moderately different due to the assumptions considered while
78
carrying out the theoretical analysis.
86
0 20 40 60 80 100 120 140 160 180 200 220
0 20 40 60 80 100 120 140 160 180 200 220

Output power (W) Output power (W)

The input current (current flowing the inductor La ) and the
(a) (b) voltage stress across the power switch are shown in Fig. 7(a).
96
95.05
94.36
100
Where, the average value of current ILa is recorded as 1.2 A
94
93.8
93.69
93.02
92.36
91.72
90
92.86
91.37
89.91
88.52
87.15
85.84
84.56
is slightly greater than the theoretical value of average current
83.32
92
Efficiency (%)

82.11
92.33 91.08 80.95

(ILa =1 A). Fig. 7(b) represents the current through inductor

Efficiency (%)

90.44 80 78.07

90.91 89.82
90 89.21
70.88

88
89.53

88.19
70
64.9 Lb and the voltage stress on the Da . It can be seen that, the
60
59.85

86
86.9

85.64
55.53

51.79
current ILb is about 0.75A and the blocking voltage on diode
84 50 48.52

82
Proposed converter

Converter in [14]
84.41

83.22
40
Proposed converter

Converter in [14]
45.64
43.09
40.8
Da is about 43 V. The blocking voltage on the diode Db
82.06

0 20 40 60 80 100 120 140 160 180 200 220 0 20 40 60 80 100 120 140 160 180 200 220
shown in Fig. 7(c) is about 20 V which is approximately equal
Output power (W) Output power (W)
to the stated theoretical value. Fig. 7(d) shows the voltage
(c) (d) stress on the diode Dd which is about 27 V. The current
Pd
through the inductor Lc and voltage stress across the diode
Pd
68% De are depicted in Fig. 7(e) with average current of 1.8 A
37% and blocking voltage of 88 V which are around the theoretical
values. The input voltage and voltage across the capacitor Ca
PSW along with with input current ILa are depicted in Fig. 7(f)
46% PSW

Pc 21%
where with the applied input voltage of 30 V at the operated
PL 2%
15%
PL

9%
PC

2%
duty ratio results the voltage VCa around 42 V. Further, the
intermediate capacitor Cb voltage VCb is depicted in Fig. 7(g)
(e) (f)
along with output current and voltage VCa . The voltage across
Fig. 8. Comparison of efficiency between theoretical and experimental: (a) the capacitor resulted around 60 V and which is in par with
Boost mode. (b) Buck mode., Efficiency versus output power: (c) Boost mode. the theoretical voltage. Finally, the output voltage V0 = VCc
(d) buck mode., Power loss distribution: (e) Boost mode. (f) Buck mode.
and voltage across the inductor VLc are shown in Fig. 7(h)
along with the input voltage. The measured average values of

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JOURNAL OF LATEX CLASS FILES, VOL. XX, NO. X, AUGUST XXXX
25.8 V for an input voltage of 30V is close the theoretical
values presented in Section III. Furthermore, the experimental
recorded waveforms of the proposed converter during boost
mode are depicted in Fig. 7(i), Fig. 7(j), Fig. 7(k), and Fig. 7(l)
respectively.
Finally, the efficiency of the proposed converter using (31) is
compared with its contemporary converter in [14] by varying
output power. From Fig. 8(c) and Fig. 8(d), it can be seen
that the proposed converter delivers better efficiency in both
boost and buck mode in comparison with converter in [14]
with same number of components. The loss breakdown of the
proposed converter in both boost and buck modes is shown in
Fig. 8(c) and Fig. 8(d), respectively. Further, the efficiency
of the proposed converter is measured and compared with
theoretical calculations as shown in Fig. 8(a) and Fig. 8(b)
for both buck and boost modes of operation.
VI. C ONCLUSION
In this article, a new single switch continuous input current
non-isolated buck-boost converter with wide voltage conver-
sion ratio and single switch is presented. The steady state
analysis of the converter in both CCM and named DCM’s
are discussed in detail and presented with respective voltage
conversion ratio’s. In addition, a detailed comparative analysis
is done among the proposed and its contemporary converters
in voltage gain, voltage stress ratio, and effectiveness index
aspects. From the comparison, it can be inferred that the
proposed converter results better voltage gain with optimum
component count as well as lower voltage stress. Furthermore,
the effectiveness index comparison confirms the prominence
of the proposed converter over its contemporary converters.
Finally, the prototype of the proposed buck-boost converter is
fabricated and tested in laboratory for both buck and boost
mode of operation. The experimental results promises the
validation of the converter theoretical analysis in CCM.
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