TIRIS Automotive Devices: Analog Front End IC TMS37122

August ’01 Chapter 3.
Application
TIRIS Automotive Devices

Analog Front End IC TMS37122
Reference Guide
11-09-21-046 August 2001
1
Analog Front End IC TMS37122 - Reference Guide August ’01
First Edition- August 2001

This is the first edition of this manual, it describes the following equipment:
Analog Front End IC TMS37122
Texas Instruments (TI) reserves the right to make changes to its products or services or to dis-
continue any product or service at any time without notice. TI provides customer assistance
in various technical areas, but does not have full access to data concerning the use and appli-
cations of customer's products.
Therefore, TI assumes no liability and is not responsible for customer applications or product
or software design or performance relating to systems or applications incorporating TI prod-
ucts. In addition, TI assumes no liability and is not responsible for infringement of patents
and/or any other intellectual or industrial property rights of third parties, which may result
from assistance provided by TI.
TI products are not designed, intended, authorized or warranted to be suitable for life support
applications or any other life critical applications which could involve potential risk of death,
personal injury or severe property or environmental damage.
The TIRIS logo and the word TIRIS are registered trademarks of Texas Instruments Incor-
porated.
Copyright  2001 Texas Instruments Incorporated (TI)
This document may be downloaded onto a computer, stored and duplicated as necessary to
support the use of the related TI products. Any other type of duplication, circulation or storage
on data carriers in any manner not authorized by TI represents a violation of the applicable
copyright laws and shall be prosecuted.
2
August ’01 Preface
About This Guide

This manual describes the TIRIS 3D-Analog Front End integrated circuit (TMS37122), it de-
scribes the functions and parameters of the 3D-Analog Front End. This circuit enables expan-
sion of a current Remote Keyless Entry system to Keyless Entry function. It provides the
information that you will need in order to use the integrated circuit in your RFID system. It
is generally targeted at security system suppliers designing hardware and software for car
manufacturers.
Conventions
WARNING:
A WARNING IS USED WHERE CARE MUST BE TAKEN, OR A CERTAIN
PROCEDURE MUST BE FOLLOWED IN ORDER TO PREVENT INJURY
OR HARM TO YOUR HEALTH.
CAUTION:
This indicates information on conditions which must be met, or a
procedure which must be followed, which if not heeded could
cause permanent damage to the equipment or software.
Note:
Indicates conditions which must be met, or procedures which must be fol-
lowed, to ensure proper functioning of the equipment or software.
Information:
Indicates information which makes usage of the equipment or software eas-
ier
If You Need Assistance

Application Centers are located in Europe, North and South America, the Far East and Aus-
tralia to provide direct support. For more information, please contact your nearest TIRIS
Sales and Application Center. The contact addresses can be found on our home page:
http://www.ti-rfid.com
3
Document Overview
Page
Chapter 1: Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 General Features ................................................................................. 7
1.2 References........................................................................................... 7
1.3 Circuit Description................................................................................ 8
Chapter 2: Electrical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 General .............................................................................................. 15
2.2 Power Supply..................................................................................... 17
2.3 Power-on-reset .................................................................................. 22
2.4 Limiter Circuits ................................................................................... 23
2.5 Wake Detector ................................................................................... 24
2.6 End-of-burst Detector......................................................................... 25
2.7 Pulse Position Demodulator............................................................... 25
2.8 Control Unit ........................................................................................ 26
2.9 FSK Modulator ................................................................................... 31
2.10 Configuration Memory........................................................................ 32
2.11 Resonant Circuit Trimming ................................................................ 44
Chapter 3: Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.1 Passive Entry Function ...................................................................... 49
3.2 Passive Start Function ....................................................................... 52
3.3 Battery Backup Function.................................................................... 54
3.4 Immobilizer Function.......................................................................... 56
3.5 Anti-Collision Function ....................................................................... 56
Chapter 4: Product Specification Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.1 Absolute Maximum Ratings ............................................................... 59
4.2 Recommended System Operating Conditions................................... 60
List of Figures
Page
Figure 1: TSSOP Package (Top View) .......................................................... 7
Figure 2: System Arrangement of 3D-Analog Front End IC TMS37122 ........ 8
Figure 3: Typical 3D-AFE Application Including Battery Backup Function... 10
Figure 4: Block Schematic of TMS37122..................................................... 16
Figure 5: Standard Battery Supply - Schematic ........................................... 17
Figure 6: Schematic for Rechargeable Battery Supply ................................ 18
Figure 7: Schematic for Battery Backup Supply........................................... 19
Figure 8: Test Arrangement with Digital Interface Test Box and PC............ 21
Figure 9: Schematic of Reset Flow .............................................................. 22
Figure 10: TMS37122 Limiter Circuits.......................................................... 23
Figure 11: Block schematic of Wake Detector ............................................. 24
Figure 12: EOB Detector and Pulse Position Modulator Function ............... 25
Figure 13: Overall State Diagram of Control Unit......................................... 27
Figure 14: Initialization State Diagram of TMS37122................................... 28
Figure 15: Control Unit Timing Diagram....................................................... 29
Figure 16: Wake Pattern Detection State Diagram ...................................... 30
Figure 17: State Diagram of Transparent Mode........................................... 31
4
August ’01 Preface
Figure 18: State Diagram of LF Transmission Mode ................................... 32

Figure 19: Memory Organisation.................................................................. 33
Figure 20: Default Memory Content ............................................................. 34
Figure 21:VWAKEA Sensitivity Diagram...................................................... 36
Figure 22: System Schematic for Indoor/Outdoor Detection........................ 37
Figure 23: VWAKEB SENSITIVITY Diagram ............................................... 38
Figure 24: Timing Diagram for Test Mode PTx04 ........................................ 43
Figure 26Timing Diagram for Test Mode PTx18 .......................................... 46
Figure 28: Passive Entry Wake Pattern Detection ....................................... 50
Figure 29: Passive Entry Challenge/Response Timing................................ 51
Figure 30: Passive Start Wake Pattern Detection........................................ 53
Figure 31: Timing Diagram for Battery Backup Function ............................. 55
Figure 32: Timing Diagram of Anti-Collision Function.................................. 57
Figure 33: Measurement System:Timing, Dynamic Current & Sensitivity.... 67
List of Tables
Page
Table 1: Description of the Device’s Pins..................................................... 11
Table 2Default Function Configuration......................................................... 33
Table 3: Wake Sensitivity VWAKEA/1 Options ............................................ 35
Table 4: Passive Start Sensitivity Options ................................................... 37
Table 5: Counter Definition for Pulse Position Demodulation ...................... 39
Table 6: Counter Definition for Pulse Position Demodulation ...................... 41
Table 7: Wake Pattern Waiting Time Options .............................................. 42
5
CHAPTER 1
Product Description
Chapter 1: Product Description

This chapter introduces the TIRIS 3D-Analog Front End (AFE) low voltage, low current in-
terface circuit for microcomputer controlled Automotive Keyless Entry Systems.
Topic Page
1.1 General Features........................................................................................7
1.2 References..................................................................................................7
1.3 Circuit Description.....................................................................................8
6
August ’01 Chapter 1. Product Description
1.1 General Features

• Analog Front End IC for RF Identification Systems
• Supports 120 … 140 kHz Systems
• Low Standby Current of typical 5 µA
• < 10 mV peak-to-peak sensitivity
• Interfaces to up to three antennas
• Receives and demodulates AM Data
• Threshold Detector for wake of an external microcomputer
• 16-bit Wake Pattern Detection
• Separate Threshold Detector supports indoor/ outdoor detection
• On Chip Antenna Trimming using EEPROM controlled capacitor
arrays
• On-chip digital Channel Sensitivity Adjustment
• Provides a battery-less backup mode using TIRIS compatible FSK
transmission
• Designed for Automotive Requirements
• 16-pin TSSOP Package
Figure 1: TSSOP Package (Top View)
1 16
2 15
3 14
4 TMS37122 13
5 12
6 11
7 10
8 9
1.2 References
[1] Digital Signature Wedge Transponder RI-TRP-B9WK Reference Manual,
11-09-21-029, July 14, 1998
[2] Transponder Signal Collision Avoidance System U.S. Patent Number 5,793,324,
August 11, 1998
[3] TSSOP Package Outline, Spec. No: PKGTS0001, JEDEC Ref: MO-153
7
1.3 Circuit Description

The 3D-Analog Front End (AFE) circuit TMS37122 is a low voltage, low current interface
circuit for microcomputer controlled Automotive Keyless Entry Systems. With few external
components it provides a 120 to 140 kHz inductive Low Frequency Channel for high-speed
data transfer to a microcomputer or other control circuits.
Typically the circuit is used to expand current Remote Keyless Entry systems, consisting of
a Microcomputer and an UHF Transmitter, to Passive (Keyless) Entry function see Figure 2.
The battery-powered device is able to detect amplitude modulated Low Frequency (LF) sig-
nals from a LF Transmitter/Receiver Unit from an extended distance compared to battery-less
devices.
The modulation principle used by the Transmitter should be based on a 100% amplitude mod-
ulation. Pulse Position Modulation (negative transition) must be used for transmission of an
optional wake pattern, which is demodulated in the circuit without Microcomputer involve-
ment. The encoding scheme of the remaining protocol data is free selectable depending on
system requirements, hardware and software capability.
The achievable distance between transmitter and transponder and the possible data speed de-
pends on the size and quality factor of the antennas. Typical achievable distances are in the
range of 1.5 to 2.5 m.
Figure 2: System Arrangement of 3D-Analog Front End IC TMS37122
Transceiver / Base Station Identification Device
UHF
Tx/Osc
UHF
Driver
Response-Channel
Trigger
(Door Handle) UHF
Receiver 3D uC
Antenna 1 LF Res- AFE
Control (customer
ponse for Backup
Unit design)
LF
TX/RX
Unit RKE
LF Write-Channel
(ASIC) buttons
The 3D-AFE can be equipped with up to three antennas covering the three space axes to avoid
reduced detection ranges due to antenna orientation (see Figure 3). The antenna resonant cir-
cuits can be tuned independently to resonance with internal EEPROM-controlled trim capac-
itor arrays accessible by a digital Trim and Test Interface.
The circuit can be completely disabled by the Microcomputer and consumes in this state a
very low quiescent current (Iquiet). In stand-by mode the current consumption is still so low
that a continuous application is feasible (Istdb). Even in case of interference the circuit has a
low current consumption due to watchdog circuit and supervision logic. The Microcomputer
is only woken and supplied with the recovered digital data and clock when a valid signal is
received.
8
Typically the device is supplied by a 3 V Lithium-battery. A built-in voltage regulator allows

a battery charge of appropriate battery types or a battery back-up function.
In back-up function it is possible to transmit data back to the base station via one of the low
frequency channels without using the UHF Transmitter. This mode is less power consuming
compared to an UHF transmission but requires a charge-up of a charge capacitor during an
extended wake period.
All three antennas can receive energy from the base station and supply the internal circuits of
the device with energy derived from the magnetic field at the antenna coils. The antenna volt-
ages of the different antennas can reach a very high level due to induced voltage. To avoid
damage of the integrated circuit, the inputs RF and VCL, are protected by Voltage Limiter
circuits.
The transmission back to the base station is using the TIRIS HDX FSK modulation and the
telegrams can therefore be made compatible to current battery-less TIRIS transponder sys-
tems. For this purpose a simple two-wire interface to the Microcomputer can be used.
A complete Identification Device consists of the following parts:

- External components
Antenna 1 (LR1)
Resonant Circuit Capacitor 1 (CR1)
Antenna 2 (LR2)
Antenna 3 (LR3)
Charge Capacitor (CL)
Battery
Buffering Capacitor (Cbat)
Battery Backup De-coupling Diode (Dbat), if function is desired
VCCO Jumper (J1), if Battery Backup or Battery Charge is desired
Microcomputer
UHF Transmitter
Test/ Trimming Interface Connector
- 3D-Analog Front End IC TMS37122
9
Figure 3: Typical 3D-AFE Application Including Battery Backup Function
PASSIVE ENTRY/ PASSIVE START TRANSPONDER WITH BATTERY BACKUP FUNCTION
RF3
RF2
TEST/TRIMMING INTERFACE
RF1
LR3 LR2 LR1 3-D ANALOG FRONT-END
CR3 CR2 CR1
TMS37122 TEN
TCLK
TDAT
VCL
GND VCCO VBAT MOD TX WDEEN WAKE EOBA CLKA/M
CL
Dbat
VCC OUT OUT OUT INT/INP INT/INP TIMER

BATTERY
MICROCOMPUTER
GND OUT
UHF TRANSMITTER
The pinning and a description of each of the pins on the TMS37122 is given in Table 1.
Note:
Apart from the test inputs TCLK, TDAT and TEN, the logic inputs do not
have internal pull-down resistors in order to save current. Therefore defined
states from the connected Microcomputer are required. If pins are not used, a
connection to GND is necessary.
10
Table 1: Description of the Device’s Pins
Pin # Pin Dir Description
1 GND - Device ground pin. It is the ground potential for all device signals.
Output of the on-chip voltage regulator. This voltage regulator

regulates the VCL voltage down to 3.0 V (nominal). The VCCO voltage
is used to supply internal logic, as well as the external Micro-computer
2 VCCO Out
(in Backup Mode). The VCCO output has a de-coupling feature, in
case an externally applied voltage at pin VCCO exceeds the VCCO
voltage. It also ensures that the battery is not discharged via VCCO.
Device connection pin for the antenna resonator 3. The antenna

3 RF3 In resonator consists of a low Q, parallel LC circuit. The other end of the
resonator is connected to pin VCL.
This is the 'Test Data' input and output for the test and configuration
interface. When data has to be shifted in, the data has to be applied at
4 TDAT I/O
TDAT. When test results are to be shifted out, the data is available at
pin TDAT.
Test Enable input for the test and configuration interface. The test
command is shifted in when TEN is low. The test command is
5 TEN In activated by setting TEN to high.
The TEN pin is also used to apply the programming voltage for the
EEPROM cells.
Device supply pin for the Transponder's Passive Entry circuitry. A

battery with 3.0 V nominal supply voltage must be connected here. A
6 VBAT In
capacitor equal to or greater than 22 nF should be connected between
VBAT and GND to buffer the VBAT supply.
Output of the 'End of Burst' Detector. The Microcomputer receives

amplitude modulated commands and data from the Base Station via
7 EOBA Out this pin. The Microcomputer might use the EOBA signal together with
the signal CLKA/M to demodulate the received signals. However it is
not a must to demodulate the EOBA signal using the CLKA/M signal.
Clock output pin of the Wake Detector Clock Regenerator. This clock
signal can be used for demodulation of the received EOB signals. It
can be switched off by the configuration Memory.This pin has a second
function when the Backup Mode is active. If TX = high the output
8 CLKA/M Out represents the signal of Antenna 1 Transmission Mode Clock
Regenerator divided by 16 (CLKM). This clock signal is used by the
Microcomputer to assert data to the MOD input synchronized to the
carrier signal. CLKM output is not influenced by the configuration
Memory option.
Wake Detector output pin. When the 3D AFE device has detected a
RF signal above the relevant threshold for a required time and if a
9 WAKE Out
correct WAKE Pattern has been detected, this output is set to logic
high level in order to wake the Microcomputer.
This is the device's 'Write Distance Expander Enable' input pin. The
10 WDEEN Passive Entry circuitry on the device is enabled when pin WDEEN is
set to high
11
Table 1: Description of the Device’s Pins
Pin # Pin Dir Description
Activation pin for Antenna 1 Transmission Mode. When this pin is set,
the antenna resonator 1 is initiated to oscillate. The serial data to be
11 TX
transmitted must be applied at MOD pin synchronous to CLKA/M
output.
Modulation input pin used for the LF HDX FSK response. When this
pin is at low level, the on-chip modulation capacitor is not connected.
12 MOD In Thus the resonator 1 is operating at 134.7kHz (nominal). When this pin
is at logic high level, the on-chip modulation capacitor is connected
and the resonator 1 is operating at 123.7kHz (nominal).
Test Clock input for the test and configuration interface. The data is
13 TCLK In
shifted in and out with the rising edge of TCLK.
Device connection pin for the antenna resonator 2. The antenna

14 RF2 In resonator consists of a low Q, parallel LC circuit.
The other end of the resonator is connected to pin VCL.
Connection pin for the antenna resonator 1. The antenna resonator

consists of a low Q, parallel LC circuit. The other end of the resonator
15 RF1 In is connected to pin VCL. The antenna resonator 1 has the additional
feature of being able to send data back to the base station via LF HDX
FSK modulation.
Device supply pin for LF HDX operation. The charge capacitor CL is

connected to pin VCL. The energy, which is received during the LF
16 VCL In
charge up phase, is stored on CL and supplies the LF HDX part via the
pin VCL.
12
CHAPTER 2
Electrical Description
Chapter 2: Electrical Description

This chapter describes the electrical circuitry of the 3D-Analog Front End (AFE) integrated
circuit TMS37122
Topic Page
2.1 General......................................................................................................15
2.2 Power Supply ...........................................................................................17
2.2.1 VBAT Supply........................................................................................17
2.2.1.1 Standard Battery Supply.............................................................17
2.2.1.2 Rechargeable Battery Supply .....................................................17
2.2.1.3 Battery Backup Supply ...............................................................18
2.2.2 VCL Supply ..........................................................................................19
2.2.2.1 Backup Mode..............................................................................19
2.2.2.2 Test Mode...................................................................................20
2.3 Power-on-reset.........................................................................................22
2.4 Limiter Circuits.........................................................................................23
2.5 Wake Detector ..........................................................................................24
2.6 End-of-burst Detector..............................................................................25
2.7 Pulse Position Demodulator ...................................................................25
2.8 Control Unit ..............................................................................................26
2.8.1 Off Mode ..............................................................................................28
2.8.2 Standby Mode ......................................................................................28
2.8.3 Init Mode ..............................................................................................28
2.8.4 Active Mode .........................................................................................28
2.8.4.1 Wake Pattern Detection..............................................................29
2.8.4.2 Transparent Mode ......................................................................30
2.9 FSK Modulator .........................................................................................31
continued on next page
13
Continued
Topic Page
2.10 Configuration Memory.............................................................................32
2.10.1 Memory Organisation...........................................................................32
2.10.2 Default Memory Content ......................................................................33
2.10.3 Configuration Options ..........................................................................35
2.10.3.1 Wake Sensitivity VWAKEA/1 ......................................................35
2.10.3.2 Passive Start Sensitivity VWAKEB/1/2/3 ....................................36
2.10.3.3 Pulse Position Demodulator Threshold ......................................38
2.10.3.4 Wake Pattern Detection Flag 'NO_WAKE' .................................39
2.10.3.5 Write Distance Expander 2 Flag 'NO_WDE2'.............................39
2.10.3.6 Write Distance Expander 3 Flag 'NO_WDE3'.............................39
2.10.3.8 Passive Entry Wake Pattern .......................................................40
2.10.3.9 Passive Start Wake Pattern........................................................40
2.10.3.10Telegram Duration 'C_TELEGR'.................................................40
2.10.3.11Wake Pattern Waiting Time 'C_WAIT' ........................................41
2.10.4 Memory Programming..........................................................................42
2.10.5 Memory Read.......................................................................................43
2.11 Resonant Circuit Trimming.....................................................................44
2.11.1 Resonance Frequency Measurement ..................................................45
2.11.2 Trimming EEPROM Programming .......................................................47
2.11.3 Modulation Frequency Check ..............................................................47
14
August ’01 Chapter 2. Electrical Description
2.1 General
The TMS37122 consists of the following main function blocks (see Figure 4):
- RF Limiter (3 fold)
- 8-bit Trimming Circuit (3 fold)
- Rectifier (3 fold)
- VCL Limiter
- Voltage Regulator (VCCO) with reverse current protection (diode)
- Clock Regenerator for Pluck Circuit and modulation clock divider.
- Divider for modulation clock (CLKM)
- Continuous Pluck Circuit (Antenna 1 only)
- Pluck Synchronization for modulation function (Antenna 1 only)
- Modulation Capacitor CM (Antenna 1 only)
- Wake Detectors (3 fold)
- EOBA Detector (3 fold)
- Signal Selector
- Pulse Position Demodulator (for Wake Pattern only)
- Wake Pattern Comparator
- Watchdog (supervising CLKI signal)
- Control Unit
- Test logic
15
WDEEN TX
3D-ANALOG FRONT-END IC TMS37122 TEST

VBAT
EOBA PTx04/07 WAKE
DETECTOR
RF3 WAKE WAKEI1 CLKA/M
LR3 DETECTOR 3 WAKEI2
CI3 WAKEI3 CONTROL UNIT
VWAKE A2/3
RECTIFIER
CR3 CT1 CT8 WITH
RF EOBA
VWAKE B2/3 WATCH- WDG CONFIGURATION
LIM3 DOG EEPROM
CLKI
VBAT
VCL TEST
PTx04/07 SELECT
TEST
8 Bit PTx34
SINGLE TRIMMING
WAKE PATTERN
PLUCK EEPROM
COMPARATOR
EEPROM WAKE1
EEPROM WAKE2
SELECTOR
TEST EOBA
SIGNAL
PTx38 DETECTOR
RF2
WAKE EOBI PULSE POSITION
LR2 DETECTOR 2 DEMODULATOR
CI2 VWAKE A2/3
RECTIFIER
CR2 CT1 CT8

RF VWAKE B2/3
LIM2.
TEST
PTx04/07
VBAT
VCL
8 Bit TEST
TRIMMING PTx24
SINGLE
EEPROM
PLUCK
EOBA
TEST DETECTOR
PTx28
WAKE
DETECTOR 1
VWAKE A1
VWAKE B1
TEST
VBAT PTx04/07
RF1
LR1
CI1
CR1 CT1 CT8 CM VCL VCL VCL CLKM
RF
LIM.
RECTIFIER
TRp CONTINUOUS CLOCK DIVIDER

PLUCK REGENE-
VCL : 16
CIRCUIT RATOR
VCL
8 Bit
CL VCL VCL PLUCK
TRIMMING
LIM. EEPROM SYNC.
TRM
GND
VOLT.
VCCO REG.
TEST
VBAT TEST PTx18
PTx34
TEST
PTx24 TEST
LOGIC
TEST
PTx14
VCL
VBAT
MOD TCLK TDAT TEN

3DBD01B.CH4
Referenced to VBAT
Figure 4: Block Schematic of TMS37122
16
2.2 Power Supply

2.2.1 VBAT Supply
Most parts of the 3D-AFE are supplied via VBAT input. Typically a 3 V Lithium Battery is
used but also the use of rechargeable batteries is possible. Directly at the TMS37122 input a
Buffer Capacitor (Cbat) should be provided with short connections to VBAT and GND pin.
Eventually also at the Microcomputer and UHF Transmitter input additional capacitor are re-
quired in order to meet the specified maximum power supply ripple (Vripple).
2.2.1.1 Standard Battery Supply

If Standard Battery Supply is desired, the VCCO output of the 3D-AFE is not used. Battery
Backup function (transmission via LF Channel in case of too low battery voltage) is not us-
able. The Charge Capacitor CL can therefore have the recommended standard value. Greater
capacitor values do not influence negatively the Write Distance Expander function. Beside
this it is possible to provide an additional LF Channel in order to overcome interference prob-
lems in this frequency band. The LF Response must take place before the UHF transmission
and is only possible if the battery voltage is above the minimum specified value, because the
supply of Microcomputer and 3D-AFE is not backed up.
Figure 5: Standard Battery Supply - Schematic
VCL
VCL
LR
CR
VOLT.
REG.
RF
RF
CL >= 22nF Rectifier
Diode
GND
VCCO
µC
VBAT
VBAT
Battery
Cbat = 22nF
3DSUP01.CH4
2.2.1.2 Rechargeable Battery Supply
If you are using a rechargeable battery, the restrictions described in section 2.2.1.1 can be
overcome. The de-coupling diode at the battery is eliminated (see Figure 6).
Weak batteries can be refreshed in the application or in special charge stations. The Identifi-
cation Device must therefore be placed in a strong continuous RF field so that the Charge Ca-
pacitor voltage (VCL) is in limitation. In this case the Voltage Regulator supplies high
enough voltage and current to the battery via output VCCO (short circuit between VCCO and
VBAT).
17
In case of very high field strength VCL decreases due to IC characteristic in the very near
distance range. To keep the maximum VCL it is recommended to connect a Schottky diode
(e.g. BAT42) between every RF input (RF1,RF2,RF3) and GND.
Figure 6: Schematic for Rechargeable Battery Supply
VCL
VCL
LR
CR
VOLT.
REG.
RF
CL >= 22nF RF
Rectifier
Diode
BAT42
GND
Rechargeable VCCO
Battery
µC
VBAT
VBAT
Cbat = 22nF
3DSUP02A.CH4
2.2.1.3 Battery Backup Supply
If you have a Battery Backup Supply option the non-rechargeable battery is de-coupled from
Microcomputer and 3D-AFE by a diode (see Figure 7). A Schottky-diode should be used to
minimize voltage drop.The charge capacitor CL must be increased to the µF range to be able
to supply the microcontroller during FSK response phase. Recommendations for calculation
of the capacity are given in section 2.2.2.1
A Low-Power Reset Circuit should supervise the Microcomputer supply voltage. If the min-
imum supply voltage (for example: 2 V) is reached, the Microcomputer will reset and the 3D-
AFE will go into Off-Mode because WDEEN is set to low. If the user of the Identification
Device tries to get into the car in Keyless Entry Mode by pulling the door handle, he will be
not successful, if he is too far away from the Base Station Antenna. This, because the Body
Controller will not get a response on his challenge because the 3D-AFE and Microcomputer
is off. After several trials the Body Controller can increase the Wake-up Time in order to
charge up the charge capacitor to a higher voltage. He reports this action also to the Identifi-
cation Device by using a special Battery Backup Command with the Challenge Data. The
User has to support the process by bringing the Identification Device nearer to the Body Con-
troller Antenna. When the field strength is so high that VCL reaches limitation, also VBAT
has reached via VCCO output a sufficient high value so that the Microcomputer starts. It will
initialize and enable the 3D-AFE via WDEEN.
Because of the received special command a transmission via UHF Channel will be avoided.
Response will be handled via LF Channel, which requires less current.
Also in case of Battery Backup function the use of Schottky diodes (e.g. BAT42) between RF
18
inputs (RF1, RF2, RF3) and GND is recommended to keep maximum VCL.
Figure 7: Schematic for Battery Backup Supply
VCL
VCL
LR
CR
VOLT.
REG.
RF
CL > = 2.2µF RF
Rectifier
BAT42 Diode
GND
VCCO
µC
VBAT
VBAT
Cbat = 22nF
Battery
3DSUP03A.CH4
2.2.2 VCL Supply

Circuit parts, which are only used during Backup Mode, are supplied by the charge voltage
VCL in the Charge Capacitor CL. CL is charged during Wake-up Time (tWake) in Backup
Mode or is fed externally during Test and Trimming Function.
2.2.2.1 Backup Mode

The capacitor value depends on the current consumption during response and the Response
Time (tTX). Because of high current consumption a supply of the UHF transmitter can typi-
cally not be considered. Therefore the Microcomputer uses LF Transmission in Battery Back-
up Mode. This voltage supply is only available in case of strong activation fields and
extended Wake Times. For calculation of the capacitor value the following information must
be available:
- Supply current of TMS37122 in Transmit Mode (Itx)
This current depends on the quality factor of the resonant circuit. At minimum quality
factor necessary for Backup Mode (Q=10), the current consumption Itx is the sum of
IVCL (~110µA) and Iact (~30µA).
- Supply current of the Microcomputer and supervision circuit (IµC)
This current is customer specific and depends on many factors. Currents of several
hundred microampere are practical.
- Required time for response over LF Channel (tTX).
For typical TIRIS frequency-scheme the maximum high bit duration is 135,6 µs.
Transmission of 96 bits therefore require maximum 13 ms. For security purpose it
should be calculated with 15 ms.
- Available VCL voltage range (dVCL).
19
The available voltage range depends on the voltage VCL, which can be charged into
CL during extended Wake-up Time and the minimum required supply voltage for the
oscillation maintenance circuit (Continuous Pluck Circuit). For proper function with
minimum 3 V should be calculated. Limitation of VCL can occur in worst case at 6
V. Therefore a VCL range of maximum 3 V should be defined.
The required capacitor is calculated with the following formulas:
Itot= Itx + IµC
CL [F] = Itot [A] * tTX[Sec] / dVCL [V]

Example:
Itot = 500µA
tTX = 15ms
dVCL = 3V
CL = Itot * tTX / dVCL = 2.5µF

If the capacitor Cbat is already in the µF range due to other reasons, CL can have less
capacity. It has only to supply the front-end part and the resonant circuit (IVCL). At a
quality factor of 10 at least a capacitor of 680nF will be required.
2.2.2.2 Test Mode

The resonant circuit of the Identification Device must be trimmed to optimum resonance after
assembly. Beside this the desired option bits must be configured in the 3D-AFE memory. For
this purpose a Test Interface is provided connected typically to Tester Unit. For engineering
purpose also a special Digital Interface Test Box, controlled by a PC via RS232 interface, can
be used (see Figure 8). Circuit diagrams for the Test Box can be delivered on request.
The Test Box is able to measure the oscillation frequency of each resonant circuit using sep-
arate test modes. During these tests VCL is fed with a stable voltage and the oscillation is trig-
gered via the test interface. The period duration is measured and reported via RS232 to the
PC. The voltage can either be supplied by a IEEE interface controlled power supply or by
power supplies in the Test Box.
20
Figure 8: Test Arrangement with Digital Interface Test Box and PC

PASSIVE ENTRY/ PASSIVE START TRANSPONDER WITH BATTERY BACKUP FUNCTION
RF3
RF2
LEVEL SHIFTER
RF1
LR3 LR2 LR1 3-D ANALOG FRONT-END
TEN
CR3 CR2 CR1 TMS37122
TCLK RS232
TDAT
µC
PC
VCL
GND VCCO VBAT MOD TX WDEEN WAKE EOBA CLKA/M
CL
DIGITAL IEEE
INTERFACE
TEST
BOX
VCC OUT OUT OUT INT/INP INT/INP TIMER VAR.
POWER
MICROCOMPUTER SUPPLY
GND OUT
VAR.
POWER
SUPPLY
UHF TRANSMITTER 15 V
POWER
SUPPLY
3DTST01B.DRW
The test interface consists of two input pins (TEN, TCLK) and one input/output pin (TDAT).
The digital input/output levels are referenced to VBAT, which can also be supplied via the
test interface if the battery is removed. The input TEN has a double function: after activation
of the Test Mode the programming voltage (VPP) is supplied via this pin.
TEN = 0V: Shift data in TDAT using TCLK
TEN = VBAT: Activate Test, decode test mode and switch test signals or data to
TDAT.
TEN = VPP: Apply programming voltage for EEPROM. TEN must already be at
VBAT, before programming voltage is applied.
TCLK = 0V: Prepare data at TDAT

TCLK = VBAT: Shift TDAT condition at positive transition
TDAT = 0: Low data. Change at negative transition of TCLK.

TDAT = VBAT: High data, externally supplied. Change at negative transition of TCLK.
TDAT = X: TDAT is digital output in certain test modes.
21
2.3 Power-on-reset
The TMS37122 does not include a power-on-reset circuit, which supervises the battery volt-
age. The circuit is reset by the Microcomputer via the WDEEN input (WDEEN='0'). It is ex-
pected that the current Microcomputer RKE system is already equipped with an efficient reset
circuit securing an initialization in case of supply voltage drop below 2 V (2.2 V).
If the Battery Backup function is used, we recommend to use a Low Power Supervisory cir-
cuit (Isupply < 1 µA). One device that could be used is:
- TPS3836/37 (Texas Instruments)
Figure 9: Schematic of Reset Flow
MR VDD VCC VBAT VCCO

RESET RST OUT WDEEN
TPS3836K25 MICROCOMPUTER TMS37122
CT GND VSS GND
V
4
3
VBAT
2
1
t
RESET
td td
WDEEN tinit tinit
BATTERY LIFE TIME BATTERY

BACKUP
22
2.4 Limiter Circuits

The TMS37122 has separate Limiter Circuits at the RF inputs, which prevents the high volt-
age parts of the circuit from overload (see Figure 10). The circuit limits the positive half-wave
with respect to ground. The negative half-wave is clamped to ground by the Rectifier Diode.
The peak-to-peak amplitude is therefore approximately two times the VCL voltage.
The common VCL pin has an additional VCL Limiter circuit. In case of strong fields the RF
signal can become very unsymmetrical and therefore the VCL could increase stronger than
the RF amplitude. In this case the VCL Limiter prevents the low voltage parts from being
overstressed.
The Voltage Regular characteristic also achieves a limitation of the VCCO voltage. Under all
VCL conditions the VCCO voltage will not exceed 4 V.
Figure 10: TMS37122 Limiter Circuits
LR
CR
RF3
RF3
RF
LIMIT.
LR
CR
RF
LIMIT.
RF2
RF2
VCL
VCL
LR
CR
VCL VOLT.
RECTIFIER LIMIT. REG.
DIODES
RF1
RF1
RF
LIMIT.
GND
VCCO
µC
VBAT
VBAT
3DLIM01.CH4
23
2.5 Wake Detector

Wake Detector 1…3, which are enabled by the Configuration Memory, are activated by the
Control Unit when WDEEN is activated. The first stage of the Wake Detector is an Automatic
Gain Control (AGC) Amplifier, which is initially at maximum amplification (see Figure 11).
In case a RF oscillation appears at the input (RF) the Automatic Gain Control starts to regu-
late. After a run-in time (tPdly) the regulation is stable and the EOB Detector is enabled. If
the amplitude of the RF Signal now exceeds a predetermined level (VWAKEA) a Clock Re-
generator is enabled.
At Wake Detector 1 the level can be configured by the Configuration Memory (Level Adjust/
Detect). Wake Detector 2 and 3 have maximum sensitivity.
The clocks provided by the Clock Regenerator are counted and supervised by the Clock Su-
pervision circuit, which activates at a certain state the EOB Detector. An analog watchdog
detects missing clocks. If at least 2 to 4 clocks are missed, the counter resets and restarts
counting. If the clock counter succeeds in counting to cWdly the WAKEI signal is set. Once
set, only WDEENIx can reset the WAKEIx signal.
Figure 11: Block schematic of Wake Detector
WAKE DETECTOR
CHECK
WAKEBx
LEVEL WAKEBx
DETECTOR
VWAKEB
VWAKEA
CONTROL UNIT
WDEENIx
LEVEL
ADJUST/ DETECT
CLKIx
EN
1pF
AGC CLOCK CLOCK
RFx WAKEIx
AMPLIFIER REGENERATOR SUPERVISION
EOB
EOBIx
DETECTOR
3DDBD01A.DRW
24
2.6 End-of-burst Detector

The Base Station transmits after a low frequency (LF) Wake burst data to the Identification
Device by means of 100% amplitude modulation (see Figure 12). At the resonant circuit of
the Identification Device this results in LF bursts and LF burst pauses or at least LF amplitude
drops depending on the duration of transmitted burst pause and the quality factor of the in-
volved resonant circuits. Coupling and therefore the distance between Base Station and Iden-
tification Device resonant circuit and the frequency deviation from ideal resonance frequency
has a big influence to the duration of the amplitude drop. In the near distance range amplitude
drops slower when the transmitter is deactivated and increases faster when activated. In the
far distance range the amplitude drops faster but increases slower.
After detection of a Wake signal the End-Of-Burst (EOB) Detector is activated (see Figure
4). The EOB-Detector has to detect any LF amplitude drop, which exceeds 50% of the initial
amplitude and has to convert it into a digital signal (EOBI). This signal is fed to a Pulse Po-
sition Demodulator circuit and, if it matches the memory defined pattern, to output EOBA.
Figure 12: EOB Detector and Pulse Position Modulator Function
WAKE WRITE READ
HIGH BIT LOW BIT LAST BIT

TRANSMITTER OFF
TXCT-
TRANSMITTER ON
toffi tonH toff tonL toff toff
twake tbitH tbitL tonL tRD
TRANSMITTER RF
near far
TRANSPONDER RF
END OF BURST (EOBI/EOBA)
toffTRP(near) toffTRP(near)
toffTRP toffTRP(far)
(far) tHdet tHdet
tHdet
WRITE DATA
3DWR01A.CH4
2.7 Pulse Position Demodulator

If Wake Pattern detection is activated, the Pulse Position Demodulator starts to work with oc-
25
currence of WAKEI for maximum 17 EOBI pulses. At each negative transition of EOBI a 7-
bit counter is reset and starts to count the regenerated RF clock (CLKI). If the counter reaches
the Pulse Position Modulation (PPM) threshold before the next negative transition, the
counter is stopped and a high bit is shifted in a compare shift register with this transition. The
PPM threshold is defined by the Configuration Memory and can be selected depending on the
desired data rate. In the other case the negative transition occurs before the threshold is
reached and a low bit is shifted.
Bit-by-bit the received pattern is compared with the two Wake-Pattern (Passive Entry, Pas-
sive Start) loaded from Configuration Memory during Standby-Mode and result is reported
to the Control Unit.
2.8 Control Unit

The Control Unit of the TMS37122 is supplied by the battery voltage (VBAT) and controls
the complete device. Therefore also VCL supplied parts are only usable in case of sufficient
VBAT supply voltage. The Control Unit has three main states called Off-Mode, Standby-
Mode, Transparent-Mode and LF Transmission Mode and several intermediate states (see
Figure 13). Interactions between the states are explained below in detail with extracted Fig-
ures.
26
Figure 13: Overall State Diagram of Control Unit
CLKI missed
WDEEN = LOW
for twdg
WDEEN = LOW
WDEEN
Off-Mode
= LOW
(Iquiet)
TX = HIGH and
CLKI CLKI =
WDEEN = HIGH
missed OFF
for
TX = LOW and twdg
TX= WAIT WDEEN = HIGH
HIGH TX=
LOW
TX = LOW Standby-
VRF < WDEEN
and Mode
VWAKEA = LOW
WDEEN VWAKEA=ON
=HIGH (Istby)
WDEEN
= LOW VRF>VWAKEA
for tWdly
(No_Wake Flag=0)
CLKI = ON
EOBI = ON
DEMOD = ON No modulation
Wait max. during tWAIT
for tWAIT
(Iact) tTELEGR
exceeded
CLKI missed CLKI missed
for twdg for twdg
1st. EOBI detected
EOBI = OFF,
Wait for
tTELEGR
No valid or complete
Receive (Iinit)
WAKE PATTERN
VRF>VWAKEA Wake Pattern during tWRX
for tWdly for max tWRX,
(No_Wake Flag=1) Check
Wake Pattern
(Iact)
WAKE PATTERN A WAKE PATTERN B
received received
(Passive Entry) (Passive Start)
VRF < VWAKEB
Transparent M.
WDEEN = Watchd. = OFF VWAKEB =
HIGH WAKE = High ON
EOBA = ON
CLKA = ON VRF > VWAKEB
(Iact)
WDEEN = LOW
TX =HIGH
Transmission
WDEEN Mode 3DSTAT1G.CH4
= HIGH CLKM=ON,
Start oscillation
27
2.8.1 Off Mode

The Control Unit is reset with low level at input WDEEN (see Figure 14).
No internal power-on-reset circuit is provided. The circuit is in Off Mode and consumes only
the quiescent current (Iquiet). All battery powered analog parts and current sources are
switched off.
A charge-up of the Charge Capacitor CL is still possible, because the constant current source
required for Voltage Regulator is supplied by VCL. Because of this behavior the battery can
be charged in Battery Charge Mode even if WDEEN is off.
Figure 14: Initialization State Diagram of TMS37122
WDEEN
OFF MODE
= LOW
(Iquiet)
WDEEN=HIGH WDEEN=LOW
and
TX = LOW
VRF < STANDBY

VWAKEA VWAKEA=ON
(Istby)
3DSTAT2.CH4
2.8.2 Standby Mode

The Control Unit includes a Configuration Memory (EEPROM), which can be programmed
via the Test/Trimming Interface. The Configuration Memory determines different modes and
timings. The configuration Memory is read when WDEEN (or WDEENIx) is set to high lev-
el. After the readout the circuit is in the Standby Mode and consumes the Standby Current
(Istby). In this state the unit remains as long as the RF amplitudes of all activated resonant
circuits are below the threshold level VWAKEA.
2.8.3 Init Mode

If a carrier is present and the amplitude at one of the three antennas exceeds the WAKE Sen-
sitivity Level A (WAKESensA1/2/3) for about 1 ms, the EOBI detector is activated.
As soon as the RF Amplitude of one resonant circuit increases, the AGC Amplifier starts to
regulate. After the run-in time (tPdly) the amplitude is checked. If the amplitude exceeds the
threshold level VWAKEA, and the regenerated clock (CLKI) is stable for twait and has no
significant interruptions (>2 clocks), the internal wake signal (WAKEI1, WAKEI2 or
WAKEI3) of the related channel is set (see Figure 15). Until this occurs the current increases
(Iinit) due to clock activity of three channels.
2.8.4 Active Mode

After detection of the first WAKEI the Control Unit disables the other activated Wake Detec-
tors in order to minimize the power consumption.CLKI and EOBI are selected accordingly.
28
The supply current decreases because only one Wake Detector remains active (Iact).
Figure 15: Control Unit Timing Diagram
tWAKE
RFreader
VWAKE
RFtrp
WDEEN
tPdly
WAKE_I tWdly
EOBI
CLKI
WAKE
EOBA
CLKA/M
IBAT Iquiet Istby Iinit Iact Iquiet Istby
3DTIM00A.CH4
2.8.4.1 Wake Pattern Detection

If the Wake Pattern Detection function is activated, the following 17 EOBI signals are inter-
preted as Pulse Position Modulation (PPM) telegram.
If no EOBI signal is detected within a via Off-Mode Memory defined time (twait), the Con-
trol Unit returns to the Standby Mode (via Off-Mode) again (see Figure 16). This is achieved
by switching off the CLKI so that the Standby Mode is entered after t = twait + twdg due to
Watchdog function. During twdg the current consumption is reduced significantly.
With the first detected EOBI signal the circuit enters the Wake Pattern receive loop. The com-
plete Wake Pattern must be received in a predetermined time (twrx) to be accepted. This time
is not configurable.
If no valid or complete Wake Pattern is detected during twrx, a waiting loop is entered. In this
loop the circuit remains for an expected time a foreign Identification Device needs to com-
plete its telegram transmission (ttelegr). Then the Standby Mode is entered via Watchdog.
Any CLKI interruption longer than twdg causes the circuit to return to Standby Mode (via
Off-Mode) and resetting the complete sequence control. Also the Configuration Memory
contents are reloaded to the relating locations.
After receipt of a complete 16-bit Pattern, the PPM Demodulator checks if the Passive Entry
29
or Passive Start Wake Pattern is received.
Figure 16: Wake Pattern Detection State Diagram
CLKI missed
for twdg
WDEEN
Off-Mode
= LOW
(Iquiet)
CLKI CLKI =
missed OFF
for
TX = LOW and twdg
WDEEN = HIGH
Standby-
VRF < WDEEN
Mode
VWAKEA = LOW
VWAKEA=ON
(Istby)
VRF>VWAKEA
for tWdly
(No_Wake Flag=0)
CLKI = ON
EOBI = ON
DEMOD = ON No modulation
Wait max. during tWAIT
for tWAIT
(Iact) tTELEGR
exceeded
CLKI missed CLKI missed
for twdg for twdg
1st. EOBI detected
EOBI = OFF,
Wait for
tTELEGR
No valid or complete
Receive (Iinit)
WAKE PATTERN
Wake Pattern during tWRX
for max tWRX,
Check
Wake Pattern
(Iact) 3DSTAT3A1.CW
2.8.4.2 Transparent Mode
If the Wake Pattern A (Passive Entry) is detected, the circuit switches to Transparent Mode
(see Figure 16). In Transparent Mode the WAKE output is set, the internal signals CLKI and
EOBI are now available at the relating outputs (CLKA/M, EOBA). The watchdog for CLKI
is disabled, which means that the external Microcomputer has to take over the supervision and
30
demodulation function.
If the Wake Pattern B (Passive Start) is detected, the circuit first checks, if the RF Amplitude
is above the threshold VWAKEB. VWAKEB is typically configured higher than VWAKEA
so that an Identification Device outside the car will not reach this RF level. It will enter the
Telegram Waiting loop (tTelegr) and then return to Standby Mode (see Figure 17).
An Identification Device inside the car will reach a higher level than VWAKEB and will
switch to Transparent Mode.
If the Wake Pattern Detection is disabled via Configuration Memory, the Transparent Mode
is entered directly from Standby Mode if VWAKEA is exceeded.
The Transparent Mode can only be left by resetting the circuit (WDEEN=low).
Figure 17: State Diagram of Transparent Mode
WDEEN
OFF = LOW
(Iquiet)
CLKI = tTELEGR
OFF exceeded
CLKI
missed
for
EOBI = OFF,
twdg
Wait for
WDEEN = LOW No valid or complete tTELEGR
Receive WAKE PATTERN (Iinit)
Wake Pattern during tWRX
for max tWRX,
Check
Wake Pattern
(Iact)
WAKE PATTERN A WAKE PATTERN B
received received
(Passive Entry) (Passive Start)
VRF < VWAKEB
Wdg. = OFF
WDEEN = WAKE = High VWAKEB =
HIGH EOBA = ON ON
CLKA = ON
(Iact) VRF > VWAKEB
3DSTAT4.CH4
2.9 FSK Modulator

If enough voltage is available in the Charge Capacitor CL, the FSK Modulator of the Antenna
1 LF channel can be used by the Microcomputer (LF Transmission Mode). This is the case in
the Backup Mode (Battery Backup Mode). Instead of transmitting the response via UHF
Channel the Microcomputer activates the TX input of the TMS37122 after reaching the
Transparent Mode (see Figure 18). This causes the Continuous Pluck Circuit of the device to
activate the oscillation at Resonant Circuit 1. The resulting clock from the VCL supplied
Clock Regenerator is divided by sixteen (CLKM) and output at CLKA/M. In order to achieve
a clock synchronous operation, the modulation data must be supplied at MOD input with neg-
ative transition of the CLKM signal. Internally the MOD signal is then synchronized with the
CLKA/M positive transition before switching on or off the Modulation Capacitor (CM).
31
The LF Transmission Mode can also be entered directly from the OFF Mode. For this purpose
the TX input must be set to high before the WDEEN is set. Releasing TX while WDEEN =
high will switch to Transparent Mode. Next activation of TX activates the FSK Modulator.
Figure 18: State Diagram of LF Transmission Mode
WDEEN = LOW
WDEEN
WDEEN = LOW OFF = LOW
TX = HIGH and (Iquiet)
WDEEN = HIGH
TX= WAIT
HIGH TX=
LOW
WDEEN
= LOW
TX = LOW
and
WDEEN
=HIGH
Wdg. = OFF
WDEEN = WAKE = High
HIGH EOBA = ON
CLKA = ON
(Iact)
TX =HIGH
CLKM=ON, 3DSTAT5.CH4
WDEEN
= HIGH Start Oscillation
2.10 Configuration Memory

2.10.1 Memory Organisation
The TMS37122 EEPROM Configuration Memory is organized by 3 rows and 5 nibbles. Each
nibble has 4 bits (see Figure 19). The Configuration Memory can be programmed and read
via Test/Trimming Interface. Programming and reading must be done nibble by nibble using
test mode PTx04 and PTx07.
32
Figure 19: Memory Organisation
NIBBLE
4 3 2 1 0
Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0
NO NO NO NO
CLKA WDE3 WDE2 WAKE
PPM THRESHOLD VWAKE B/ 2/3 VWAKE B/ 1 VWAKE A/ 1 0
C_TELEGR PASSIVE ENTRY WAKE PATTERN 1 ROW
C_WAIT PASSIVE START WAKE PATTERN 2
Bit 3 Bit 0 Bit 15 Bit 0
3DMEMD3.DRW
2.10.2 Default Memory Content

The TMS37122 is delivered with the following Default Memory Content (see Table 2 and Figure 20):
Table 2 Default Function Configuration
Value
Memory Cell Note
[hex]
VWAKEA/1 F Maximum Sensitivity
VWAKEB/1 F Maximum Sensitivity
VWAKEB/2/3 F Maximum Sensitivity
cHdet = 56, tHdet = 417 µs

PPM Threshold 7
(fTX=134.2kHz)
Wake Pattern Detection is

NO_WAKE0 1
deactivated
NO_WDE2 0 Wake Detector 2 is activated
NO_WDE3 0 Wake Detector 3 is activated
NO_CLKA 0 CLKA output is activated
PE WAKE PATTERN 0000 Passive Entry Wake Pattern is '0'
PS WAKE PATTERN 0000 Passive Start Wake Pattern is '0'
C_TELEGR 0 cTelegr = 0, tTelegr = 30.5 ms
C_WAIT 0 cwait = 0, twait = 7.6 ms
33
Figure 20: Default Memory Content

NIBBLE
4 3 2 1 0
Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0
NO NO NO NO
CLKA WDE3 WDE2 WAKE
PPM THRESHOLD VWAKE B/ 2/3 VWAKE B/ 1 VWAKE A/ 1
0
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C_TELEGR PASSIVE ENTRY WAKE PATTERN
1 ROW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C_WAIT PASSIVE START WAKE PATTERN
2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 3 Bit 0 Bit 15 Bit 0
3DMEMD4.DRW
The default PPM Threshold is configured for a medium data rate of 2kBit/s, realized for ex-
ample with a low bit period of tbitL=400 and a high bit period of tbitH=600µs (see Figure
12). It is assumed that toff is as short as possible (toff<=100µs), but still achieving 50% mod-
ulation (m=33%) under all conditions. Under this assumptions CLKA is available continu-
ously or interrupted only shortly during toff. If this cannot be achieved due to lower quality
factors and thereore stronger damping, or if higher data rates are demanded, PPM Threshold
must be adapted.
34
2.10.3 Configuration Options

2.10.3.1 Wake Sensitivity VWAKEA/1
A three-dimensional antenna arrangement typically consists of 2 ferrite antennas, positioned
in an angle of 90 degree and an air coil antenna. Preferably the air coil antenna is connected
to RF1 because for key fob and card applications this antenna has the optimum orientation
with respect to the Base Station antennas. In order to match the sensitivity of the air coil an-
tenna to the sensitivity to the equal ferrite antennas the sensitivity RF1 can be reduced (see
Table 3 and Figure 21).
Table 3: Wake Sensitivity VWAKEA/1 Options
Wake Sensitivity
VWAKEA/1 min VWAKEA/1 VWAKEA/1 max

DEC MSB LSB
[mVpp] nom [mVpp] [mVpp]
15 2 5 10 1 1 1 1
14 2.5 7 13.2 1 1 1 0
13 3.0 9.0 16.4 1 1 0 1
12 3.5 11 19.6 1 1 0 0
11 4.0 13.0 22.8 1 0 1 1
10 4.5 15.0 26.0 1 0 1 0
9 5.0 17.0 29.2 1 0 0 1
8 5.5 19.0 32.4 1 0 0 0
7 6.0 21.0 35.6 0 1 1 1
6 6.5 23.0 38.8 0 1 1 0
5 7.0 25.0 42.0 0 1 0 1
4 7.5 27.0 45.2 0 1 0 0
3 8.0 29.0 48.4 0 0 1 1
2 8.5 31.0 51.6 0 0 1 0
1 9.0 33.0 54.8 0 0 0 1
0 9.5 35.0 58 0 0 0 0
35
Figure 21:VWAKEA Sensitivity Diagram

60
50
40
SENSITIVITY [mVpp]
SPECmin
30 SPECnom
SPECmax
20
10
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONFIGURATION
2.10.3.2 Passive Start Sensitivity VWAKEB/1/2/3
If the system includes Passive Start function, it can be helpful to implement an indoor/outdoor
detection to avoid erroneous start of the engine by inside person in case Identification Device
is outside. For this purpose the Passive Start Wake Pattern is set to a different value than the
Passive Entry Wake Pattern. When the Passive Start Wake Pattern is received, the Identifica-
tion Device checks if the amplitude of the oscillation is above Passive Start Sensitivity
VWAKEB/1 (VWAKEB/2/3). Only if this lower threshold is exceeded, the 3D-AFE enters
the Transparent Mode and the engine can be started, because the Microcomputer can return
the correct response.
The sensitivity level for Passive Start can be adjusted depending on the system behavior. The
field strength generated outside the car by an internal Passive Start Base Station (for example:
in dashboard) must be unable under all circumstances to induce a voltage higher than the Sen-
sitivity B (see Figure 22). The threshold voltage is therefore selectable for Antenna 1 sepa-
rately by VWAKEB/1 (see Table 4 and Figure 23). For Antenna 2 and 3, which are typically
equal, a common threshold level (VWAKEB/2/3) is configurable. The range and resolution
is equal to VWAKEB/1.
36
Figure 22: System Schematic for Indoor/Outdoor Detection
Passive Start Sensitivity

(VWAKEB1, VWAKEB2/3)
PE Wake Pattern
Passive Entry Sensitivity
(VWAKEA/1, VWAKEA/2/3)
PS Wake Pattern
3DPSAP1.DRW
Table 4: Passive Start Sensitivity Options
Passive Start Sensitivity
VWAKEB/1/2/3 VWAKEB/1/2/3 VWAKEB/1/2/3

DEC MSB LSB
min [mVpp] nom [mVpp] max [mVpp]
15 2 5 10 1 1 1 1
14 8.0 16.0 27.5 1 1 1 0
13 14.0 27.0 45.0 1 1 0 1
12 20.0 38.0 62.5 1 1 0 0
11 26.0 49.0 80.0 1 0 1 1
10 32.0 60.0 97.5 1 0 1 0
9 38.0 71.0 115.0 1 0 0 1
8 44.0 82.0 132.5 1 0 0 0
7 50.0 93.0 150.0 0 1 1 1
6 56.0 104.0 167.5 0 1 1 0
5 62.0 115.0 185.0 0 1 0 1
4 68.0 126.0 208.0 0 1 0 0
3 74.0 137.0 220.0 0 0 1 1
2 80.0 148.0 237.5 0 0 1 0
1 86.0 159.0 255.0 0 0 0 1
0 92.0 170.0 272.5 0 0 0 0
37
Figure 23: VWAKEB SENSITIVITY Diagram

300
250
200
SENSITIVITY [mVpp]
SPECmin
150 SPECnom
SPECmax
100
50
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONFIGURATION
2.10.3.3 Pulse Position Demodulator Threshold

Four bits are provided defining the Pulse Position Demodulation Threshold Count (cHdet) for decoding the
PPM Wake Pattern. The resulting Threshold Time (tHdet) depends on the used system frequency:
tHdet = cHdet / fTXThe numbers in below table are given for the nominal TIRIS System Frequency
(fTX=134.2 kHz),the default cHdet is 56:
38
Table 5: Counter Definition for Pulse Position Demodulation
Pulse Position Modulation PPM Threshold
DEC Chdet Thdet Nom.[µs] MSB LSB
0 - - 0 0 0 0
1 8 59 0 0 0 1
2 16 119 0 0 1 0
3 24 179 0 0 1 1
4 32 238 0 1 0 0
5 40 298 0 1 0 1
6 48 358 0 1 1 0
7 56 417 0 1 1 1
8 64 477 1 0 0 0
9 72 537 1 0 0 1
10 80 596 1 0 1 0
11 88 656 1 0 1 1
12 96 715 1 1 0 0
13 104 775 1 1 0 1
14 112 112 1 1 1 0
15 120 894 1 1 1 1
2.10.3.4 Wake Pattern Detection Flag 'NO_WAKE'

If the NO_WAKE flag is set no Wake Pattern check is performed and the Control Unit
switches directly to Transparent Mode if VWAKE-A threshold is exceeded.
2.10.3.5 Write Distance Expander 2 Flag 'NO_WDE2'

If the NO_WDE2 flag is set the Wake Detector of RF2 input is completely disabled. The RF2
input should be connected to VCL externally in this case. Standby current consumption is re-
duced due to this.
2.10.3.6 Write Distance Expander 3 Flag 'NO_WDE3'

If the NO_WDE3 flag is set the Wake Detector of RF3 input is completely disabled. In this
case the RF3 input should be connected to VCL externally. Standby current consumption is
reduced due to this.
2.10.3.7 CLKA Output Disable Flag ‘NO_CLKA’
If the NO_CLKA flag is set, the CLKA/M output does not provide a clock when WAKE is
activated. This prevents back coupling of interference to the sensitive RF inputs due to not
optimized PCB layout.
The option can be used at identification devices, which do not require the CLKA. This is the
case, if the microcomputer is able to measure period duration or if the data (EOBA) includes
39
the clock information (e.g. Manchester Coding). During Transmission Mode (TX=high) the
clock CLKM is available even if CLKA is disabled.
2.10.3.8 Passive Entry Wake Pattern
The desired Wake Pattern for the Passive Entry function can be selected as desired. If a sep-
arate transponder for Immobilizer function is in the system, pattern should be avoided, which
are similar to a Challenge telegram. This especially if the Base Station uses same modulation
principle for data transfer to the transponder.
2.10.3.9 Passive Start Wake Pattern
The Wake Pattern for the Passive Start function can be selected as required. If a separate tran-
sponder for Immobilizer function is in the system, patterns which are similar to a Challenge
telegram should be avoided. Especially if the Base Station uses same modulation principle
for data transfer to the transponder.
Attention:
If Passive Start Wake Pattern and Passive Entry Wake Pattern are equal, only
the Passive Start Sensitivity determines if the Transparent Mode is entered.
2.10.3.10Telegram Duration 'C_TELEGR'
If the Wake Pattern check detected a non-valid or incomplete Wake Pattern it can be assumed
that a foreign Base Station had requested communication from a foreign Identification De-
vice. To avoid ongoing wake-up of the non-addressed Identification Device a waiting period
is meaningful. Therefore a counter is loaded with ctelegr. The counter counts down using
CLKI as source. The resulting waiting time must be adapted to typical communication dura-
tion after a wake signal (see Table 6). The communication duration consists of the Challenge
Telegram and the UHF Response Telegram, which are together typically in the range of 100
ms. The telegram time is calculated with the following formula:
ttelegr = ctelegr / fTX
40
Table 6: Counter Definition for Pulse Position Demodulation
Telegram Duration
ttelegr
DEC ctelegr MSB LSB
nom.[ms]
0 4096 30.5 0 0 0 0
1 8192 61.0 0 0 0 1
2 12288 91.6 0 0 1 0
3 16384 122.1 0 0 1 1
4 20480 152.6 0 1 0 0
5 24576 183.1 0 1 0 1
6 28672 213.7 0 1 1 0
7 32768 244.2 0 1 1 1
8 36864 274.7 1 0 0 0
9 40960 305.2 1 0 0 1
10 45056 335.7 1 0 1 0
11 49152 366.3 1 0 1 1
12 53248 396.8 1 1 0 0
13 57344 427.3 1 1 0 1
14 61440 457.8 1 1 1 0
15 65536 488.4 1 1 1 1
2.10.3.11Wake Pattern Waiting Time 'C_WAIT'
If the Wake Pattern check detected no modulation after internal wake-up, it can be assumed
that noise was the reason for activation. A initialization and return to the Standby Mode after
a reasonable waiting time is meaningful. Therefore a counter is loaded with cwait. The
counter counts down using CLKI as source. The resulting waiting time must be adapted to
the Wake-up Times (tWAKE) used in the system. Typically the Wake-up Time is shorter than
10ms. In best case the Identification Device internally wakes up 3 ms after beginning of wake
period. So the Control Unit has to wait at least 7 ms until begin of modulation (see Table 7).
If the Battery Backup function is used, longer Wake-up times will be used. Assuming that
reaction times of more than 200 ms will not be acceptable by the system user and the mini-
mum communication time is 50 ms, the maximum Wake-up Time will be around 150 ms. Be-
cause of the exponential rise behavior, the charge voltage VCL will reach 63% of the
maximum voltage (~3 V) after 30 ms. At this time enough voltage is available at VCCO to
initialize the Microcomputer (~2.5 V). Because the initialization will need some time
WDEEN will not be set before the 30 ms are gone and the Wake Pattern will be received latest
120 ms after start of Wake-up Time.
The Wake Pattern Waiting Time is calculated with the following formula:
twait = cwait / fTX
41
Table 7: Wake Pattern Waiting Time Options
Wake Pattern Waiting Time
DEC cwait ttwait nom.[ms] MSB LSB
0 1024 7.6 0 0 0 0
1 2048 15.3 0 0 0 1
2 3072 22.9 0 0 1 0
3 4096 30.5 0 0 1 1
4 5120 38.2 0 1 0 0
5 6144 45.8 0 1 0 1
6 7168 53.4 0 1 1 0
7 8192 61.0 0 1 1 1
8 9216 68.7 1 0 0 0
9 10240 76.3 1 0 0 1
10 11264 83.9 1 0 1 0
11 12288 91.6 1 0 1 1
12 13312 99.2 1 1 0 0
13 14336 106.8 1 1 0 1
14 15360 114.5 1 1 1 0
15 16384 122.1 1 1 1 1
2.10.4 Memory Programming

For Programming Test Mode PTx04, TDAT, TCLK and TEN must be connected to a Tester
Unit (see Figure 8). The circuit must be supplied by VBAT and must be activated (Standby
Mode) during all test functions (WDEEN=high).
The Test Mode is addressed by shifting in the 6-bit test number (04hex) using TDAT and
TCLK input (see Figure 24). All data must be supplied with LSB first and the High state at
every input must have VBAT level. TDAT condition should be changed at the negative tran-
sition of TCLK. The data are shifted in with positive transition. After the Data to be pro-
grammed the Row and Nibble information is shifted. Row and Nibble address is binary
coded. After that 16 clocks must be supplied while TEN is high in order to clock the internal
Control Unit. Then the level at TEN can be increased to VPP level and programming is exe-
cuted. Rise and fall time of VPP must be observed.
With deactivation of TEN the circuit resets automatically and is ready for next test command.
VBAT and/or WDEEN must not be initialized.
42
Figure 24: Timing Diagram for Test Mode PTx04
VBAT
WDEEN
TEST MODE
PTx04
TDAT DATA ROW NIBBLE
LSB LSB LSB LSB
TCLK
1 2 3 4 5 6 1 2 3 4 1 2 3 4 1 2 3 1 16
VPP
TEN VBAT
trVPP
tPRG
tfVPP
3DTMOD4A.DRW
2.10.5 Memory Read

The result of programming function is checked with Read Test Mode PTx07 (see Figure 25).
After shifting in the Test Mode (07hex), the Row and Nibble address, the Tester Unit con-
nected to TDAT must be switched to input. Fifteen TCLK pulses are needed to clock the IC
Control Unit. After nine TCLK pulses the first data bit is already available at output TDAT.
Then additional five clocks are required for the Control Unit. With the negative transition of
the next TCLK, the Tester Unit must store the first data bit. The next three data bits are shifted
with the positive transition of TCLK and should be stored by the Tester Unit at the negative
transitions.
Low at TEN resets the test circuit and TDAT becomes input again.
43
VBAT
WDEEN
TEST MODE
PTx07 DATA OUT
TDAT ROW NIBBLE undefined BIT 1 BIT 2-4

LSB LSB LSB
TCLK
1 2 3 4 5 6 1 2 3 4 1 2 3 1 91 5 1 2 3 4
TEN VBAT
3DTMOD7.DRW
2.11 Resonant Circuit Trimming

The three Resonant Circuits (LR,CR) connected between VCL and the inputs RF1, RF2 and
RF3 need to be trimmed to the optimal system frequency (fTX) in case the tolerances of the
inductance and the external capacitor are too high. Especially for the Battery Backup and
Charge Function an accurate trimming is important because of the energy transfer to the
charge capacitor CL is better.
Each RF-input has a certain input capacitance CIN with respect to GND, which must be taken
into consideration during definition of the resonant circuit components. This capacitor de-
creases with increasing VCL (CRF1, CRF2, CRF3).
As well as this, an 8-bit capacitor array is provided at each RF-input. The Trimming Capac-
itors are activated or deactivated by means of 8-bit EEPROM cells. Per default all capacitors
are programmed off. The external components are selected in a way that the resonant circuit
frequency range resulting from the parameter variations without Trimming Capacitors (but
with Input Capacitance) is below the desired frequency. By switching (programming) on the
binary weighted capacitors the resonant circuit range can be shifted up to achieve symmetri-
cal distribution around the system frequency.
In case the LF Transmission function is used, also the non-configurable Modulation Capaci-
tor (CM) must be taken into consideration when the resonant circuit components are defined.
The resulting frequency hub is depending on the used components and must be adapted to the
Base Station Requirements.
The system manufacturer has to trim the Identification Device after assembly using the Trim/
Test Interface. The following Test Modes are provided:
- PTx14 Programming of Antenna 1 trim byte (on and off)
44
- PTx16 H-Bit frequency of Antenna 1 without plucking

- PTx18 L-Bit frequency of Antenna 1 without plucking
2.11.1 Resonance Frequency Measurement

The first action in the trimming process is a measurement of the base resonant circuit frequen-
cy. For an optimum energy transfer the trimming should be done for a VCL of 4V, because
this voltage is necessary for a LF Response but is still below the limitation voltage. Therefore
VCL is supplied externally via the Test Interface (see Figure 8). During this test VCL and
VBM must be equal (VCL, VBAT = 4V).
After test number (18hex, 28hex, 38hex) is shifted into the IC (see Figure 24), the next clock
signal at TCLK triggers an oscillation at the addressed resonant circuit (RF1, RF2, RF3). The
TCLK signals should be short (tpluck), because during this time th RF pin is short circuit to
ground and a high current will flow from VCL via the coil.
This trigger action is further called 'pluck', because the action can be compared with the
plucking of a spring, which is fasten at one side (VCL) and pulled down to ground.
Important Note:
Do not measure at the RF pins during trimming process, because the capaci-
tance load will falsify the result. The same is the case if metal is near by the
antennas.
The oscillation fades away depending on the resonant circuit quality factor. Because the
TMS37122 uses a separate Clock Regenerator for this test, a clock will appear at TDAT im-
mediately if oscillation starts. Preferable at least the duration of 10 cycles should be mea-
sured. Then period duration of a single cycle can be calculated, which represents the
resonance frequency.
In case an additional period duration measurement is desired, the oscillation can be enhanced
once more with a further TCLK signal, after measurement is completed.
The measurement will be finished switching off TEN and VCL.
45
Figure 26Timing Diagram for Test Mode PTx18
VBAT
WDEEN
VCL PERIOD DURATION

MEASUREMENT
>/= 10 PULSES
TEST MODE
PTx18
TDAT
LSB
1
TCLK
1 2 3 4 5 6
TEN VBAT
RFx
3DTMD18B.DRW
46
2.11.2 Trimming EEPROM Programming

Using the known typical parameters of the external components, IC input capacitance (CRF1,
CRF2, CRF3) and the result from first resonance frequency measurement a necessary parallel
capacitor can be calculated. From this it can be determined which internal trimming capaci-
tors must be switched on.
After clocking in the test number of the relating trimming circuit (PTx14, PTx24, PTx34), the
8-bit Trimming Byte is shifted (see Figure 27). LSB is shifted first, which represents the
smallest capacitor (CT1). A low bit switches off and a high bit switches on a capacitor. The
programming mode is entered with TEN = high. Programming starts when TEN is ramped-
up to VPP level. The test mode is left with TEN=low.
Result of programming process should be checked by an additional Resonance Frequency

Measurement and Trimming EEPROM Programming should be repeated if necessary.
VBAT
WDEEN
TEST MODE
PTx14
TDAT TRIMMING BYTE
LSB LSB
TCLK
1 2 3 4 5 6 1 2 3 4 5 6 7 8
VPP
TEN VBAT
trVPP
tPRG
tfVPP
3DTMOD14.DRW
2.11.3 Modulation Frequency Check

During LF Transmission Mode a Frequency Shift Keying signal is transmitted. The Reso-
nance Frequency of the trimmed Resonant Circuit is the representation of a Low Bit (fL). The
High Bit is represented by the lower High Bit Frequency (fH), achieved by switching on the
Modulation Capacitor (CM). For checking this frequency Test Mode PTx16 is provided.
The test flow is according to Figure 24 with the exception that test number is 16hex.
47
Chapter 3: Application
This chapter describes the various functions of the integrated circuit and how they can be used
in actual applications.
Topic Page
3.1 Passive Entry Function ...........................................................................49
3.2 Passive Start Function ............................................................................52
3.3 Battery Backup Function ........................................................................54
3.4 Immobilizer Function...............................................................................56
3.5 Anti-Collision Function ...........................................................................56
48
CHAPTER 3
Application
3.1 Passive Entry Function

The standard application of 3D-AFE is the Passive (Keyless) Entry function. The car driver
approaches the car and triggers the Base Station by pulling the door handle or by another trig-
ger mechanism. The Base Station transmits the Passive Entry (PE) Wake Pattern, a Command
and a Challenge using typically an outdoor Antenna, for example in the outside mirror. The
Antenna is driven by a LF Transceiver, which is typically activated with an active low signal
called TXCT- (see Figure 28).
It is assumed that the Identification Device is in Standby Mode (WDEEN=high). During

Wake-up Time the IC internal wake (WAKEI) will be activated if the threshold VWAKEA
is exceeded at one or more antennas. The first WAKEI signal determines the receive channel.
During the Waiting Time the Base Station will start modulation while sending the Passive En-
try Wake Pattern. The internal clock CLKI will be active during this period.
If the received PE Wake Pattern is equal to the PE Wake Pattern in the EEPROM, the RF level
check with VWAKEB will NOT be performed and the 3D-AFE will activate the output
WAKE at once. This will cause the Microcomputer of the Identification Device to wake-up
after an eventually µC Wake Delay. Depending on the required time the Base Station should
insert an active period between Wake Pattern and Command transmission. The digitized am-
plitude modulation is output at the EOBA and demodulation is done by the Microcomputer.
For this purpose the CLKA signal can be used as reference, which is available at output
EOBA/M.
The Command sent to the Microcomputer must include an information that a Passive Entry
action is requested.
49
Figure 28: Passive Entry Wake Pattern Detection

BASE
WAKE-UP PASSIVE ENTRY WAKE PATTERN COMMAND + CHALLENGE
STATION off
TXCT- TIME DATA
on
ID 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
DEVICE
WDEEN
WAKEI VWAKEA.
µC
tWAIT WAKE
DELAY
EOBI
CLKI
DATI
PE 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
PATTERN
PS
PATTERN
WAKE.
COMMAND + CHALLENGE.
EOBA. DATA
CLKA/M
3DATIM01.DRW
After checking the Command the Microcomputer knows that a Passive Entry function is re-
quested (see Figure 29). The Challenge will be encrypted (ENCR), respectively the Rolling
Code will be determined depending on the system. Then the Microcomputer waits for the next
EOBA signal created by the Base Station, switching off the Transmitter. When this has hap-
pened, the UHF Transmitter is activated and the Response Telegram is sent to the Base Sta-
tion. There the Response is checked and the door is opened if valid.
The Microcomputer initializes the 3D-AFE after transmission of the Response with a short
negative pulse at WDEEN. The circuit returns to Standby Mode and is ready for next cycle.
50
August ’01 Chapter 3. Application
Figure 29: Passive Entry Challenge/Response Timing

PE COMMAND
INIT
+ ENCR
WAKE WAKE PATTERN MC
CHALLENGE
BASE off
STATION
TXCT-
on
0 1 0 0
ID
DEVICE
WDEEN.
VCL.
WAKEI.
WAKE.
EOBA.
0 1 0 0
CLKA/M
TX
MOD
UHF RESPONSE
TX
3DTIM02A.CH4
51
3.2 Passive Start Function

A further application of 3D-AFE is the Passive Start function. The car driver is already seated
in the car and triggers the Base Station by pushing a button at the dashboard or at the middle
console. The Base Station transmits now the Passive Start (PS) Wake Pattern, a Command
and a Challenge using an indoor Antenna, located for example in the dashboard, seat or door.
The Antenna is driven by a LF Transceiver, which is typically activated with an active low
signal called TXCT- (see Figure 30).
It is assumed that the Identification Device is in Standby Mode (WDEEN=high). During

Wake-up Time the IC internal wake (WAKEI) will be activated if the threshold VWAKEA
is exceeded at one or more antennas. The first WAKEI signal determines the receive channel.
During the Waiting Time (twait) the Base Station will start modulation while sending the PS
Wake Pattern. The internal clock CLKI will be active during this period.
If the received PS Wake Pattern is equal to the PS Wake Pattern in the EEPROM, the RF level
check with VWAKEB will be performed (sensitivity stays at VWAKEA level). If the level is
higher than VWAKEB, the output WAKE is set. This will cause the Microcomputer of the
Identification Device to wake-up after an eventually µC Wake Delay. Depending on the re-
quired time, the Base Station should insert an active period between Wake Pattern and Com-
mand transmission.
The digitized amplitude modulation is output at the EOBA and demodulation is done by the
Microcomputer. For this purpose the CLKA signal can be used as reference, which is avail-
able at output EOBA/M.
The Command sent to the Microcomputer must include an information that a Passive Start
action is requested.
After checking the Command, the Microcomputer knows that a Passive Start function is re-
quested. The Challenge will be encrypted (ENCR), respectively the Rolling Code will be de-
termined depending on the system. Then the Microcomputer waits for the next EOBA signal
created by the Base Station, switching off the Transmitter. When this has happened, the UHF
Transmitter is activated and the Response Telegram is sent to the Base Station. There the Re-
sponse is checked and the engine is started if valid.
The Microcomputer initializes the 3D-AFE after transmission of the Response with a short
negative pulse at WDEEN. The circuit returns to Standby Mode and is ready for next cycle.
52
Figure 30: Passive Start Wake Pattern Detection
BASE
WAKE-UP PASSIVE START WAKE PATTERN COMMAND + CHALLENGE
STATION off
TXCT- TIME DATA
on
ID 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
DEVICE
WDEEN
WAKEI VWAKEA. VWAKEB.

µC
tWAIT WAKE
DELAY
EOBI
CLKI
DATI
PE 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
PATTERN
PS
PATTERN
WAKE.
COMMAND + CHALLENGE.
EOBA. DATA
CLKA/M
3DBTIM01.DRW
53
3.3 Battery Backup Function

It is assumed that the system is configured to work with Battery Backup Supply (see Figure
7) that means VCCO is able to supply VBAT. Battery voltage is so low that the Supervisory
Circuit has reset the Microcomputer (see Figure 9). Due to this WDEEN is low and the whole
Identification Device consumes a low quiescent current.
The car driver tries to get into the car by pulling the door handle while the Identification De-
vice is still in far distance range of the Base Station Antenna. The Base Station sends out the
Passive Entry Wake Pattern, Passive Entry Command and the Challenge, but gets no Re-
sponse, because the Identification Device is off.
The Base Station controller in such a case will repeat the Challenge several times. Because it
takes into account that the battery of the Identification Device is empty, it increases the Wake-
up Time and sends out the PE Backup Command.
The car driver, who recognizes that the door does not open, brings the Identification Device
nearer to the back mirror, because he was advised to do by the car’s user manual. As a result
the charge capacitor in the Identification Device is charged up to a higher voltage (see Figure
31). Via the voltage regulator in the 3D-AFE, the supply voltage of Microcomputer and Front
End is increased. The Supervisory Circuit will detect sufficient voltage and will restart the
Microcomputer. After initialization the Microcomputer will enable the 3D-AFE and in trans-
parent mode the Backup Command and the Challenge will be received.
The Microcomputer now knows that the Response cannot be sent via UHF Channel, because
current consumption will be too high. Therefore it uses the LF Transmission Mode. By setting
TX to high with occurrence of last EOBA signal, an oscillation is started at Resonant Circuit
1. The Response is transmitted via LF channel using FSK controlled by MOD input. The data
to be transmitted are changed synchronous to the CLKM signal available at output CLKA/M.
Timing requirements and data formats of the TIRIS System and Transponders should be ob-
served [1].
The LF data are received by the Transceiver connected to the Mirror Antenna and checked
by the Base Station Controller.
After transmission of the whole Response the Microcomputer resets the TX input and initial-
izes the 3D-AFE using WDEEN.
54
Figure 31: Timing Diagram for Battery Backup Function
PE/ PS BACKUP
INIT COMMAND
+ ENCR
WAKE WAKE PATTERN MC
CHALLENGE
BASE off
STATION
TXCT-
on
0 1 0 0
ID
DEVICE
VCL
VBAT
RESET
WDEEN.
WAKE.
EOBA
0 1 0 0
CLKA/M
TX
MOD
UHF
TX
RF1
3DTIM03A.DRW
55
3.4 Immobilizer Function

The current Immobilizer function could be desired additional (backup) or instead of Passive
Start function. In this case the 3D-AFE together with a Microcomputer could even replace a
TIRIS Transponder because compatibility can be achieved.
The car driver has to place in this case the Identification Device near a car-internal LF Trans-
ceiver Antenna. This can for example be the traditional Keylock Reader Antenna or another
reader in the dashboard.
The car driver is triggering the immobilization process using a push button or a mechanical
key. This causes the Transceiver to send out a charge burst (typical 50 ms). The field strength
and coupling between Transceiver and Identification Device should be high enough that the
charge capacitor is charged to maximum.
For full compatibility it is assumed that the Wake Pattern detection of 3D-AFE is disabled.
Due to this the 3D-AFE enters at once the Transparent Mode and the Microcomputer inter-
prets the Commands and Data eventually sent after the charge. If enough supply voltage is
available because of intact battery or charge voltage (battery backup), a Response can be pre-
pared and sent back using the procedure described in previous section (see Figure 31).
3.5 Anti-Collision Function

If more than one Identification Device is in the field during a Passive Entry or Passive Start
function, the simultaneous UHF Responses initiated by a Challenge, might interfere each oth-
er. A solution to this problem is described in a TIRIS Patent [2], which is allowed to use in
conjunction with the TMS37122.
The Identification Device Microcomputer must have stored for this purpose in its memory a
'Key Number' and eventually a 'Car Number'. The Wake Pattern also fulfils the task of a 'Car
Number'. Let us suppose that the system is designed for maximum four Identification Devices
per car. These four devices have the same 'Car Number' but different 'Key Numbers' (for ex-
ample: 1, 2, 3,4).
Interference by foreign Identification Devices can be easily avoided by sending the 'Car
Number' (Wake Pattern) together with Command and Challenge. The Identification Device
will only respond if the 'Car Number' (Wake Pattern) matches.
To avoid collision of the four valid Identification Devices the following procedure must be
implemented in the software:
Whenever the 3D-AFE is initialized (WDEEN = high) a software counter is set to zero. After
receipt and Encryption of a Challenge the next EOBA signal is awaited. Instead of transmit-
ting at once the Response the software increment with this signal the counter and compares
the content with the 'Key Number' in the memory.
Only if equal the Response is performed. Otherwise next EOBA is awaited. So the four de-
vices will respond in separate time windows (see Figure 32).
After the counter has reached the maximum key number, the 3D-AFE is re-initialized.
If the Identification Device does not manage to count to the maximum number within the du-
ration of three responses, the circuit is also reset.
56
Figure 32: Timing Diagram of Anti-Collision Function

COMMAND
+
BASE INIT (CAR NUMBER)
+ ENCR REQUEST RESPONSE
STATION WAKE WAKE PATTERN MC
off CHALLENGE 1 2 3 4
TXCT-
on
0 1 0 0
ID
DEVICE
WDEEN
VCL.
WAKE.
EOBA.
0 1 0 0
CLKA/M
TX
MOD
UHF
TX
3DTIM06A.CH4
57
Chapter 4: Product Specification Data

This chapter describes all of the product specifications that you need to know in order to in-
tegrate the device into your system.
Topic Page
4.1 Absolute Maximum Ratings....................................................................59
4.2 Recommended System Operating Conditions......................................60
4.2.1 Base Station - Test Station Conditions ................................................60
4.2.2 Identification Device Conditions ...........................................................60
4.2.3 Recommended Operating Conditions for IC ........................................61
4.2.3.1 Identification Device Antennas ...................................................61
4.2.3.2 Resonant Circuit Capacitor.........................................................61
4.2.3.3 Charge Capacitor........................................................................61
4.2.3.4 IC ................................................................................................62
4.2.4 IC Characteristics over Operating Free-air Temperature Range .........63
4.2.4.1 General IC Characteristics..........................................................63
4.2.4.2 Input Capacitances .....................................................................63
4.2.4.3 Modulation Capacitor..................................................................63
4.2.4.4 Trimming Capacitors and Switches ............................................64
4.2.4.5 CLKA Watchdog Circuit ..............................................................64
4.2.4.6 Clock Regenerator/ Pluck Logic .................................................65
4.2.4.7 RF Limiter ...................................................................................65
4.2.4.8 VCL Limiter .................................................................................65
4.2.4.9 Voltage Regulator .......................................................................65
4.2.4.10 Supply and Reference Currents .................................................66
4.2.4.11 Wake Detector ............................................................................66
4.2.4.12 CLKA Sensitivity .........................................................................70
4.2.4.13 EOBA Sensitivity.........................................................................70
4.2.4.14 AGC Amplifier .............................................................................70
4.2.4.16 Control Interface .........................................................................72
4.2.4.17 Clock Supervision .......................................................................72
4.2.4.18 Pulse Position Demodulator .......................................................73
4.2.4.19 Electrostatic Discharge ...............................................................73
4.2.4.20 Package......................................................................................73
58
CHAPTER 4
Product Specification Data
4.1 Absolute Maximum Ratings
Parameter Sign Note Min Nom Max Unit
Operating free-air
TaR -40 85 ºC
temperature
Storage Temperature Ts -40 100 ºC
Battery Voltage VBAT -0.3 5.5 V
1.1 x
Input Voltage VIN MOD, TX -0.3 V
VBAT
TEN, TCLK, 1.1 x

Input Voltage VIN -0.3 V
TDAT VBAT
WAKE, CLKA/M
High Level Output Current IOH 100 µA
EOBA, TDAT
WAKE, CLKA/M
Low Level Output Current IOL 100 µA
EOBA, TDAT
RF1, RF2, RF3

Input Current Iant 10 mA
See Note 1
All further Recommended Operation Conditions are valid for the full operating free-air tem-
perature range, unless otherwise noted!
Note 1:
Continuous activation of one RF input at a time.
59
4.2 Recommended System Operating Conditions

4.2.1 Base Station - Test Station Conditions
Transmitter frequency fTX 120 134.2 140 kHz

Wake-up Time tWAKE 5 10 ms
Wake-up Time tWAKE Backup Mode 10 50 ms
Data Rate fRX 100% AM, PPM 500 2000 4000 bits/s
Pulse Position
Wake Data Rate fWAKE Modulation, 1000 2500 4000 bits/s
16 low bits
Transmitter Operating
QopTX 30 33
Quality Factor
4.2.2 Identification Device Conditions
Note:
The following parameters have to be established in the application.
ANT1, ANT2, ANT3

Resonance Frequency fRES 120 134.2 140 kHz
VCL = 5 V
ANT 1 used for backup
Identification Device Quality
QopTRP function 10 30
Factor
Notes 1 & 2
ANT 1, 2, 3,
Identification Device Quality
QopTRP no backup function 20
Factor
Notes 1 & 2
ANT1, -40...85 ºC
Low Bit Transmit Frequency fL Qop=10…30 130.2 134.7 139.5 kHz
Notes 1 & 2
ANT1, 25 ºC
Low Bit Transmit Frequency fL Qop=10…30 132.0 134.7 136.5 kHz
Notes 1 & 2
ANT1, -40...85 ºC
High Bit Transmit Frequency fH Qop=10…30 118.0 123.7 128.0 kHz
Notes 1 & 2
ANT1, 25 ºC
High Bit Transmit Frequency fH Qop=10…30 120.0 123.7 126.5 kHz
Notes 1 & 2
Notes:
1. Fres = 134.2 kHz.
2. Min/Max parameters depend on LR + CR temperature coefficient.
60
August ’01 Chapter 4. Product Specification Data
4.2.3 Recommended Operating Conditions for IC

4.2.3.1 Identification Device Antennas
Inductance of antenna for LR1,LR2, 25 ºC CR1,2,3 =

2.37 2.47 2.57 mH
fRES=134.2kHz LR3 470 pF +/- 5%
Capacitance of LR1, LR2,
CLR 11 pF
LR3
Quality factor QLR 33
4.2.3.2 Resonant Circuit Capacitor
Resonant Circuit Capacitor CR fRES = 134.2kHz 446.5 470 493.5 pF

Dielectric NP0
Temperature Coefficient of CR dCR/
+/-30 73 ppm/K
(NP0) CR*dT
Dielectric R2H
Temperature Coefficient of CR dCR/ -220/
ppm/K
(R2H) CRdT +60
Quality factor QCR 1000
Operating Voltage RF 20 50 Vpp
4.2.3.3 Charge Capacitor
Backup Function
Charge capacitor CL 10 22 33 nF
not used
Dielectric of CL CLdiel X7R
Charge Capacitor dCL(T)/
+/-10 %
Temperature Variation CL
Charge Capacitor Aging dCL(t)/CL +0/-5 %
Insulation resistance Rins <16 dc 4 GΩ
Dissipation factor DF 0.035
Operating voltage VCL 10 16 Vdc
Itot*
Backup Function
Charge capacitor CLbup tTELEGR F
used
/3V
61
4.2.3.4 IC
Battery Voltage VBAT versus DG 2.0 3.0 4.0 V

Battery Voltage Test VBAT Tst 2.5 4.0
Power Supply Ripple Vripple 50 mVpp
WDEEN, MOD,
0.95 x 1.05 x
High level input voltage VIH TX,VBAT= V
VBAT VBAT
2.0 ... 4V
WDEEN, MOD,
0.05 x
Low level input voltage VIL TX, VBAT = 0 V
VBAT
2.0 … 4V
all outputs except
Output Load Capacitance COL 10 pF
VCCO
all outputs except
Output Load Resistance RL 100 kΩ
VCCO
Output Current IVCCO VCCO 1 mA
with respect to DG, VCL=
Supply Voltage for Trim/
VCL 25 ºC 2.5 VBAT 6 V
Test
=4
High level input voltage, VBAT= 0.95 x 1.05 x
VIH V
TDAT, TCLK, TEN 2…4V VBAT VBAT
Low level input voltage, VBAT= 0.05 x
VIL 0 V
TDAT, TCLK, TEN 2…4V VBAT
Clock frequency fTC TCLK 100 134.2 1000 kHz
Rise and fall time, TDAT,
tf 500 ns
TCLK, TEN
Programming Voltage Vpp TEN pin 15 16 17 V
VPP Rise Time trVPP VBAT to VPP 1 5 ms
VPP Fall Time tfVPP VPP to VBAT 1 ms
Programming Time tPRG 15 20 ms
PTx18,
Pluck Time tpluck PTx28, 100 1000 ns
PTx38
Reset Time treset WDEEN=0 10 µs
Max. EOBA duration during
toffTRP 0.5 ms
Wake Pattern Detection
Max. EOBA duration in
toffTRP WAKE=high 1 ms
Transparent Mode
62
4.2.4 IC Characteristics over Operating Free-air Temperature Range
4.2.4.1 General IC Characteristics
16-pin
Package
TSSOP
4.2.4.2 Input Capacitances
Effective Input VCL = 5 V

Capacitance CRF1 25 ºC 19 23 27 pF
(CRFx=CIx+ dCI/dV) CT = off
VCL<0.5 V
Input Capacitance CI1 25 ºC, 26 pF
CT = off
Effective Input VCL = 5 V

CRF2
Capacitance 25 ºC 12 16 20 pF
CRF3
(CRFx=CIx+ dCI/dV) CT = off
VCL<0.5 V
CI2
Input Capacitance 25 ºC, 19 pF
CI3
CT = off
Temperature Coefficient of
dCI/dT -0.1 pF/K
CI1, C2
Input Capacitance Change VCL = 3...5V

dCI/dV -0.4 -0.5 pF/V
(CT=off) 25 ºC

dCI/dV -0.05 -0.1 pF/V
(CT=on) 25 ºC

dCI/dV -1.1 pF/V
(CT=off) 25 ºC
Input Capacitance Change VC L= 3...5V

dCI/dV -0.2 pF/V
(CT=on) 25 ºC
4.2.4.3 Modulation Capacitor
Modulation Capacitor CM 25 ºC 89.2 105 120.8 pF

Voltage Coefficient of CM dCM/dV 25 ºC 0.2 pF/V
Temperature Coefficient of CM dCM/dT 0.02 pF/K
63
4.2.4.4 Trimming Capacitors and Switches
Trimming Steps Tstep 256

Min. Trimming Capacitor CT0 0
Trimming Capacitor 1 CT1 25 ºC 0.5 0.6 0.7 pF
Trimming Capacitor 6 CT6 25 ºC 16 18.8 21.6 pF
Max. Trimming Capacitor 127.5 150 172.5 pF
CT 25 ºC
(CT = CT1+CT2....+CT8) -15 0 +15 %
Voltage Coefficient of CT dCT/dV 0.1 pF/V
Temp. Coefficient of CT dCT/dT 0.02 pF/K
'On' Res. Trim Switch 1 RT1 VPP = 16 V 800 Ω
'On' Res. Trim Switch 8 RT8 VPP = 16 V 28.0 Ω
'Off' Res. Trim S. 1 ... 8 RT1..8 VPP = 16 V 1 ΜΩ
4.2.4.5 CLKA Watchdog Circuit
CLKA Watchdog Time twdg VBAT = 2 ...4 V 500 800 2600 µs
64
4.2.4.6 Clock Regenerator/ Pluck Logic
Clock Regenerator
Vreg VCL = 2.5 V 10 120 380 mV
Sensitivity
Clock Regenerator
Vreg VCL = 6 V 10 130 400 mV
Sensitivity
4.2.4.7 RF Limiter
RF Limiter Voltage VRFlim Ilim = 10 µA 12 16 V
RF Limiter Voltage VRFlim Ilim = 10 mA 13 17 V
RF Limiter Current IRFlim continuous 10 mA
Note 1:
Continuous activation of one RF input at a time.
4.2.4.8 VCL Limiter
VCL Limiter Voltage VCLlim Ilim = 10 µA 6 V
VCL Limiter Voltage VCLlim Ilim = 10 mA 7 V
VCL Limiter Voltage VCLlim applicative 6 8 V
VCL Limiter Current ICLlim continuous 10 mA
4.2.4.9 Voltage Regulator
Ivcco = 0.5mA
VCCO Output Voltage Vvcco Cvcco >/= 100 pF 2.0 2.15 V
VCL = 3 V
Rvcco = 10 ΜΩ
VCCO Output Voltage Vvcco Cvcco >/= 100 pF 3.4 4.1 V
VCL = VCLlim
Ivcco = 1 mA
VCCO Output Voltage Vvcco Cvcco >/= 100 pF 2.8 3.3 4 V
VCL = 5 V
65
4.2.4.10 Supply and Reference Currents
VBAT = 4 V
Quiescent Current Iquiet 100 nA
WDEEN = 0 V
Stand-by current, VBAT = 4 V

Istby 5 7 µA
3 Antennas WDEEN = 4V
Stand-by current, VBAT = 4 V

Istby 3.5 5 µA
2 Antennas WDEEN = 4V
Stand-by current, VBAT=4V,

Istby 2 3.5 µA
1 Antenna WDEEN=4V
VBAT = 4 V
Initialization Current Iinit WAKE = 0 V 10 µA
WDEEN = 4V
VBAT = 4 V
Active Current Iact WAKE = 4 V 20 30 µA
WDEEN = 4V
Quiescent Current, VCL IVCL VCL= 5 V 0.2 2 4 µA
Supply Current during VCL = 5 V,

IVCL 110 µA
LF Transmission Q = 10
VRF = 5 V
DC Input Current IHF 20 nA
VBAT = 0…4 V
VRF = 10V
DC Input Current IHF 100 nA
VBAT = 0…4 V
4.2.4.11 Wake Detector
For Wake Detector measurements the 3D-AFE should be configured to work without Wake
Pattern Detection. The circuit is supplied by a variable power supply at VBAT (VBAT = 2…4
V) and fed by a Signal Generator between RF1 (RF2, RF3) and VCL (see Figure 33). The
unused RF inputs are connected to VCL.
The sine wave output of the Signal Generator can be switched on and off and the amplitude
also be continuously varied. As well as this, the amplitude can be modulated according to
specification using a Modulation Generator.
The currents are measured via a measurement resistor using a Differential Probe.
The different states of the 3D-AFE are reached by push button activation at WDEEN.
66
Figure 33: Measurement System:Timing, Dynamic Current & Sensitivity
VCL
SIGNAL
GENERATOR f_RES
50Ohm V_wakeA (B, C)
Test / Trimming Interface

RF1 TDAT
ON / OFF JP1
R3 3D ANALOG FRONTEND IC
f mod ~
~ 50
Ohm
JP2
RF2
TMS 37122
TCLK
RF3 TEN
JP3
VCL CLKA
VCCO WDEEN WAKE EOBA /M
GND VBAT MOD TX
MODULATION VBAT
GENERATOR CL
~ 22nF
WDEEN
~ f_mod / 100%
MOD
TX
For simulation:
change of battery
VBAT
POWER JP4
SUPPLY
+2V ... 4V +
C1
100nF
V R meas
_
+
STORAGE SCOPE
+ _
+ _
R meas = 10kOhm
DIFF. TRIG
uA ( 100mV: I=10uA )
PROBE
I_quiet
e.g.: R&S / UIG HP1141A
I_stby
(Micro Ampere Meter) I_init
I_act
50
Ohm PROBE CONTROL
3DMEA07.ch4
& POWER MODULE
HP1142A
4.2.4.11.1 Wake Delays
Settling Time tPdly VBAT = 2…4 V 2 ms
Wake Delay Count cWdly VRF >/= Vwake 256
Wake Delay Time tWdly VRF >/= Vwake 256/ftx ms
67
4.2.4.11.2 Wake Sensitivity A/Antenna 1
Configurable
Wake Sensitivity A typical range
VwakeA/1 5 35 mVpp
Range/ Antenna 1 25 ºC,
VBAT=3V
Wake Sensitivity A/ Configured to

VwakeA/1 2 5 10 mVpp
Antenna 1 highest sensitivity
Wake Sensitivity A
RESA/1 4 Bit
Resolution/Ant. 1
Wake Sensitivity A
VstepA/1 0.5 2 3.2 mVpp
Step Size/Ant. 1
4.2.4.11.3 Wake Sensitivity A/Antenna 2 and 3
Wake Sensitivity A Antenna VwakeA/

Fix 2 5 10 mVpp
2 and 3 2/3
4.2.4.11.4 Wake Sensitivity B/Antenna 1
Configurable,
Wake Sensitivity B typical range
VwakeB/1 5 170 mVpp
Range/ Antenna 1 25 ºC,
VBAT=3V
Wake Sensitivity B VwakeB Configured to

2 5 10 mVpp
Antenna 1 /1 highest sensivity
Wake Sensitivity B RESA

4 Bit
Resolution/Antenna 1 /1
Wake Sensitivity B VstepB

6.0 11 17.5 mVpp
Step Size/Antenna 1 /1
4.2.4.11.5 Wake Sensitivity B/Antenna 2 and 3
Configurable,
Wake Sensitivity B Range/ VwakeB/ typical range
5 170 mVpp
Antenna 2 and 3 2/3 25 ºC,
VBAT=3V
Wake Sensitivity B VwakeB Configured to

2 5 10 mVpp
Antenna 2/3 /2/3 highest sensitivity
68
Wake Sensitivity B RESB

4 Bit
Resolution/Ant. 2 and 3 /2/3
Wake Sensitivity B VstepB

6.0 11.0 17.5 mVpp
Step Size/ Ant. 2 and 3 /2/3
69
4.2.4.12 CLKA Sensitivity
Clock Regenerator VWakeA/

Vclka mVpp
Sensitivity, CLKA 2
4.2.4.13 EOBA Sensitivity
Vmax=
Modulation Depth for valid 33
m VwakeA, %
EOBA (a=50%)
Note1
2
Modulation Depth for idle Vmax=VwakeA,
m(idle) (a=
EOBA Note 1
96%)
VRF = VWAKE to
EOBA Activation Delay dtEOBA VWAKE/2, 15 46 90 µs
VBAT=2V
Step VRF =
VWAKE/2 to
EOB Deactivation Delay dtNEOB 15 42 60 µs
VWAKE,
VBAT=2V
Note 1: a= Vmin / Vmax = (1-m) / (1+m)
4.2.4.14 AGC Amplifier
Coupling Capacity Ccpl 1 pF
Input Impedance/ Low Vrf=5mVpp,

Rin 2 MΩ
Amplitude fTX= 134.2kHz
Input Impedance/ High Vrf=15Vpp,

Rin 1.2 MΩ
Amplitude fTX=134.2 kHz
Center frequency of
fc_AGC 120 kHz
amplifier
dfAGC
-3dB Band-width of amplifier 50 kHz
-3dB
-20dB Band-width of dfAGC

270 kHz
amplifier -20dB
70
4.2.4.15 Test Interface
with respect to DG
Pull-down Resistor, TCLK RTCLK 70 100 250 kΩ
25 ºC
with respect to DG
Pull-down Resistor, TEN RTEN 7 10 25 kΩ
25 ºC
with respect to DG,

Pull-down Resistor, TDAT RTDAT 70 150 250 kΩ
25 ºC, VBAT = 3 V
Low Level Output Voltage, 0.05 x 0.07 x

VOL VBAT = 2…4 V V
TDAT VBAT VBAT
High Level Output Voltage, 0.93 x 0.95 x

VOH VBAT = 2…4 V V
TDAT VBAT VBAT
Low Level Input Current,

IIL VIL = 0 V 0 mA
TDAT
High Level Input Current,

IIH VIH = 4 V 0.05 0.3 mA
TDAT
High Level Output Current IOH TDAT 100 µA
Low Level Output Current IOL TDAT 100 µA
71
4.2.4.16 Control Interface
Input capacitance Ci WDEEN, MOD, TX 10 pF
VIL = 0 V,
Low Level Input Current IIL -10 nA
VBAT = 4 V
VIH = 4 V,
High Level Input Current IIH +10 nF
VBAT = 4 V
VBAT = 2 … 4 V, 0.05 x 0.07x

Low Level Output Voltage VOL V
RL = 100 kΩ VBAT VBAT
VBAT = 2 …4 V 0.93 x 0.95 x

High Level Output Voltage VOH V
RL = 100 kΩ VBAT VBAT
CL = 10 pF,
Rise and fall time tf RL = 100 kΩ 500 ns
VBAT = 2 …4 V
4.2.4.17 Clock Supervision
Control Counter Clock

fctrl fRES Hz
Frequency
Wake Pattern Waiting Count

cwait 1024 16384
(configurable)
Wake Pattern Waiting Time fRES = 134.2 kHz,

twait 7.6 122.1 ms
(configurable) twait = cwait/fRES
Wake Pattern Waiting Count

4 bit
Resolution
Wake Pattern Receive Time

twrx fRES = 134.2 kHz 15.3 ms
(fix value)
Wake Pattern Receive

cwrx 2048
Count (fix value)
Telegram Count ctelegr 4096 65536
fRES = 134.2 kHz,

Telegram Time ttelegr ttelegr = ctelegr / 30.5 488.3 ms
fRES
Telegram Count Resolution 4 bit
72
4.2.4.18 Pulse Position Demodulator
High Bit Detection

cHdet 8 64 128
Threshold Count (PPM)
fRES = 134.2 kHz,

High Bit Detection
tHdet tHdet = cHdet / 59.6 417 891 µs
Threshold Time (PPM)
fRES
4.2.4.19 Electrostatic Discharge
The component withstands the following electrostatic discharges at each pin:

±2 kV Human Body Model (MIL STD 883 compliant)
4.2.4.20 Package
The 3D Analog Front End IC is delivered in the following package:

16 PIN TSSOP: PW (R-PDSO-G16)
For more information about this package please refer to:

http://www.ti.com/sc/docs/psheets/mechanic/P.htm
73
This datasheet has been downloaded from:
www.DatasheetCatalog.com
Datasheets for electronic components.

TIRIS Automotive Devices: Analog Front End IC TMS37122

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TIRIS Automotive Devices: Analog Front End IC TMS37122

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August ’01 Chapter 3.

TIRIS Automotive Devices

11-09-21-046 August 2001

First Edition- August 2001

Copyright  2001 Texas Instruments Incorporated (TI)

About This Guide

If You Need Assistance

Figure 18: State Diagram of LF Transmission Mode ................................... 32

Chapter 1: Product Description

1.1 General Features

Figure 1: TSSOP Package (Top View)

1.3 Circuit Description

Figure 2: System Arrangement of 3D-Analog Front End IC TMS37122

Transceiver / Base Station Identification Device

Typically the device is supplied by a 3 V Lithium-battery. A built-in voltage regulator allows

A complete Identification Device consists of the following parts:

Figure 3: Typical 3D-AFE Application Including Battery Backup Function

PASSIVE ENTRY/ PASSIVE START TRANSPONDER WITH BATTERY BACKUP FUNCTION

VCC OUT OUT OUT INT/INP INT/INP TIMER

Table 1: Description of the Device’s Pins

Pin # Pin Dir Description

Output of the on-chip voltage regulator. This voltage regulator

Device connection pin for the antenna resonator 3. The antenna

Device supply pin for the Transponder's Passive Entry circuitry. A

Output of the 'End of Burst' Detector. The Microcomputer receives

Table 1: Description of the Device’s Pins

Pin # Pin Dir Description

Device connection pin for the antenna resonator 2. The antenna

Connection pin for the antenna resonator 1. The antenna resonator

Device supply pin for LF HDX operation. The charge capacitor CL is

Chapter 2: Electrical Description

continued on next page

3D-ANALOG FRONT-END IC TMS37122 TEST

CR2 CT1 CT8

TRp CONTINUOUS CLOCK DIVIDER

MOD TCLK TDAT TEN

Figure 4: Block Schematic of TMS37122

2.2 Power Supply

2.2.1.1 Standard Battery Supply

Figure 5: Standard Battery Supply - Schematic

2.2.1.2 Rechargeable Battery Supply

Figure 6: Schematic for Rechargeable Battery Supply

2.2.1.3 Battery Backup Supply

Figure 7: Schematic for Battery Backup Supply

2.2.2 VCL Supply

2.2.2.1 Backup Mode

CL [F] = Itot [A] * tTX[Sec] / dVCL [V]

CL = Itot * tTX / dVCL = 2.5µF

2.2.2.2 Test Mode

Figure 8: Test Arrangement with Digital Interface Test Box and PC

TCLK = 0V: Prepare data at TDAT

TDAT = 0: Low data. Change at negative transition of TCLK.

Figure 9: Schematic of Reset Flow

MR VDD VCC VBAT VCCO

CT GND VSS GND

WDEEN tinit tinit

BATTERY LIFE TIME BATTERY

2.4 Limiter Circuits

Figure 10: TMS37122 Limiter Circuits

2.5 Wake Detector

Figure 11: Block schematic of Wake Detector

2.6 End-of-burst Detector

Figure 12: EOB Detector and Pulse Position Modulator Function