A NOVEL DIGITAL MULTIPLIER

CHIP BASED ON THE NEURAL NETWORK

Ho Sun Chung, Jin Kyung Ryeu and Wu I1 Lee

Dept. of Electroninc Engineering, Kyungpook National

University, Taegu 702-701, KOREA

technique. However, the digital output of their ADC

Abstract
depends on the initial states or previous output states
A novel digital multiplier, based on the cif the netvurk, and the inter-connect ions between the
unidirectional feedback type (UFT) neural network, was neuruns are somewhat complex in VLSI implementation. To
desigrlrd and VLSI implement.ad. The number of feedback nveri:ome this problem, successive approximation
connections in the proposed UFT neural network has been algorithm has been used in the design of '-bit ADC
reduced to a half of the number required in the using the optical implementation method[51.
Hopfield model. The application of the UFT neural This paper presents a unidirectional feedback type(llFT)
network tCJ digital c:ircuit.s are i 1 lustrated in neural nettark model. The number of feedback
designing a binary multiplier chip. The architecture of connections in the LIFT model is reduced to a half of
the digital multiplier used in this work is simpler the number required in the Hopfield model. The UFT
than those of earlier ones designed by other model has a capability of constructing a wide range of
conventional digital techniques. digital circuits, where its principal operation is
I. Introduction based on an analog and digital technique. Analog
Because of the advant.ages in the simplicity of c:omputation is used only internally and the input as
neural network and its associated para1 le1 processing well as the output data are digital, thus making

nature, a rapidly grobing number of researchers are integration in a digital-system straight forward. In

working on hardware implementation of neural w d e r to realize the digital circ-uit.s, ve propose to

networksC11. For the VLSI implementation of neural design parallel input 7-to-3 and 1S-trr-4 1's counters
circuits and systems, the analog and digital approach for the purpuse of implementing the high speed 5:::5 and
seems to be extremely attractive in terms of size, 12:::12 digital multiplier designs. The multipliers
pcwer, and speed. Several promising research results d here are different frum the w n ~ e n tional
have been reported, including suc:h det,ices as digital multiplier in both ciri:uit configuration and
assoLiative memories[21 and digital image processor for thv performance. We h a w implementrd the proposed 1 ' s
pattern recognition[31. ~:uuntersand mu1 t ip1 iers Kith 2 micrometer double metal
The simplicity of network architecture and its CHnS tec,hnc,logy.
circuits, composing of amp1 i fiers( neurons) and 11. U n Neural Network Model

conductances(synapses), makes the Hopfield network 'The.Hopfi~ldnetwork has the bidirectional feedback
suitable f o r VLSI implementation. This net,work, which i-ypl, nrtwirk Tlr. which is symmetric and bithout
simply finds the minimum of the energy function, is self-feedhack terms, i.e. Tih = Th, and Til = 0. It has
applied t.o an associative memory and t.n solving bren u w d in the design of Tank-Hopfirld ADC. The
optimization problems. Due to the bidirectional digital output of the ADC is dependent on previnus
feedback connections between the neurons and the output states as vel1 as tllc: initial states. In order
complexity of the energy function, there exist several tn implement J'LSI digital circuits, ve need a special
local minima. A parallel neural network y u r p ( ~ s eneural network, which is unidirectional feedbag-k
analog-to-digital converter(AUC) was designed by Tank i y p e ( l ' F T ) mlndrl shown in Fig. 1.

and Hopfieldl41, vhu used the energy minimization The numbrr of ferdhacrk connect inns in thr proposed

CH2868-8/90/0000-104$1.00 0 1990 IEEE

LIFT model is reduced to a half of t.he number needed for
the cast. of the Hopfield model. We propose a novel
~:lr~uitof the parallel 7-to-3 1 ’ s counter with UFT
mudeI in Fig. 2. The feedback connections from the
higher bit output nodes are unidirectional. All the 7
input signals V1 - V7 art: connected to the PMOS gates
in parallel. And the remaining two terminals GND and
YDD arc’ c:onnt.cted to the PMOS and NMOS gates,
ri.sprv.1 ibely. Two inverters are connected in series and
v11i-k u s clne amplifier(neuron) unit.
The output voltage of neuron ”i” is given by:
f : transfer function of the amplifier(neuron)
VJ : input voltage from neuron j
Vk : output voltage of neuron k
The weight matrix TI, and T a r are defined as
Ttj = 1 (3)
= cf“-‘ ifk>i
i f k g i
(4)
111. Multiplication Alaorithm
The multiplication of binary numbers is performed in
tht, same way as bit11 decimal numbers as shown in Fig.
3 . Let us multiply the two binary numbers 11111 and
11111. The multiplicand is multiplied by each bit of
the multiplier, starting from the least significant
hit. Each s w h multiplication forms a part.ia1 product.
I F the multiplier bit is 1 , the multiplicand is copied
dnwn : otherwise, zero is copied down. The numbers
wpii~d dobn in successive 1 ines are shifted by one
posit inn each t o the left from the previous numbers.
I l w I S R output, is simply the product of A0 and BO.
And by adding two product terms (AO:>Bl) and ( A l X l O ) ,
%-bit carry ”01” is generated at the second stage and
p r ‘ o l ~ g e t e d t o the next stages successively. At the
third stage, 2-bit carry ”10” is generated by adding
j’artial products ( l , l , l ) and a carry from the previous
:;t.agii. For the o t h c r stages, carries are generated by
llre sum of partial product and carries from previous
::tag(.:; as the Gay deswibed above. This addition
prc~cc.;s is identical to counting the number of ”1”.
Thu:, a cmunter which counts the number of ”1” and also
1047
is capable of generating 2-bit. carry is required, The
LSE counter circuit forms the final product output. The
stage at which t.lie most number of addition is performed
is F4 and at this stage, a total of 7
values( 1 , 1 , 1 , l , l , 1 ,O) are counted. Therefore 7-to-3 1 ’ s
wunter which counts the number of ”1” from 7 input is
required t.o obtain the output of P4. For the other
st.ages, the size of the 1 ’ s counter is determined by
the number of partial products and carries.
IV. &sign of Parallel Input 1’s Counter
The 7-to-3 1 ’ s counter designed with UFT neural
model is shown in Fig. 2. Inputs and outputs of this
circuit are V1 to V7 and VO1 to V03, respectively.
Input signals(V1 - V7) and GND are connected to the
stages of PMOS, and feedback signals and VDD are
connected to the stage of NMOS. The geometric parameter
W/L of a MOS t.ransist.orspecifies its conductance. For
a fixed channel length L, the conductance is
proportional to the channel width W. The conductance
value ”1” represents t.he case that W is 5 micrometers
and L is 2 micrometers for the PMOS. For the NMOS, W is
2 micrometer and L is 2 micrometer. Conductances of
FMOS’s are all 1 and those of NMOS’s whose gates are
connected t o VDD are 1, 2 and 4. And the conductances
of NMOS’s of the feedback part are 2 and 4. When all
MOS transistors are on, the difference between the
total conductance of the PMOS and that of the NMOS at
each stage is 1, 2 and 4, respectively.
The operation of the circuit is as follows : If any
input is I , the PMOS of t.hat column will be off. The
output is determined by the difference between the
total conductance of PMOS’s and that of NMOS’s. When
t.he sum of PMOS conductances is greater than or equal
to that of NMOS, the stage of buffer input is regarded
as high ; ot.herwise, it is low. For example, when all
inputs(V1 - ‘47) are 1 all outputs(V01 - V03) are also
1.
V. Design of Multiplier
Fig. 4 sl~o\.s the 5:35 multiplier. It consists of AND
gates and parallel input 1 ’ s counters. Inputs of the
circuit are multiplicands A0 to A4 and the multipliers
BO t o 04, and the output results are FO to P9. The LSB
output PO is simply the product of A0 and BO. The
output P1 is the sum of (A1:XBl) and (AlNiO), and is
obtained from the output of the half adder. The carry
References
is propagated to the next 1’s counter. To obtain output
C11 H. P. Craf, and L. D. Jackel, ”Analog Electronic
P2, count4 circuit is used whose inputs are (Al*B4),
Neural Network Circuits,” IEEE Circuits and Devices
(A2*B3), (A3*B2) and a carry from previous stage. The
Magazine, pp.44-49, July 1989.
output LSB from the count4 circuit forms P2 and the
[Z] R. E. Howard, D. B. Schwartz, J. S . Denker, R. W.
other 2 bits are propagated successively. The other
Epworth, H. P. Graf, W. E. Hubbard, L. D. Jackel,
outputs P3, P4, ... and P9 are obtained by choosing the B. L. Straughn, and D. M. Tennant, ”An Associative
counter circuit in the order of the corresponding
memory Based on an Electronic Neural Network
number of the inputs.
Architecture,” IEEE Trans. on Electroniuc Devices,
Expanding the above mentioned method, a 12*12
vol. ED-34, no. 7 , pp.1553-1556, July 1987.
multiplier was also designed using 15-to-4 1 ’ s counter.
[31 H. P. Craf, and P. devegvar, ”A CMOS Implementation
VI. Simulation Results and Layout of a Neural Network Model,” Proceedings of the
The circuit simulator PSPICE is used as a simulation 1987 Stanford Conference, pp.351-362, the HIT
too1 for simulating a 7-to-3 1’s counter. The simulated Press.

results of the 7-to-3 1’s counter are shown in Fig. [41 D. W. Tank, and J. J. Hopfield., ”Simple ’Neural’
5(a) and (b). It is shown that outputs of 7-to-3 1’s Optimization Networks : an A/D Converter, Signal
counter are determined by the number of ”1” to the Decision Circuit,” IEEE Trans. on Circuits and
input circuit. Systems, vol. CAS-33, no. 5, pp.533-541, May 1986.
IC mask pattern of 5*5 multiplier is shown in Fig. [SI J. S. Jang, S. Y. Shin, and S. Y. Lee, ”Optical
Neural-net Analog-to-Digital Converter,” Optics
6. The circuit was designed with the CMOS 2 micrometer
Letters, vol. 14, no. 3, pp.159-161, Feburary 1989.
double metal design rules.
VII. Conclusion
A unidirectional feedback type(UFT) neural network
model has been presented. The UFT model applications to
digital circuits were demonstrated to the design of a
novel parallel 740-3 1’s counter and a 15-to-4 1’s
counter. Digital 5*5 and 12*12 multipliers were also
designed. These circuits are VLSI implemented with CMOS

2 micrometer double metal design rules. The simulation

results show that the multipliers have been performed \
Y,

correctly. Moreover, the operation time required for

Fig. 1. Unidirectional feedback type model
producing an output is independent of the number of

bits in the digital circuits. Therefore these

multipliers can be used in high speed digital signal U00 GND U1 U2 U3 U4 U5 U6 U7

processing systems.

Uo.

UI.

Fig. 2. Circuit of parallel input 7 to 3 1’s counter.

1048
 ( A 4 A3 A2 A 1 AO) 1 1 1 1 1
(84 E3 82 B1 BO) 1 1 1 1 1

1 1 1 1 1
partial 1 1 1 1 1
products 1 1 1 1 1
1 1 1 1 1
1 1 1 1 1

0 1
1 0
1 0
1 1
1 1
1 0
0 1 f :
0 1
________________________________ i T :M......;.................. ;.................. ;.................. :.................. j
1 1 1 1 0 0 0 0 0 1
t
1
_ 1 I0.

d ;
4 g
F9 P8 P7 P6 P5 P4 P3 P2 P1 PO output products
( a ) Input waveforms.

Fig. 3. 3ultiplication process of binary number

..... ..................,

FIE
Q1
Q2
A3
A4
BE
61
62
E
63
84 ................................................................................................ I
8 , .............................................................................................. ,

. , .. ..................
..................... ,
4
! z s
Fig. 4. Circuit of 535 multiplier.
( b ) Output waveforms.
Fig. 5. Simulation result of 7 to 3 1’s counter.

Fig. 6. Mask pattern of 9 3 5 multiplier.

1049