Question 1.

Design a 1-12 counter (counter which counts from 1 to 12) with the following inputs

and outputs:

• Reset: Synchronous active high reset that forces the counter to 1.

• Enable: Set high for the counter to run

• Clock: Positive edge triggered clock input

• Q: Counter output (Select the number of bits appropriately)

3 Marks

Evaluation: Code without comments or explanation will not be evaluated. Non-synthesizable

code will carry zero marks.

Solution 1 :

module top_mod12(

input reset,

input enable,

input clk,

output [3:0] q

);

reg [3:0] count_reg = 1, count_next;

//Sequential always block

//This always block gets executed at positive edge of the clock

//If reset is 1, the counter will be set to initial value (1)

//If reset is 0, the counter register will take the next count value

always @ (posedge clk)

begin

if (reset == 1'b1)

count_reg <=1;

else

count_reg <= count_next;

end
 //Combinational always block

always @ (*) begin

if(enable) // If enable is 1 ,the counter runs

if(count_reg<4'b1100) //Rollover condition in Combinational block

count_next = count_reg+1; // The counter is incremented

else

count_next = 1; // The counter is set to initial value 1, when the count reaches 12

else

count_next = count_reg; // If enable is 0, the counter is not incremented

end

assign q = count_reg;

endmodule

Marking Criteria :

• Comments Missing : Penalty of ‘-1’

• Incorrect Reset input handling : Penalty of ‘-1’
• Incorrect Enable handling : Penalty of ‘-1’
Solution:

Rubric:
● 1 Mark for Correct Switch case
○ If switch case is incorrect then 0
● 1 Mark for correct output condition
○ If output always block incorrect then 0
● 1 Mark correct syntax
○ If syntax is not correct then 0.
Verilog Code
module parity(
input [35:0] Data_in,
output reg [31:0] Data_out,
output reg Data_status
);

wire [3:0] parity; // Vector containing parity bits of each byte of input data

// assign statements to calculate parity bits of each byte of the Data_in

assign parity[0] = ^(Data_in[7:0]); // XOR operation on 8-bits of data
assign parity[1] = ^(Data_in[15:8]);
assign parity[2] = ^(Data_in[23:16]);
assign parity[3] = ^(Data_in[31:24]);

//Combinational block for Data_out

always @(*)
begin
if(parity==Data_in[35:32]) // checking if parity bits matches
Data_out = Data_in[31:0];
else
Data_out = 32'd0;
end

//Combinational block for Data_Status

always @(*)
begin
if(parity==Data_in[35:32])
Data_status = 1;
else
Data_status = 0;
end

endmodule

Evaluation Criteria
● Correct output for Data_status flag: 1
● Correct output for Data_out: 1
● Correct parity bit generation: 1