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Mfmis VS Mfis
Mfmis VS Mfis
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868 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 3, MARCH 2018
simply connected by a wire, as shown in Fig. 1(c). The MFMIS neglected second-order effects, such as mobility degradation,
structure can thus be simulated by a lumped model approach short channel effects, and so on, in order to compare the
by self-consistently solving the Landau–Devonshire (L–D) two structures only on the basis of the NC effect. Recently,
model of the ferroelectric with the MOSFET physics [13], it has been reported that the NC state in MFMIS NCFET
[15]–[19]. L–D equation relates the voltage drop across the may become unstable in practical devices in the presence
ferroelectric, Vfe and the gate charge density, Q G as Vfe = of leakage current [24] or domain formation [25], which
2α Q G + 4β Q G 3 , where α and β are the material-dependent need to be duly addressed [26]. We have assumed the
parameters. α and β can also be related to the ferroelectric devices to be leakage free in this paper. We have used the
material properties, the remnant polarization (Pr ), and the L–D equation parameters for a CMOS process compatible
coercive field (E c ) [20]. In this paper, we solve the L–D Gd:HfO2 ferroelectric in the simulations [27]. Pr and E c
equation with the Berkeley short-channel IGFET model values calculated from the L–D parameters are found to be
bulk (BSIM-BULK) (formerly BSIM6) MOSFET model [21], 12.13 μC/cm2 and ≈1 MV/cm, respectively [20]. We also
[22] in Verilog-A to simulate the MFMIS NCFET. discuss results with other possible material parameters of
However, for the MFIS structure, the above-mentioned HfO2 -based ferroelectrics later in Section III-C.
approach cannot be used, as the voltage at the ferroelectric–
oxide interface (internal voltage, Vint ) varies in the longitudinal III. R ESULTS AND D ISCUSSION
(source to drain) direction when a nonzero drain bias is A. Drain Current
applied. This structure has been modeled either by adopting a
Fig. 2(a)–(d) compares the I D –VG and I D –V D
full analytical approach [14], [23] or by a distributed modeling
characteristics and the corresponding derivatives for
approach [13] to calculate the channel current. In this paper,
MFMIS and MFIS NCFETs. It is evident that the MFMIS
we apply a segmentation approach to model MFIS NCFET
structure shows higher ON-current, transconductance (gm ),
as a series network of N identical MFMIS units, as shown
and output conductance (gds) compared with MFIS for
in Fig. 1(d), where each unit is modeled using L–D and BSIM-
Pr = 12.13 μC/cm2 . Note that both the structures show a
BULK as explained earlier. Ideally, N should be very large, but
lower threshold voltage and a larger OFF-current compared
our simulation results show that the electrical characteristics
with the reference MOSFET (tfe = 0) due to the internal
start to saturate when N becomes as large as 100 except for
voltage amplification caused by NC effect, which is present
the hysteretic operation regimes. Thus, for simplicity and to
even for VG = 0 as the flat band voltage (VFB ) = 0. Fig. 2(e)
avoid large simulation time, we have assumed N = 100 for the
shows the variation of the ON-current with the thickness of
nonhysteretic cases and N = 300 for the hysteretic cases. All
the ferroelectric layer (tfe ) at iso-IOFF of 1 nA/μm. Iso-IOFF
the simulations have been carried out using the commercial
is achieved using a VFB tuning. As shown in the figure,
Cadence Spectre SPICE simulator. For the MFIS device sim-
ON -current of both the structures increases with tfe with
ulation, SPICE satisfies conditions of channel potential con-
MFMIS excelling MFIS for all the tfe values. These results
tinuity in between the subtransistors and the channel current
are in quite contrast with previously reported results [13], [14]
continuity in all the subtransistors. Simulation using the above-
which use different ferroelectric materials, as explained later.
mentioned method provides node voltages and node currents
For the low values of drain voltage, both the structures show
associated with each node and other electrical quantities of
similar current values as evident in Fig. 2(b). This is expected,
interest used in this paper as follows. For any nth subtransistor
since, for low V D values the internal voltage (Vint in Fig. 1)
(an MFMIS NCFET), the local gate charge density, Q G n
does not vary much from source to drain making the MFIS
(=gate charge per unit area of the n th subtransistor) can
structure behavelike MFMIS.
be accessed from the BSIM-BULK Verilog-A code, which
calculates it using an analytical expression [21], [22]. The
local ferroelectric and internal gate capacitance densities can B. Hysteresis Behavior
then be calculated by the expressions Cfen = ∂ Q G n /∂ Vfen Fig. 3(a) compares the hysteresis characteristics of the two
and Cintn = ∂ Q G n /∂ Vintn , respectively, where Vfen and Vintn , structures observed for large tfe values. First, we note that
respectively, denote ferroelectric and internal node voltages. the MFIS device shows a smoother hysteresis compared with
The inversion charge density at each node (Q I n ) along the the sharp jumps at transition points in the MFMIS device,
channel can again be accessed from the BSIM-BULK code. consistent with [13]. In MFMIS, dipoles in the ferroelectric
BSIM-BULK evaluates inversion charge densities at the source capacitor behave in unison due to the presence of an equipo-
and drain of each subtransistor, which are further used to tential metal layer at the ferroelectric–oxide interface, causing
calculate the surface potential at these nodes [21], [22]. Once, a large change in the polarization and hence, the current.
surface potential is obtained as a function of position, the On the other hand, in MFIS, different dipoles require different
horizontal x-component of the electric field is calculated by gate voltages to reach hysteresis transition depending upon the
taking its negative gradient along the channel. value of the electron–hole quasifermi level difference (VC )
In this paper, we have assumed a long channel internal in the channel, as shown in Fig. 3(b). Hysteresis threshold
MOSFET for both the MFMIS and MFIS NCFETs with length voltages (VG values at which hysteretic jumps occur) increase
L = 1 μm, width W = 1 μm, body doping concentration with VC . Thus, as VG is swept forward, first of all, the dipole
Na = 5 × 1017 cm−3 , interfacial oxide thickness tox = at the source end (VC = 0) makes a hysteretic jump followed
1 nm, and electron mobility μ = 500 cm2 /V-s. We have by other dipoles one by one in continuation from the source
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PAHWA et al.: PHYSICAL INSIGHTS ON NC TRANSISTORS IN NONHYSTERESIS AND HYSTERESIS REGIMES 869
Fig. 2. Comparison of (a) ID –VG , (b) ID –VD , (c) transconductance, and (d) output conductance of MFMIS and MFIS NCFETs for different remnant
polarization values. Solid lines correspond to Gd:HfO2 ferroelectric. MFMIS structure exhibits higher ION , gm , and gds compared with MFIS for the
high Pr . On the contrary, for the low Pr case, MFIS exhibits higher ION , gds , and gm (in the high VG range) than MFMIS. (e) ON-current variation
with ferroelectric thickness for MFMIS and MFIS NCFETs at iso-IOFF . VFB and tfe denote the flat band voltage and the thickness of the ferroelectric
layer, respectively. Ec = 1 MV/cm is used for all the plots.
Fig. 3. (a) Hysteresis characteristics of MFMIS and MFIS devices. MFMIS exhibits hysteresis at larger ferroelectric thickness compared with MFIS.
Hysteresis plots are shown for the equal maximum width of hysteresis (0.1 V) of the two structures. (b) Impact of electron–hole quasifermi level
difference on hysteresis characteristics of ferroelectric dipoles in MFIS NCFET. (c) Variation of ferroelectric (Cfe ) and internal MOS capacitances (Cint )
as the functions of the gate charge density. In this figure, for MFIS, Cfe , Cint , and QG signify local densities at the source end while for MFMIS they
signify the total value of the quantity/gate area.
toward the drain end. This results in a smooth hysteresis of hysteresis windows. Note that the MFMIS structure shows
behavior in I D –VG characteristics of MFIS NCFET. When VG the same hysteresis window at a much larger ferroelectric
is swept backward, dipoles again one by one return to lower thickness (tfe ) compared with the MFIS structure. Also,
polarization values but at different (lower) threshold voltages note that it does not exhibit hysteresis at tfe =18.5 nm
compared with those in the forward sweep, giving rise to a whereas the MFIS does, but still provides a comparable
hysteresis behavior. ON -current. Hysteresis in any ferroelectric–dielectric system
In Fig. 3(a), hysteresis characteristics of MFMIS and occurs when the absolute value of negative ferroelectric
MFIS structures are shown for the equal maximum widths capacitance becomes equal to the value of positive dielectric
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870 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 3, MARCH 2018
Fig. 4. (a) Gate charge density as a function of ferroelectric voltage drop for MFIS NCFET along source to drain direction for different Pr values.
Gate charge density values for the corresponding MFMIS NCFETs are also shown by MFMIS bias points. (b) Inversion charge density profiles in
the channel along source to drain direction. (c) Internal gate voltage (Vint ) and surface potential (ψs ) profiles along source to drain direction. Internal
gate voltage levels for the corresponding MFMIS devices are also given (horizontal lines) for a comparison purpose. (d) Horizontal component of
electric field in the channel along source to drain direction.
capacitance [1], [28]. For MFIS, the onset of hysteresis is source end [29] where Q I denotes inversion charge density
decided by the hysteresis transition in the source end dipole, and E x denotes the horizontal component of the electric
i.e., by the capacitance divider formed there by ferroelectric field. Therefore, we investigate the Q I and E x profiles in the
and internal MOS capacitances. Note that, the capacitance channel for low and high values of Pr in the following to
matching at the source side remains unaffected by the drain explain the above-mentioned observations.
voltage (in a long channel MOSFET). On the other hand, Fig. 4(a) shows gate charge density versus ferroelectric
due to the lumped nature of MFMIS, hysteresis is governed voltage curves for MFIS NCFET for both the high and
by the capacitance divider formed between total ferroelectric low Pr values. The corresponding MFMIS gate charge den-
capacitance and total internal MOS capacitance, which is sities appear as single bias points in the figure (as all the
influenced by the drain voltage [29]. Fig. 3(c) shows these dipoles in MFMIS have the same polarization value). Note
capacitances as a function of gate charge density Q G . At tfe = that in MFIS, Q G always decreases in the source to drain
16.5 nm, ferroelectric capacitance |Cfe | matches exactly with direction due to drain to channel coupling regardless of the
internal MOS capacitance Cint for MFIS implying the onset value of Pr . For high Pr , all the dipoles in the ferroelectric of
of hysteresis. However, in the case of MFMIS, capacitance MFIS reside in the NC regime, as shown in Fig. 4(a). Fig. 4(b)
matching gets disturbed by reduction in Cint caused by a drain shows the inversion charge density profiles in the channel
to channel coupling resulting in a nonhysteretic behavior from source toward drain for MFMIS and MFIS structures.
at the same tfe . MFMIS shows hysteresis only when tfe is MFMIS shows a lower Q I in the channel compared with
increased to 22.5 nm at which |Cfe | reduces and matches with MFIS for the high Pr . This observation can be explained
the lower Cint . Thus, for logic applications, where hysteresis is by considering a simple case of Q I near the source which
unwanted, MFMIS can be considered as a better choice over is a direct function of internal voltage Vint . The Vint at the
a rather hysteresis susceptible MFIS structure for a given tfe . source side [Vint1 in Fig. 1(d)] in MFIS is decided only by
the local capacitor divider built of Cfe1 and Cint1 , which is
independent of V D . While, for MFMIS, it is decided by the
C. Impact of Ferroelectric Material Parameters total lumped capacitances, Cfe and Cint [or the total gate
In general, Pr value of HfO2 -based ferroelectrics can lie in charge, see Fig. 1(c)] which are the functions of V D too in
a range beginning from a small value of 1 to 30 μC/cm2 , while addition to the applied gate voltage. V D disturbs the matching
E c remains close to 1 MV/cm [6], [27], [30]–[33]. Therefore, of the capacitances, as discussed in Section III-B, giving rise
in this section, we explore the behavior of MFMIS and MFIS to a lower Vint , as shown in Fig. 4(c) and therefore, a lower
NCFETs with respect to different values of Pr . Q I in MFMIS compared with MFIS. However, Vint in MFIS
Fig. 2(a)–(d) shows electrical characteristics of MFMIS and structure decreases in the source to drain direction since,
MFIS NCFETs for two different Pr values. For a low Pr value Vint = VG −Vfe , and Vfe increases with a decrease in Q G in NC
of 2 μC/cm2 , MFIS shows a higher ON-current and output region. Note that, the surface potential (ψs ) shown in Fig. 4(c)
conductance (gds) compared with an MFMIS contrary to the still increases but rather gradually compared with MFMIS. The
trends at a higher Pr = 12.13 μC/cm2 . Moreover, MFIS shows decreasing Vint profile in MFIS thus, produces a counter effect
a slightly negative gds or a negative differential resistance for causing a reduction in the horizontal component of electric
high V D values [16]. Both the MFIS and MFMIS for low Pr field in the channel, as shown in Fig. 4(d) compared with
case show a sudden rise in transconductance (gm ) in low VG MFMIS for which Vint remains a constant throughout. This
region with MFMIS also exhibiting a peak in gm in accordance results in a lower ON-current for MFIS than MFMIS in the
with [13]. For MFMIS, gm starts to decrease in high VG region case of high Pr ferroelectric despite a higher inversion charge
while for MFIS, it maintains a monotonically increasing trend. density in the channel for MFIS [Fig. 4(b)].
The channel current in the strong inversion region can be In case of the low Pr ferroelectric, all the dipoles in MFMIS
approximated by μW E x Q I (drift current) calculated near the structure and most of the dipoles in MFIS structure are able to
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PAHWA et al.: PHYSICAL INSIGHTS ON NC TRANSISTORS IN NONHYSTERESIS AND HYSTERESIS REGIMES 871
IV. C ONCLUSION
reach a positive capacitance (PC) state, as shown in Fig. 4(a).
Some of the dipoles close to the drain end in an MFIS structure We provide the new physical insights into the operation of
still reside in the NC region due to a strong drain to channel the MFMIS and the MFIS structures of NCFET. Our analysis
coupling there, which reduces their polarization. Interestingly, shows that for high remnant polarization ferroelectric-
MFIS exhibits a lower Q I compared with MFMIS for low Pr based NCFETs, MFMIS structure excels the MFIS in
ferroelectric devices which derives from a lower Vint for the terms of ON-current with respect to supply voltage and
same, as shown in Fig. 4(c) (we again focus near the source ferroelectric thickness variation. However, for very low
side for simplicity). This is due to the fact that for the dipoles remnant polarization materials, the MFIS shows a relatively
near the source, Vfe > 0 [Fig. 4(a)], which implies Vint < VG . better performance compared with the MFMIS at high supply
While for MFMIS, Q G bias point is lower in value (due voltages. We also show that the MFMIS incurs a hysteresis
to drain voltage effect) with Vfe < 0 in spite of lying in at a larger ferroelectric thickness compared with the MFIS
the PC branch, which implies Vint > VG . This explains a while maintaining comparable ON-current, which makes it a
lower Q I for the MFIS structure. Contrary to the high Pr more suitable choice for hysteresis-free logic applications.
case, Vint in the MFIS structure for low Pr increases from the
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872 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 3, MARCH 2018
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[18] G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, “Designing energy neering from Delhi Technological University,
efficient and hysteresis free negative capacitance FinFET with negative New Delhi, India in 2014. He is currently pursuing
DIBL and 3.5X ION using compact modeling approach,” in Proc. IEEE the Ph.D. degree with IIT Kanpur, Kanpur, India.
Eur. Solid-State Device Res. Conf. (ESSDERC), Sep. 2016, pp. 41–46, His current research interests include the
doi: 10.1109/ESSDERC.2016.7599584. physics and modeling of negative capacitance
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PAHWA et al.: PHYSICAL INSIGHTS ON NC TRANSISTORS IN NONHYSTERESIS AND HYSTERESIS REGIMES 873
Tapas Dutta (M’16) received the Ph.D. degree Yogesh Singh Chauhan (SM’12) was with ST
in nanoelectronics and nanotechnology from Microelectronics, Noida, India, from 2003 to
the Institut National Polytechnique de Grenoble, 2004, IBM, Bengaluru, from 2007 to 2010,
Grenoble, France, in 2014. the Tokyo Institute of Technology, Tokyo, Japan,
He then joined IIT Kanpur, Kanpur, India, as a in 2010, and the University of California at Berke-
Post-Doctoral Researcher, where he involved in ley, Berkeley, CA, USA, from 2010 to 2012. He is
multiscale simulations of III–V and 2-D material- currently an Associate Professor at IIT Kanpur,
based FETs, and compact modeling of negative Kanpur, India. His current research interests
capacitance transistors and the BSIMSOI model. include the characterization, modeling, and
simulation of semiconductor devices.
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