FPGA Based Design

Grading:

Comments:

Section: Electronics

Assignment No: 02 Date of Submission:

April-29-2022

Assignment Title:
Design of 4MB RAM and FIFO module along with test
bench

Submitted by: Muhammad Osama

Submitted to: Dr. Shahid Nazeer

Batch:
BSEE 2019-23

Semester
6th

Department of Electrical Engineering

 Table of Contents
Table of Contents.......................................................................................................................2

1 Objectives:..........................................................................................................................4

2 Introduction:........................................................................................................................4

3 Procedure............................................................................................................................4

4 Results:................................................................................................................................5

4.1 Main RAM module:....................................................................................................5

4.2 RAM Testbench...........................................................................................................5

4.3 Tasks............................................................................................................................6

4.3.1 To initialize all the variables:..........................................................................................6

4.3.2 To make a text file that is filled with random data:.......................................................6
4.3.3 To write data in from the text file and update the write signal:....................................6
4.3.4 To read data from the text file and update the read signal;..........................................7
4.3.5 To compare the two text files and see if they equal:.....................................................7
4.4 Console View:.............................................................................................................8

4.5 Output 4MB RAM:......................................................................................................8

4.6 Write and Read Output files:.......................................................................................9

4.7 Compare data...............................................................................................................9

4.8 Output files:...............................................................................................................10

4.9 Discussion and Conclusion:......................................................................................10

5 FIFO Module....................................................................................................................10

5.1 Procedure:..................................................................................................................10

5.2 Block Diagram:.........................................................................................................11

5.3 Task No. 1.................................................................................................................12

5.3.1 (Main FIFO module).....................................................................................................12

 5.3.2 Testbench FIFO Module:..............................................................................................13
5.3.3 Results..........................................................................................................................14
5.4 Task No.2(Updated code using two Instances):........................................................14

5.4.1 Block Diagram:.............................................................................................................14

5.4.2 Main FIFO Module:......................................................................................................15
5.4.3 RAM Controller:...........................................................................................................15
5.4.4 General RAM Module:.................................................................................................16
5.4.5 Testbench FIFO Module:..............................................................................................16
5.4.6 Results:........................................................................................................................17
5.4.7 Discussion and Conclusion:..........................................................................................17
6 References:........................................................................................................................18
1 Objectives:
 To make 4Mb RAM module along with test bench
 To make 4 Mb FIFO module

2 Introduction:
Random-access memory is a form of computer memory that can be read and changed in
any order, typically used to store working data and machine code. A random-access
memory device allows data items to be read or written in almost the same amount of time
irrespective of the physical location of data inside the memory.
FIFO is an approach for handling program work requests from queues or stacks so that
the oldest request is handled first. In hardware, it is either an array of flops or read/write
memory that stores data from one clock domain and on request supplies the same data
to other clock domains following FIFO logic

3 Procedure
 Assigned RAM: 4MB
 The address lines were computed as 𝑎 = 𝑙𝑜𝑔2(4000 ∗ 1024) and were taken as
22. The address lines were taken to be 8.
 The memory was filled with write only commands and the data wrote was
random.
 The read function was enabled, and the read function requested random
addresses between 0 and 4194304.
 Read and write data was dumped into output text files.
 Different task modules were used to implement the RAM testbench.
.
4 Results:
4.1 Main RAM module:

4.2 RAM Testbench

4.3 Tasks

4.3.1 To initialize all the variables:

4.3.2 To make a text file that is filled with random data:

4.3.3 To write data in from the text file and update the write signal:
4.3.4 To read data from the text file and update the read signal;

4.3.5 To compare the two text files and see if they equal:
4.4 Console View:

4.5 Output 4MB RAM:

4.6 Write and Read Output files:

4.7 Compare data

4.8 Output files:

4.9 Discussion and Conclusion:

The RAM assigned was 4Mb. The RAM module was defined and initialized. The
parameter was defined for the specific RAM which was parameter [23:0] DEPTH = 2^23.
Random data was stored into the RAM and then read when the read function was
enabled.The read and write data was stored in different output files respectively. Both the
data were compared using the compare function and the data was stored in an output file
named compare_data.txt as shown in the results section. Different task modules were used to
implement the RAM testbench as shown in section 4. In short, the data files were writte
according to the defined RAM and the outputs verified the correct working of the 4Mb RAM.

5 FIFO Module
5.1 Procedure:

FIFO is an approach for handling program work requests from queues or stacks so that
the oldest request is handled first. In hardware, it is either an array of flops or read/write
memory that stores data from one clock domain and on request supplies the same data
to other clock domains following FIFO logic. Hence, we first store some data into a text file.
We want that when we have a read signal the date input first comes out first.

 To achieve that, a RAM module was used that stores the data is written in the file.
 Read and write pointers were used that are basically the address of the read and
write location.
 Code writes into FIFO when it is empty and Write signal is enabled
 FIFO has some data and Read signal is enabled. If FIFO is full then we cannot write
into it and if FIFO is empty, we cannot read from it.
 A combinational logic is used to control the values from RAM. The read and write
pointers are fed as the addr_r and addr_w respectively.
5.2 Block Diagram:

Figure 1: Block Diagram for FIFO module

5.3 Task No. 1

5.3.1 (Main FIFO module)

5.3.2 Testbench FIFO Module:
5.3.3 Results
5.4 Task No.2(Updated code using two Instances):

5.4.1 Block Diagram:

Figure 2: Block Diagram for FIFO module using RAM controller

5.4.2 Main FIFO Module:

5.4.3 RAM Controller:

5.4.4 General RAM Module:

5.4.5 Testbench FIFO Module:
5.4.6 Results:

Updated FIFO 4MB output(RAM controller used)

Zoomed Version:

5.4.7 Discussion and Conclusion:

In the test bench, the data was written to the FIFO and than stored into the RAM. The data is read
from the FIFO module using the dout function. It was observed from the waveforms that when the
data was written, FIFO gave a full_signal and when the data was read, an empty_signal was
generated.

When the data was read from an empty FIFO, it gave an underflow_signal and an overflow_signal
was generated when an already full FIFO was written on. All the results were verified and
implemented successfully, and the waveforms are attached in the results section for reference.

The FIFO module was updated to complete the second task and a ram controller module was
defined. Both the ram controller and the general ram module were initialized and called in the
update FIFO top module. The waveforms for both the FIFO working are attached in the results
section 5.3.3 for Simple FIFO using RAM and 5.4.6 for FIFO using RAM controller module. In a
nutshell, all the modules were working and the functioning of the code was verified successfully.

6 References:
 [1]
“ModelSim ® Tutorial.” [Online]. Available: https://www.microsemi.com/document-
portal/doc_view/131618-modelsim-tutorial.

 [1]
“ISE In-Depth Tutorial,” 2011. [Online]. Available:
https://www.xilinx.com/htmldocs/xilinx13_3/ise_tutorial_ug695.pdf

 [1]
 “ISE 10.1 Quick Start Tutorial.” Accessed: Apr. 20, 2022. [Online]. Available:
https://www.eng.auburn.edu/~strouce/class/elec4200/qst.pdf