BRAC UNIVERSITY DEPT. OF COMPUTER SCIENCE AND ENGINEERING COURSE NO.: CSE250 Circuits and Electronics Laboratory Experiment No. 4 Name of the Experiment: Verification of Thevenin’s Theorem and Maximum Power Transfer Theorem. Name Md Nam Panve Section StudentID | QUWOll9S Groap No, Part 1 OBJECTIVE: To verify Thevenin's theorem with reference to a given circuit theoretically as well as experimentally. INTRODUCTION: It is often desirable in circuit analysis to study the effect of changing a particular branch element while all other branches and all the sources in the circuit remain unchanged. Thevenin’s theorem is a technique to this end, and it reduces greatly the number of computations that we have to do each time a change is made. Using Thevenin’s theorem the given circuit excepting the particular branch to be studied is reduced to the simplest equivalent circuit possible and then the branch to be changed is connected across the equivalent circuit. ‘Thevenin’s theorem states that any two-terminal linear bilateral networks containing sources and passive elements can be replaced by an equivalent circuit consisting of a voltage source (Vth) in series with a resistor (Rth), where, Vth = The open circuit voltage (VOC) at the two terminals A & B. Rh = The resistance looking into terminals A and B of the network with all sources removed. Rn A sk A +h + Linear + Bilateral Vi Ve Re Network _ = eI B There are several methods for determining Thevenin resistance Ryy. An attractive method for determining Rru is: (1) determine the open circuit voltage, and (2) determine the short circuit current Isc as shown in the figure; then Linear Bilateral Ra= Voc Network ISCAPPARATUS: > Rnitnre: Ry 1, Re= 3.9 OR, Rae 47 ORL” 1 (KA); 2.2(KO) > Multimeter > DC Power Supply > Breadboard > Jumper wires PROCEDURE: > Arrange the original circuit as shown in the > Measure Vi, I for three values of RL ‘& recot Ry, 3.3kQ figure. Apply 10V de from de power supply rd the data in the table. Ri, (1 kA, 2.22) -| | lov Ox Ry, 1k Rs 4.7K. ve Circuit 1: Original Circuit FINDING Vp & Rau: > Remove the load resistance RL and find the open circuit voltage between terminals A & B. This voltage is Thevenin voltage i.e., Vth=Voe- Ry, 33k A + tov Vz Ri tk Rs, 4.7KQ. Voc B Circuit 2: Cireuit for finding Voc >Placea short circuit between terminals A & B and find the short cireuit current Isc. Divide the open’ circuit voltage by short circuit current to find the Thevenin resistance, Le Voc R= TseRe 3.3k0. A ov (F)vy Rika Ry 47K. [te > Construct Thevenin’s equivalent circuit as shown in figure 4 setting the power supply at Vix volts and the rheostat at Rry ohms. Now measure the load current I, and the load voltage V;. for the values of Ry, determined in step 2. Compare these values with previous values. Ra, Re (1KO,2.2 KO) Circuit 4: Thevenin equivalent circuit REPORT: 1, Find theoretically the Thevenin equivalent circuit for the values of Ry, Ro, Ry & Vs recorded in the table. Also find I,, and V,.Replys li at Mise. Ln Ve Va Va Cart Be)” FEO Ry Neo NV, = “Ae ~ 10/3202 . Re RN Va Moo * 5 884 ee “Thevenin Gaeutt : = 4 t.- ve 2 OBE 2.004 mA te eR 92 *hO1S T eR = 200SxX LOG s 2.033 4F Noe a 2. Show the results in tabular form (Table 1- Table 4). 3. Mention the advantages of using the Thevenin Theorem, Aa simple need i assessing powert eineuls, whieh frp Wave a food dtel chenges voluc Hrnowphet tea omabyss pnecery 6 povided! by cthevenin’s Theonam ator! navies to redo. goon entive aundl, fa dreonoms offers om Aiclive dacknique fo doton mba fa voldoge cuncit Hg acres, te Lead. thevenins theonam 1s parteadanky h Infol whey andly2ing— poston sputter. And —oftan amends that conbdn « cingle- neriston — thot Jy sabjeot dy change nrecontttina nN cecluldon of de inet An cach possible a ds — ood pesrynce In orden defemiwe ee wilt acess i geek ttt aunnet cthnewgeh .OBJECTIVE: Part2 Hib shieodt ‘ F e objective of this experiment is to verify the maximum power transfer theorem. THEORY: ‘The maxim i um power transfer theorem states that a resistive load will receive maximum power when a Tesistive value is exactly equal to the Thevenin's resistance of the network as “seen” by the * Rn A Linear —e Bilateral Re a Circuit = = Va Ru ° B B We know that any circuit A terminated with a load Rt can be reduced to its Thevenin’s equivalent. Now according to this theorem, the load R will receive maximum power when Ri=Rrx The efficiency of power transfer is defined as the ratio of the power delivered to the load Pour, to the power supplied by the source Prv. on = Poet x 100= Ye x 100 =—Re — x 100 Py Vine Ri+ Rr The voltage regulation is defined Load voltage at no load — Load voltage at full load SSS esSCSCSsSSSS~CSC~CS~S Load voltage at full load R ‘At maximum power transfer condition, n= 50 % & VR= 100 %, Arelatively low efficiency ‘of 50 % can be tolerated in situations where power levels are relatively Tow such as in electronic & communications circuits for transmission & reception of signals where the Engineer's goal is o receive or transmit the maximum amount of power. However, when large power levels are involved, such as at generating stations, efficiencies of 50 % would not be acceptable. The goal here is high efficiency andnot maximum power. Power utility systems are designed to transmit the power to the load withthe greatest efficiency by reducing the Josses onthe power lines. Thus, the effort is concentrated on reducing RTH, which would represent the resistance of the source plus the line resistance.APPARATUS: > Multimeter > DC power supply > Resistors: R,=220.Q, 470.0, 1 kO, 1.5 kO, 1.94 kQ, 3.3kO, 4.7 KO, 5.6 kA, 10k, 18k > Breadboard << <—~ > Jumper wires Vin Cireuit 5: Cirouit for maximum power transfer theorem verification PROCEDURE: > Set up the circuit as shown in figure. > Apply Vth from de power supply. » Vary the load resistor from 220 Q to 18 kO & measure the voltage VI, & the current I REPORT: 1. Show the results in tabular form (Table 5). 2. Plot the following curves using the data from Table 8. Attach the plots to your report separately, (See next page for the instructions to plot using Google sheet) ) %nvsRL i) %VRvs RL ii) Loss vsRL iy) POUT vs RL y ILvsRL vw) VivsRLPART 3 PLOTTIN ve G CIRCUIT CHARACTERISTICS ON GOOGLE SHEETS . ain, : eee by visiting https://docs.eoogle.com/spreadsheets ae ea a ‘with the data that you've collected in the lab (refer to your lab sheet), lumn Rt. (ka) and any other column you want to plot with (to select a column, click on the column head, e.g, “A” , €.g,, “A”. Then hold CN’ iki og, "Bt select oth eoheone) ITRL while clicking the second column, sR Loe Pout ow 26] - 1 32 | i ee Note: This is a sample data collected from a simulation. Your data may not ‘match with this. 3, Select Insert @ Chart. You should be getting a graph that looks like the folowing diagram. [iii rermat osta rose enterons He | Prax ri) vs. RL KO) oo a = es , & Orwing Function ou 1B checker @ Peosie che B comment cuteanent B Nowe4. A Chart Editor section should pop up at the right side of your screen. If it doesn’t show up, then double click on the graph, Go the setup section in the chart editor and change the “Chart type” to “Line chart”. Your ‘graph should be changed into a line plot as shown below. @ Chart editor x Customize ute = 5, Ina similar way, plot %n vs Ri, %VR vs Rt, Loss vs Rt, Pour vs Rt, Invs Rr, Vivs Rt. DISCUSSION: 1. Comment on the results obtained and discrepancies (if any),Data Table Signature of lab faculty ayaa Date: Group Table 13 Circuit 1 Ri (kQ) Ri(kQ) Rs(kQ) WOls %. 26D Gey Table 2: Circuit 1 Load Volt: Load current. Observation | Ru(kO) | MON Ty) eV Re (mA) Experimental 2.026 Theoretical 4 Table 3: Circuit 2 & Ciréuit3 Jo For cireult 2 Voc (V) For circuits | 0a R= Vrallsc (KO) Experimental B88 Experimental | % 064 Experimental Theoretical | 5-98 Theoretical | % 5-74 Theoretical | + 9}) ‘i Load Voltage Load current Observation | Ru(kQ) Vi) | evURu (mA) Experimental 0 DBR 1.290, Theoretical Qo"Table 5: Circuit 5 Le Pw Re(kQ) | Vn (V) | Ve(¥) | VURL | Viele Vult | Piv-Pour (mA) (mW) _| (mW) (mw) = | Pour= | LOss= wn | %vR Oe] Hee |G [resy [io-goa [3399] 509 BNL 1910326 for | See [ Yerfor4ge | ago B [8294 | 0,605 81 9% | BOK lab&] SES | 522 forgos [4-936] 1-syt | 0194 ee7e [10-84 oye | S38 [2786 [1-442] 4.307 [3-996 [4.971 U7.9e |H-26 56 | 58 | ano [0-755 [4-494 [3490 [1.250 LWT [3G 25 dons 7865 | 1-844 psae [9-440] %065 [levy [122% 4446 2396 | 1609 [9-465 [3-824 | 5.646 [40-40 3-934 B.s1t [108K [6.963 [B-C1t [ase [5% 7) ona. Aro4y [Hat> [1z.048 [2344 | 163417 79 GAl9: 0538 [a you 140954 PBC NZ 9541 9,149, Error Calculation © Percentage of Error = Theoretical Value am Theoretical Value - Experimental Value Theorestent Vets — Sxpermeniaivet X 100% Table 6; Error Calculation Parana Theoreial [Experimental |g, egy Table 3: Voc(V) B86 OY, Table 3: _Isc= Vs/R:(mA) B04 0 +397. Table 3: | Rra= VrulIsc(kQ) hon ote 0+ %64y, _ Expected Value ~ Observed Value 7 © Percentage of Error = "Empetdvene X 100% Table 7: Error Calculation Original Circuit (Table 2) | Thevenin’s Circuit (Table 4) | 9, Paneer, [Expected Value] [Observed Value] % Error epemenay | V99® 1583 0 BYosyen vs. R 100 18 = 0 a 25 ° 2 4 6 8 10 2 14 16 R Vivs.R 8 4 > 2 o 2 4 6 3 10 72 4 16Ilvs.R 25 20 15 10 0s 00 pout vs. R 4 poutloss vs. R loss %VRvs.R 1000 50 500 VR 250