Index

Sr. No Experiment Page No Remark

1. Introduction to VHDL.
2. To write a program in VHDL for
implementing the half adder and to verify
the functionality.
3. To write a program in VHDL for
implementing the full adder and to verify
the functionality.
4. To write a program in VHDL for
implementing the half subtractor and to
verify the functionality.
5. To write a program in VHDL for
implementing the full subtractor and to
verify the functionality.
6. To write a program in VHDL for
implementing the 2 to 4 decoder and to
verify the functionality.
 Experiment – 1
Aim :- Introduction to VHDL.
Theory :- What is VHDL?
VHDL stands for Very High-Speed Integration Circuit HDL (Hardware
Description Language). It is an IEEE (Institute of Electrical and Electronics
Engineers) standard hardware description language that is used to
describe and simulate the behavior of complex digital circuits.

The most popular examples of VHDL are Odd Parity Generator, Pulse

Generator, Priority Encoder, Behavioral Model for 16 words, 8bit RAM,
etc.

VHDL supports the following features:

o Design methodologies and their features.

o Sequential and concurrent activities.
o Design exchange
o Standardization
o Documentation
o Readability
o Large-scale design
o A wide range of descriptive capability.

History of VHDL

VHDL was developed by the Department of Defence (DOD) in 1980.

o 1980: The Department of Defence wanted to make circuit design

self-documenting.
o 1983: The development of VHDL began with a joint effort by IBM,
Inter-metrics, and Texas Instruments.
o 1985 (VHDL Version 7.2): The final version of the language under
the government contract was released.
 o 1987: DOD permitted for commercial purpose, and VHDL became
IEEE Standard 1076-1987.
o 1993: VHDL was re-standardized to enhance the language
o 1996: A VHDL package used with synthesis tools and became a part
of the IEEE 1076 standard.
o 1999: Analog Mixed Signal extension (VHDL-AMS)
o 2008: IEEE Standard 1076-2008 (New features) was released.

Why VHDL?

VHDL is used for the following purposes:

o For Describing hardware

o As a modeling language
o For a simulation of hardware
o For early performance estimation of system architecture
o For the synthesis of hardware

Basic elements of VHDL

There are the following three basic elements of VHDL:

ENTITY

The Entity is used to specify the input and output ports of the circuit. An
Entity usually has one or more ports that can be inputs (in), outputs (out),
input-outputs (inout), or buffer.

An Entity may also include a set of generic values that are used to declare
properties of the circuit.

Entity Declaration

You can declare an entity using the following syntax:

Simplified syntax

1.      entity entity_name is  
2. ort (  
 3. port_1_name : mode data_type;  
4. ort_2_name : mode data_type;  
5.                  .......  
6.                  Port_n_name : mode data_type  
7.                  );  
8.     end entity_name; 

Using generic

If an entity is generic, then it must be declared before the ports. Generic

does not have a mode, so it can only pass information into the entity.

Simplified syntax

1. entity entity_name is  
2.     generic (  
3.                   generic_1_name : data_type;  
4.                   generic_2_name : data_type;  
5.                    ........  
6.                   generic_n_name : data_type  
7.                    );  
8.  port (  
9.              port_1_name : mode data_type;  
10.               port_2_name : mode data_type;  
11.               ........  
12.               Port_n_name : mode data_type  
13.                );  
14.      end entity_name;  

Rules for writing Port name:

- Port name consist of letters, digits, and underscores.

- It always begins with a letter.
- Port name is case insensitive.

Modes of Port

in         Input port
out         Output port
inout         Bidirectional port
buffer         Buffered output port

Architecture

Architecture is the actual description of the design, which is used to

describe how the circuit operates. It can contain both concurrent and
sequential statements.

Architecture Declaration

An architecture can be declared using the following syntax:

1. architecture architecture_name of entity_name is  
2. begin  
3.    (concurrent statements )  
4. end architecture_name;  

configuration
A configuration defines how the design hierarchy is linked together. It is
also used to associate architecture with an entity.

Configuration Declaration

1. configuration configuration_name of entity_name is  
2. --configuration declarations  
3. for architecture_name  
4.   for instance_label : component_name  
5.      use entity library_name.entity_name(architecture_name);  
6. end for;  
7. --  
8. end for;  
9. end [configuration] [configuration_name];  

Types of Modeling Style in VHDL

There are 4 types of modeling styles in VHDL:

1. Data flow modeling (Design Equations)

Data flow modeling can be described based on the Boolean expression. It
shows how the data flows from input to output. It works on Concurrent
execution.

2. Behavioral modeling (Explains Behaviour)

Behavioral modeling is used to execute statements sequentially. It shows

that how the system performs according to the current statement.

Behavioral modeling may contain Process statements, Sequential

statements, Signal assignment statements, and wait statements.

3. Structural modeling (Connection of sub modules)

Structural modeling is used to specify the functionality and structure of

the circuit.

Structural modeling contain signal declarations, component instances,

and port maps in component instance.

VHDL Objects

VHDL uses the following three types of objects:

1. Constants :- Constant is an object which can only hold a single value

that cannot be changed during the whole code.

Example: constant number_of_bytes integer:=8;

2. Variables :- A variable also holds a single value of a given type. The

value of the variable may be changed during the simulation by using
variable assignment operator.Variables are used in the processes and
subprograms.Variables are assigned by the assignment operator ":=".

Example : variable index: integer :=0;

3. Signals :- Signals can be declared in architecture and used anywhere

within the architecture. Signals are assigned by the assignment operator
"<=".

Example :-
Signal sig1: std_logic;
Sig1 <= '1'

Data Types in VHDL

Data Types are the abstract representation of stored data.

There are the following data types in VHDL -

1. Scalar Types

o Integer
Integer data types are the set of positive and negative whole
numbers.
o Floating point
Floating point data types are the set of positive and negative
numbers that contain a decimal point.
o Enumeration
Enumeration data type is used to increase the readability of the
code.
o Physical
Physical data type describes objects in terms of a base unit,
multiples of base unit, and a specified range.

2. Composite Types

o Arrays
Arrays are used to hold multiple values of the same types under a
single identifier
o Record
Records are used to specify one or more elements, and each
element has a different name and different type.

VHDL Operator

VHDL Operators are used for constructing the expressions.There are the
following types of operators in VHDL:

1. Logical Operators
Logical Operators are used to control the program flow. When the logical
operators combined with signals or variables, then it is used to create
combinational logic.

o and
o or
o nand
o nor
o xor
o xnor
o not

2. Relational Operators

In VHDL, relational operators are used to compare two operands of the

same data type, and the received result is always of the Boolean type.

o = Equal to
o /= Not Equal to
o < Less than
o > Greater than
o <= Less than or equal to
o >= Greater than or equal to

3. Arithmetic Operators

Arithmetic Operators are used to perform arithmetic operations. These

operators are numeric types, such as integer and real.

o + Addition
o - Subtraction
o * Multiplication
o / Division
o & Concatenation
o mod Modulus
o rem Remainder
 o abs Absolute Value
o ** Exponentiation

4. Shift Operators

In VHDL, shift operator is used to perform the bit manipulation on the

data by shifting and rotating the bits of its first operand right or left.

o Sll shift logical left

o Srl shift logical right
o Sla shift arithmetic left
o Sra shift arithmetic right
o Rol rotate left
o Ror rotate right

Advantage of VHDL

A list of advantages of VHDL is given below:

o It supports various design methodologies like Top-down approach

and Bottom-up approach.
o It provides a flexible design language.
o It allows better design management.
o It supports a multi-level abstraction.
o It provides tight coupling to lower levels of design.
o It supports all CAD tools.
o It strongly supports code reusability and code sharing.

Disadvantage of VHDL

A list of disadvantages of VHDL is given below:

o It requires specific knowledge of the structure and syntax of the

language.
o It is more difficult to visualize and troubleshoot a design.
o Some VHDL programs cannot be synthesized.
o VHDL is more difficult to learn.
 Experiment – 2
Aim :- To write a program in VHDL for implementing the half adder and
to verify the functionality.
Required Component :- Multisim Softwere.
Theory :- Half adders are a basic building block for new digital
designers. A half-adder shows how two bits can be added together
with a few simple logic gates. A single full-adder has two one-bit
inputs, a carry-in input, a sum output, and a carry-out output.
Half adder is the simplest of all adder circuits. Half adder is a
combinational arithmetic circuit that adds two numbers and produces a
sum bit (s) and carry bit (c) both as output. The addition of 2 bits is done
using a combination circuit called a Half adder. The input variables are
augend and addend bits and output variables are sum & carry bits. A and
B are the two input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of A
and B. it is evident from the function of a half adder that it requires one
X-OR gate and one AND gate for its construction.
Truth Table Diagram
Input Output
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

VHDL Program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_adder is

port(a,b:in bit; sum,carry:out bit);

end half_adder;

architecture data of half_adder is

begin

sum<= a xor b;

carry <= a and b;

end data;

Waveform:-
Result :- This is a program in VHDL for implementing the half adder and to
verify the functionality.
 Experiment – 3
Aim :- To write a program in VHDL for implementing the full adder and to
verify the functionality.
Required Component :- Multisim Softwere.
Theory :- Full Adder is the adder which adds three inputs and
produces two outputs. The first two inputs are A and B and the third
input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM
Full Adder is the adder that adds three inputs and produces two outputs.
The first two inputs are A and B and the third input is an input carry as C-
IN. The output carry is designated as C-OUT and the normal output is
designated as S which is SUM. A full adder logic is designed in such a
manner that can take eight inputs together to create a byte-wide adder
and cascade the carry bit from one adder to another. we use a full adder
because when a carry-in bit is available, another 1-bit adder must be
used since a 1-bit half-adder does not take a carry-in bit. A 1-bit full
adder adds three operands and generates 2-bit results.
Truth Table

Input Output
A B CIN Sum COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Diagram

VHDL Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is port

(a,b,c:in bit; sum,carry:out bit);

end full_adder;

architecture data of full_adder is

begin

sum<= a xor b xor c;

 carry <= ((a and b) or (b and c) or (a and c));

end data;

Waveform:-

Result :- This is a program in VHDL for implementing the full adder and to
verify the functionality.

Experiment – 4
Aim :- To write a program in VHDL for implementing the half subtractor
and to verify the functionality.

Required Component :- Multisim Softwere.

Theory :- The Half-Adder is a basic building block of adding two
numbers as two inputs and produce out two outputs. The adder is
used to perform OR operation of two single bit binary numbers.
A half subtractor is a digital logic circuit that performs binary subtraction
of two single-bit binary numbers. It has two inputs, A and B, and two
outputs, DIFFERENCE and BORROW. The DIFFERENCE output is the
difference between the two input bits, while the BORROW output
indicates whether borrowing was necessary during the subtraction.
The half subtractor can be implemented using basic gates such as XOR
and NOT gates. The DIFFERENCE output is the XOR of the two inputs A
and B, while the BORROW output is the NOT of input A and the AND of
inputs A and B.
Truth Table Diagram
Input Output
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

VHDL Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library ieee;

use ieee.std_logic_1164.all;

entity half_sub is

port ( a,b : in std_logic;

dif,bo: out std_logic );

end half_sub;

architecture sub_arch of half_sub is

begin
 dif <= a xor b;

bo <= (not a) and b;

end sub_arch;

Waveform:-

Result :- This is a program in VHDL for implementing the half subtractor

and to verify the functionality.

Experiment – 5
Aim :- To write a program in VHDL for implementing the full subtractor
and to verify the functionality.
Required Component :- Multisim Softwere.
Theory :- The Half Subtractor is used to subtract only two numbers.
To overcome this problem, a full subtractor was designed. The full
subtractor is used to subtract three 1-bit numbers A, B, and C,
which are minuend, subtrahend, and borrow, respectively. The full
subtractor has three input states and two output states i.e., diff and
borrow.
A full subtractor is a combinational circuit that performs subtraction of
two bits, one is minuend and other is subtrahend, taking into account
borrow of the previous adjacent lower minuend bit. This circuit has
three inputs and two outputs. The three inputs A, B and Bin, denote the
minuend, subtrahend, and previous borrow, respectively. The two
outputs, D and Bout represent the difference and output borrow,
respectively. Although subtraction is usually achieved by adding the
complement of subtrahend to the minuend, it is of academic interest to
work out the Truth Table and logic realisation of a full subtractor; x is the
minuend; y is the subtrahend; z is the input borrow; D is the difference;
and B denotes the output borrow. The corresponding maps for logic
functions for outputs of the full subtractor namely difference and
borrow.
Truth Table
Input Output
A B BIN Difference BOUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Diagram

VHDL Program
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_sub is

port(a,b,c: in bit; sub, borrow:out bit);

end full_sub;

architecture data of full_sub is

begin

sub<= a xor b xor c;

borrow <= ((b xor c) and (not a)) or (b and c);

end data;

Waveform:-

Result :- This is a program in VHDL for implementing the full adder and to
verify the functionality.

Experiment – 6
Aim :- To write a program in VHDL for implementing the 2 to 4 decoder
and to verify the functionality.
Required Component :- Multisim Softwere.
Theory :- A Decoder is a combinational logic circuit that has ‘n’ input
signal lines and 2n output lines. In the 2:4 decoder, we have 2 input lines
and 4 output lines. In addition, we provide ‘enable‘ to the input to
ensure the decoder is functioning whenever enable is 1 and it is turned
off when enable is 0.
Truth Table:-
Input Output
A/A0 B/A1 En Y3 Y2 Y1 Y0
X X 0 X X X X
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0

Diagram :-
VHDL Program :-
1. 2 to 4 decoder using logic gates
entity decoder2 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder2;

architecture bhv of decoder2 is

begin

b(0) <= not a(0) and not a(1);

b(1) <= not a(0) and a(1);
b(2) <= a(0) and not a(1);
b(3) <= a(0) and a(1);

end bhv;

2. 2 to 4 decoder using if else statement

entity decoder1 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder1;

architecture bhv of decoder1 is

begin

process(a)
begin
if (a=”00″) then
b <= “0001”;
elsif (a=”01″) then
b <= “0010”;
elsif (a=”10″) then
b <= “0100”;
else
b <= “1000”;
end if;
end process;

end bhv;

3. 2 to 4 decoder using case statement

entity decoder is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder;
architecture bhv of decoder is
begin

process(a)
begin
case a is
when “00” => b <= “0001”; when “01” => b <= “0010”; when “10” => b <=
“0100”; when “11” => b <= “1000”;
end case;
end process;

end bhv;

Waveform:-

Result :- This is 2 to 4 Decoder.