Assignment -2,subject:VLSI DESIGN ,SUB Code: 20EC C23 , VI SEM,ECE -E1,

submission date:29.04.2023, Deadline for submission:4.05.2023

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Answer any 6 questions from 1 to 11 questions and 12 to 25 compulsory MAX:100

Total :Min 20 questions out of 25

S. STEM CO BTL
no
1 Describe constructional features and performance characteristic of Pseudo- NMOS logic and 4 4
2 a. Derive pull up to pull down ratio for an NMOS inverter driven by another NMOS inverter. 4 1
b. Derive pull up to pull down ratio for an NMOS inverter driven by one or more pass transistors.
3 Clearly explain about ION-IMPLANTATION step in IC fabrication 3 2
4 Define Chemical Vapor Deposition 3 5
5 Draw circuit diagram of Bi-CMOS 2-input NAND gate 4 4
6 Define charge leakage in DRAM 5 2
5 Explain the NMOS &CMOS fabrication procedure 3 2
6 Design an area efficient layout diagram for the CMOS logic shown below Y = (A + B + C). 4 4
7 Explain various steps involved in photo lithography 5 4
8 Explain the design of MOS inverter with different loads 4 4
9 a) Realize XOR and XNOR circuits using transmission gates. b) transmission gates compared to pass txr 4 5
11 Draw the circuit diagrams and the corresponding stick diagrams for nMOS and CMOS inverters 4 2
12 Explain the Ion Implantation system in detail? 3 4
13 Design a D-FF using Transmission gate logic? 4 3
14 a) Compare SRAM and DRAM , b) Explain read and write operation of 3T DRAM 4 4
15 Explain read and write operations of 6T SRAM cell 5 2
Find the test vector for the following circuit using path sensitization method when path 3 is struck at 0. 5 3

16 Define controllability and observability 5 2

17 Draw the symbolic layout for the CMOS inverter and write the general CMOS logic gate layout 4 2
guidelines
18 Fault models (stuck-at 1 and stuck – at-0)-Path sensitization 5 5
19 What is the need of testability? Explain design for testability 5 4
20 Write a short note MOS layers and symbolic diagram translation to MASK form 3 4
21 A)Explain different forms of pull-ups used as load in CMOS enhancement. 4 2
B) Determine pull-up to pull-down ratio of an NMOS inverter when driven through one or more pass
transistors. 4 5
22 A) What is stick diagram and explain about different symbols used for components in Stick diagram. 3 4
Draw the stick and layout for a two input CMOS NAND gate
B) Design a stick diagram and layout for two input CMOS NAND gate indicating all the regions and
layers 4 5
23 a)Draw and explain the BiCMOS inverter, Bi-Cmos NAND & Bi-CMOS two-input NOR gates 3 2
b) Draw and explain NOR and NAND based ROM memory design
24 a)Draw and explain AND/OR representation of PLA b)Explain the challenges in testing of VLSI design 5 1
25 a)Explain the D-Algorithm with example b) Describe the ASIC and SOC 5 4